Texas Instruments | ISO734x-Q1 Robust EMC, Low-Power, Quad-Channel Digital Isolators (Rev. B) | Datasheet | Texas Instruments ISO734x-Q1 Robust EMC, Low-Power, Quad-Channel Digital Isolators (Rev. B) Datasheet

Texas Instruments ISO734x-Q1 Robust EMC, Low-Power, Quad-Channel Digital Isolators (Rev. B) Datasheet
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ISO7340-Q1, ISO7341-Q1, ISO7342-Q1
SLLSEK5B – JULY 2015 – REVISED MAY 2017
ISO734x-Q1 Robust EMC, Low-Power, Quad-Channel Digital Isolators
1 Features
2 Applications
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM Classification Level 3A
– Device CDM Classification Level C6
Signaling Rate: 25 Mbps
Integrated Noise Filter on the Inputs
Default Output High and Low Options
Low Power Consumption, Typical ICC per Channel
at 1 Mbps:
– ISO7340-Q1: 0.9 mA (5-V Supplies),
0.7 mA (3.3-V Supplies)
– ISO7341-Q1: 1.2 mA (5-V Supplies),
0.9 mA (3.3-V Supplies)
– ISO7342-Q1: 1.3 mA (5-V Supplies),
0.9 mA (3.3-V Supplies)
Low Propagation Delay: 31 ns
Typical (5-V Supplies)
3.3-V and 5-V Level Translation
70-KV/μs Transient Immunity, Typical (5-V
Supplies)
Robust Electromagnetic Compatibility (EMC)
– System-level ESD, EFT, and Surge Immunity
– Low Emissions
Operates from 3.3-V and 5-V Supplies
Wide-Body SOIC-16 Package
Safety-Related Certifications:
– 4242-VPK Basic Isolation per DIN V VDE V
0884-10 and DIN EN 61010-1
– 3-KVRMS Isolation for 1 minute per UL 1577
– CSA Component Acceptance Notice 5A, IEC
60950-1 and IEC 61010-1 End Equipment
Standards
– GB4943.1-2011 CQC Certified
Optocoupler Replacement in:
– Industrial Fieldbus
– Profibus
– Modbus
– DeviceNet Data Buses
– Servo Control Interface
– Motor Control
– Power Supplies
– Battery Packs
3 Description
The ISO734x-Q1 family of devices provides galvanic
isolation up to 3000 VRMS for 1 minute per UL 1577
and 4242 VPK per VDE V 0884-10. These devices
have four isolated channels comprised of logic input
and output buffers separated by a silicon dioxide
(SiO2) insulation barrier.
The ISO7340-Q1 device has four channels in forward
direction, the ISO7341-Q1 device has three forward
and one reverse-direction channels, and the
ISO7342-Q1 device has two forward and two reversedirection channels. In case of input power or signal
loss, the default output is low for orderable part
numbers with suffix F and high for orderable part
numbers without suffix F. See the Device Functional
Modes section for further details.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE
ISO7340-Q1
ISO7341-Q1
SOIC (16)
10.30 mm × 7.50 mm
ISO7342-Q1
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
VCCI
Isolation
Capacitor
VCCO
INx
OUTx
ENx
GNDI
GNDO
VCCI and GNDI are supply and ground
connections respectively for the input
channels.
VCCO and GNDO are supply and ground
connections respectively for the output.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7340-Q1, ISO7341-Q1, ISO7342-Q1
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
1
1
1
2
3
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings ............................................................ 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Power Ratings........................................................... 6
Insulation Specifications............................................ 7
Safety-Related Certifications..................................... 8
Safety Limiting Values .............................................. 8
Electrical Characteristics—5-V Supply ..................... 9
Supply Current Characteristics—5-V Supply .......... 9
Electrical Characteristics—3.3-V Supply .............. 10
Supply Current Characteristics—3.3-V Supply ..... 10
Switching Characteristics—5-V Supply................. 11
Switching Characteristics—3.3-V Supply.............. 11
Insulation Characteristics Curves ......................... 12
Typical Characteristics .......................................... 13
8
9
Parameter Measurement Information ................ 15
Detailed Description ............................................ 17
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
17
17
18
19
10 Application and Implementation........................ 20
10.1 Application Information.......................................... 20
10.2 Typical Application ................................................ 20
11 Power Supply Recommendations ..................... 24
12 Layout................................................................... 25
12.1 Layout Guidelines ................................................. 25
12.2 Layout Example .................................................... 25
13 Device and Documentation Support ................. 26
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
26
14 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (August 2016) to Revision B
•
Page
Deleted Reinforced from the data sheet title .......................................................................................................................... 1
Changes from Original (July 2016) to Revision A
Page
•
CQC certification is now certified instead of planned ............................................................................................................. 1
•
Changed the minimum air gap (clearance) parameter (L(I01)) to the external clearance parameter.................................... 7
•
Changed the minimum external tracking (creepage) parameter (L(I02)) to the external creepage parameter...................... 7
•
Changed the input-to-output test voltage parameter (VPR) to the apparent charge parameter (qpd)...................................... 7
•
Changed the typ value for the enable propagation delay, high impedance-to-high output parameter of the FC
devices and the typ value for the enable propagation delay, high impedance-to-low output parameter of the C
devices from 16 to 16000 in the Switching Characteristics—3.3-V Supply table................................................................. 11
•
Added the Receiving Notification of Documentation Updates section ................................................................................ 26
2
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5 Description (continued)
Used in conjunction with isolated power supplies, these devices help prevent noise currents on a data bus or
other circuits from entering the local ground and interfering with or damaging sensitive circuitry. The ISO734x-Q1
device has integrated noise filter for harsh industrial environment where short noise pulses may be present at the
device input pins. The ISO734x-Q1 device has TTL input thresholds and operates from 3-V to 5.5-V supply
levels. Through innovative chip design and layout techniques, electromagnetic compatibility of the ISO734x-Q1
family of devices has been significantly enhanced to enable system-level ESD, EFT, surge, and emissions
compliance.
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6 Pin Configuration and Functions
DW Package
16-Pin SOIC
ISO7340-Q1 Top View
DW Package
16-Pin SOIC
ISO7341-Q1 Top View
VCC1
GND1
1
16
VCC1
GND1
16
15
VCC2
GND2
1
2
2
15
VCC2
GND2
INA
3
14
OUTA
INA
3
14
OUTA
INB
4
13
OUTB
INB
4
13
OUTB
INC
5
12
OUTC
5
12
OUTC
IND
6
11
OUTD
INC
OUTD
6
11
IND
NC
7
10
EN
7
10
GND1
8
9
EN1
GND1
8
9
EN2
GND2
GND2
DW Package
16-Pin SOIC
ISO7342-Q1 Top View
VCC1
1
16
VCC2
GND1
2
15
GND2
INA
3
14
OUTA
INB
4
13
OUTB
OUTC
5
12
INC
OUTD
6
11
IND
EN1
7
10
EN2
GND1
8
9
GND2
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
ISO7340-Q1
ISO7341-Q1
ISO7342-Q1
EN
10
—
—
I
Output enable. All output pins are enabled when EN is high or
disconnected and disabled when EN is low.
EN1
—
7
7
I
Output enable 1. Output pins on side-1 are enabled when EN1 is
high or disconnected and disabled when EN1 is low.
EN2
—
10
10
I
Output enable 2. Output pins on side-2 are enabled when EN2 is
high or disconnected and disabled when EN2 is low.
2
2
2
8
8
8
GND1
—
Ground connection for VCC1
—
Ground connection for VCC2
9
9
9
15
15
15
INA
3
3
3
I
Input, channel A
INB
4
4
4
I
Input, channel B
INC
5
5
12
I
Input, channel C
IND
6
11
11
I
Input, channel D
NC
7
—
—
—
No connect pins are floating with no internal connection
OUTA
14
14
14
O
Output, channel A
OUTB
13
13
13
O
Output, channel B
OUTC
12
12
5
O
Output, channel C
OUTD
11
6
6
O
Output, channel D
VCC1
1
1
1
—
Power supply, VCC1
VCC2
16
16
16
—
Power supply, VCC2
GND2
4
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7 Specifications
7.1 Absolute Maximum Ratings
See
(1)
Supply voltage (2)
VCC
VCC1, VCC2
Voltage
INx, OUTx, ENx
MIN
MAX
–0.5
6
–0.5
UNIT
V
VCC + 0.5
(3)
V
IO
Output current
±15
mA
TJ
Maximum junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
Maximum voltage must not exceed 6 V.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±4000
Charged-device model (CDM), per AEC Q100-011
±1500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
MIN
NOM
UNIT
Supply voltage
IOH
High-level output current
IOL
Low-level output current
VIH
High-level input voltage
2
5.5
V
VIL
Low-level input voltage
0
0.8
V
tui
Input pulse duration
1 / tui
Signaling rate
25
Mbps
TJ
Junction temperature (1)
136
°C
TA
Ambient temperature
125
°C
(1)
3
MAX
VCC1, VCC2
5.5
–4
V
mA
4
mA
40
ns
0
–40
25
To maintain the recommended operating conditions for TJ, see the Thermal Information table.
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7.4 Thermal Information
ISO734x-Q1
THERMAL METRIC (1)
DW (SOIC)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
78.4
°C/W
RθJC(top)
RθJB
Junction-to-case(top) thermal resistance
41
°C/W
Junction-to-board thermal resistance
43
ψJT
°C/W
Junction-to-top characterization parameter
15.6
°C/W
ψJB
Junction-to-board characterization parameter
42.5
°C/W
RθJC(bottom)
Junction-to-case(bottom) thermal resistance
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 12.5-MHz 50% duty cycle square wave
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
PD
Maximum power dissipation by both sides of ISO7340-Q1
92
PD1
Maximum power dissipation by side-1 of ISO7340-Q1
24
PD2
Maximum power dissipation by side-2 of ISO7340-Q1
68
PD
Maximum power dissipation by both sides of ISO7341-Q1
PD1
Maximum power dissipation by side-1 of ISO7341-Q1
42
PD2
Maximum power dissipation by side-2 of ISO7341-Q1
60
PD
Maximum power dissipation by both sides of ISO7342-Q1
111
PD1
Maximum power dissipation by side-1 of ISO7342-Q1
55.5
PD2
Maximum power dissipation by side-2 of ISO7342-Q1
55.5
6
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mW
102
mW
mW
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7.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
External clearance (1)
Shortest terminal-to-terminal distance through air
>8
mm
CPG
External creepage (1)
Shortest terminal-to-terminal distance across the
package surface
>8
mm
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
>13
µm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
>400
V
Rated mains voltage ≤ 300 VRMS
I–IV
Rated mains voltage ≤ 600 VRMS
I–III
Rated mains voltage ≤ 1000 VRMS
I-II
CLR
Material group
II
Overvoltage Category
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 (2)
VIORM
Maximum repetitive peak isolation voltage AC voltage (bipolar)
VIOTM
Maximum transient isolation voltage
VTEST = VIOTM;
t = 60 s (qualification); t = 1 s (100% production)
VIOSM
Maximum surge isolation voltage (3)
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.3 × VIOSM = 7800 VPK (qualification)
qpd
Apparent charge
(4)
Barrier capacitance, input to output (5)
CIO
Isolation resistance, input to output (5)
RIO
1414
VPK
4242
VPK
6000
VPK
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM = 1697 VPK, tm = 10 s
≤5
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM = 2262 VPK, tm = 10 s
≤5
Method b1: At routine test (100% production) and
preconditioning (type test) Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM = 2651 VPK, tm = 1 s (100%
production)
≤5
VIO = 0.4 sin (2πft), f = 1 MHz
2.4
VIO = 500 V, TA = 25°C
>1012
VIO = 500 V, 100°C ≤ TA ≤ x°C
>1011
VIO = 500 V at TS = 150°C
>109
Pollution degree
2
Climatic category
40/125/21
pC
pF
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
VTEST = VISO = 3000 VRMS, t = 60 s (qualification);
VTEST = 1.2 × VISO = 3600 VRMS, t = 1 s (100%
production)
Withstand isolation voltage
3000
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall
be ensured by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device
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7.7 Safety-Related Certifications
VDE
CSA
Certified according to DIN V VDE V 0884-10
Approved under CSA Component
(VDE V 0884-10):2006-12 and DIN EN 61010- Acceptance Notice 5A, IEC 60950-1, and
1 (VDE 0411-1):2011-07
IEC 61010-1
UL
CQC
Recognized component under
UL 1577
Certified according to
GB4943.1-2011
Basic Insulation;
Maximum Transient Overvoltage, 4242 VPK;
Maximum Surge Isolation Voltage, 6000 VPK;
Maximum Repetitive Peak Isolation Voltage,
1414 VPK
800 VRMS Basic Insulation and 400 VRMS
Reinforced Insulation working voltage per
CSA 60950-1-07+A1+A2 and IEC 60950-1
2nd Ed.+A1+A2;
300 VRMS Basic Insulation working voltage
per CSA 61010-1-12 and IEC 61010-1 3rd
Ed.
Single protection, 3000 VRMS
Reinforced Insulation, Altitude ≤
5000 m, Tropical Climate, 250
VRMS maximum working voltage
Certificate number: 40016131
Master contract number: 220991
File number: E181974
Certificate number:
CQC15001121716
7.8 Safety Limiting Values
Safety limiting (1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure
of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
IS
TS
(1)
8
TEST CONDITIONS
Safety input, output, or supply
current
MIN
TYP
MAX
RθJA = 78.4 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C,
see Figure 1
290
RθJA = 78.4 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C,
see Figure 1
443
Safety temperature
UNIT
mA
150
The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air
thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air
thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount
packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient
temperature plus the power times the junction-to-air thermal resistance.
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7.9 Electrical Characteristics—5-V Supply
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
IOH = –4 mA; see Figure 14
TEST CONDITIONS
VCCO (1) – 0.5
4.7
IOH = –20 μA; see Figure 14
VCCO (1) – 0.1
5
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage
hysteresis
IIH
High-level input current
VIH = VCC at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
CMTI
Common-mode transient
immunity
VI = VCC or 0 V; see Figure 17
CI
Input capacitance (2)
VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V
(1)
(2)
MAX
UNIT
V
IOL = 4 mA; see Figure 14
0.2
0.4
IOL = 20 μA; see Figure 14
0
0.1
V
480
mV
10
μA
–10
μA
25
70
kV/μs
3.4
pF
VCCO is supply voltage, VCC1 or VCC2, for the output channel being measured.
Measured from input pin to ground.
7.10 Supply Current Characteristics—5-V Supply
All inputs switching with square wave clock signal for dynamic ICC measurement. VCC1 and VCC2 at 5 V ± 10% (over
recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUPPLY
CURRENT
MIN
TYP
MAX
ICC1
0.6
1.4
ICC2
0.4
0.8
ICC1
0.6
1.4
ICC2
3.2
4.8
ICC1
1.4
2.3
ICC2
5.6
7.1
ICC1
2.7
4
ICC2
9.3
12
ICC1
0.8
1.8
ICC2
0.7
1.3
ICC1
2
3.2
ICC2
2.9
4.4
ICC1
3.2
4.5
ICC2
4.9
6.5
ICC1
5
7
ICC2
7.8
11
Disable
ICC1, ICC2
0.7
1.6
DC to 1 Mbps
ICC1, ICC2
2.5
4
10 Mbps
ICC1, ICC2
4.1
5.6
25 Mbps
ICC1, ICC2
6.4
9
UNIT
ISO7340-Q1
EN = 0 V
Disable
DC to 1 Mbps
Supply current
DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with
square wave clock input; CL = 15 pF
10 Mbps
25 Mbps
mA
ISO7341-Q1
EN1 = EN2 = 0 V
Disable
DC to 1 Mbps
Supply current
DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with
square wave clock input; CL = 15 pF
10 Mbps
25 Mbps
mA
ISO7342-Q1
EN1 = EN2 = 0 V
Supply current
DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with
square wave clock input; CL = 15 pF
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7.11 Electrical Characteristics—3.3-V Supply
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
IOH = –4 mA; see Figure 14
TEST CONDITIONS
VCCO (1) – 0.5
3
IOH = –20 μA; see Figure 14
VCCO (1) – 0.1
3.3
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage
hysteresis
IIH
High-level input current
VIH = VCC at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
CMTI
Common-mode transient
immunity
VI = VCC or 0 V; see Figure 17
(1)
MAX
UNIT
V
IOL = 4 mA; see Figure 14
0.2
0.4
IOL = 20 μA; see Figure 14
0
0.1
V
450
mV
10
μA
–10
μA
25
50
kV/μs
VCCO is supply voltage, VCC1 or VCC2, for the output channel being measured.
7.12 Supply Current Characteristics—3.3-V Supply
All inputs switching with square wave clock signal for dynamic ICC measurement. VCC1 and VCC2 at 3.3 V ± 10% (over
recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUPPLY
CURRENT
MIN
TYP
MAX
ICC1
0.4
0.7
ICC2
0.3
0.6
ICC1
0.4
0.7
ICC2
2.3
3.6
ICC1
0.9
1.3
ICC2
3.9
5.1
ICC1
1.6
2.4
ICC2
6.3
8
ICC1
0.6
1
ICC2
0.5
0.8
ICC1
1.4
2.3
ICC2
2.2
3.2
ICC1
2.2
3
ICC2
3.4
4.5
ICC1
3.3
4.7
ICC2
5.2
7.2
Disable
ICC1, ICC2
0.5
0.9
DC to 1 Mbps
ICC1, ICC2
1.8
2.8
10 Mbps
ICC1, ICC2
2.8
4
25 Mbps
ICC1, ICC2
4.3
5.8
UNIT
ISO7340-Q1
EN = 0 V
Disable
DC to 1 Mbps
Supply current
DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with
square wave clock input; CL = 15 pF
10 Mbps
25 Mbps
mA
ISO7341-Q1
EN1 = EN2 = 0 V
Disable
DC to 1 Mbps
Supply current
DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with
square wave clock input; CL = 15 pF
10 Mbps
25 Mbps
mA
ISO7342-Q1
EN1 = EN2 = 0 V
Supply current
10
DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with
square wave clock input; CL = 15 pF
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mA
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7.13 Switching Characteristics—5-V Supply
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse width distortion |tPHL – tPLH|
TEST CONDITIONS
MIN
TYP
MAX
20
31
58
ns
4
ns
Same-direction Channels
2.5
ns
Opposite-direction Channels
17
ns
23
ns
See Figure 14
UNIT
tsk(o) (2)
Channel-to-channel output skew time
tsk(pp) (3)
Part-to-part skew time
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Disable propagation delay, high-to-high impedance output
7
13
ns
tPLZ
Disable propagation delay, low-to-high impedance output
7
13
ns
7
13
15000
23000 (4)
15000
23000 (4)
7
13
tfs
(3)
(4)
ISO734xFCQDWQ1 and
ISO734xFCQDWRQ1
ns
ns
See Figure 15
ISO734xCQDWQ1 and
ISO734xCQDWRQ1
ns
ISO734xFCQDWQ1 and
ISO734xFCQDWRQ1
Fail-safe output delay time from input power loss
ns
1.7
ISO734xCQDWQ1 and
ISO734xCQDWRQ1
Enable propagation delay, high
impedance-to-low output
tPZL
(1)
(2)
See Figure 14
Enable propagation delay, high
impedance-to-high output
tPZH
2.1
See Figure 16
9.4
μs
Also known as Pulse Skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
The enable signal rate should be ≤ 43 Kbps.
7.14 Switching Characteristics—3.3-V Supply
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse width distortion |tPHL – tPLH|
tsk(o)
(2)
tsk(pp)
(3)
TEST CONDITIONS
See Figure 14
MIN
TYP
MAX
22
35
66
2.5
Same-direction Channels
Channel-to-channel output skew time
3
Opposite-direction Channels
Part-to-part skew time
28
Output signal rise time
tf
Output signal fall time
tPHZ
Disable propagation delay, high-to-high impedance output
9
18
tPLZ
Disable propagation delay, low-to-high impedance output
9
18
9
18
16000
24000 (4)
16000
24000 (4)
9
18
tPZL
tfs
(1)
(2)
(3)
(4)
ns
16
tr
tPZH
UNIT
2.8
See Figure 14
Enable propagation delay, high impedanceto-high output
Enable propagation delay, high impedanceto-low output
ISO734xCQDWQ1 and
ISO734xCQDWRQ1
ISO734xFCQDWQ1 and
ISO734xFCQDWRQ1
See Figure 15
ISO734xCQDWQ1 and
ISO734xCQDWRQ1
ISO734xFCQDWQ1 and
ISO734xFCQDWRQ1
Fail-safe output delay time from input power loss
ns
2.1
See Figure 16
9.4
ns
μs
Also known as Pulse Skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
The enable signal rate should be ≤ 45 Kbps.
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7.15 Insulation Characteristics Curves
500
Safety Limiting Current (mA)
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
400
300
200
100
0
0
50
100
150
Ambient Temperature (qC)
200
D001
Figure 1. Thermal Derating Curve for Limiting Current per VDE
12
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7.16 Typical Characteristics
6
10
ICC2 at 5 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC1 at 3.3 V
Supply Current (mA)
8
ICC2 at 5 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC1 at 3.3 V
5
Supply Current (mA)
9
7
6
5
4
3
2
4
3
2
1
1
0
0
0
5
10
TA = 25°C
15
20
Data Rate (Mbps)
25
0
30
CL = 15 pF
10
15
20
Data Rate (Mbps)
TA = 25°C
Figure 2. ISO7340-Q1 Supply Current vs Data Rate
(15-pF Load)
25
30
D001
CL = No Load
Figure 3. ISO7340-Q1 Supply Current vs Data Rate
(No Load)
6
9
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
7
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
5
Supply Current (mA)
8
Supply Current (mA)
5
D001
6
5
4
3
4
3
2
2
1
1
0
0
0
5
10
TA = 25°C
15
20
Data Rate (Mbps)
25
30
0
5
D001
CL = 15 pF
10
15
20
Data Rate (Mbps)
TA = 25°C
Figure 4. ISO7341x-Q1 Supply Current vs Data Rate
(15-pF Load)
25
30
D001
CL = No Load
Figure 5. ISO7341x-Q1 Supply Current vs Data Rate
(No Load)
7
5
4.5
6
Supply Current (mA)
Supply Current (mA)
4
5
4
3
2
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
1
3.5
3
2.5
2
1.5
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
1
0.5
0
0
0
5
TA = 25°C
10
15
20
Data Rate (Mbps)
25
30
CL = 15 pF
Figure 6. ISO7342x-Q1 Supply Current vs Data Rate
(15-pF Load)
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0
5
D001
10
15
20
Data Rate (Mbps)
TA = 25°C
25
30
D002
CL = No Load
Figure 7. ISO7342x-Q1 Supply Current vs Data Rate
(No Load)
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Typical Characteristics (continued)
6
0.9
Low-Level Output Voltage (V)
High-Level Output Voltage (V)
0.8
5
4
3
2
1
VCC at 3.3 V
VCC at 5 V
0
-15
0.7
0.6
0.5
0.4
0.3
0.2
VCC at 3.3 V
VCC at 5 V
0.1
0
-10
-5
High-Level Output Current (mA)
0
0
TA = 25°C
40
Propagation Delay Time (ns)
Power Supply Under-Voltage Threshold (V)
42
VCC Rising
VCC Falling
2.42
2.4
2.38
2.36
2.34
38
36
34
32
tPHL at 3.3 V
tPHL at 5 V
tPLH at 3.3 V
tPLH at 5 V
30
2.32
-50
0
50
100
Free-Air Temperature (qC)
28
-40
150
0
27
120
Pk-Pk Output Jitter (ps)
140
25
23
21
19
20
40
60
80
100
Free-Air Temperature (qC)
140
D006
100
80
60
40
20
tGS at 3.3 V
tGS at 5 V
120
Figure 11. Propagation Delay Time vs Free-Air Temperature
29
17
-20
D005
Figure 10. Power Supply Undervoltage Threshold vs FreeAir Temperature
Input Glitch Suppression Time (ns)
D004
Figure 9. Low-Level Output Voltage vs Low-Level Output
Current
2.46
15
-40
15
TA = 25°C
Figure 8. High-Level Output Voltage vs High-level Output
Current
2.44
5
10
Low-Level Output Current (mA)
D003
Output Jitter at 3.3 V
Output Jitter at 5 V
0
-5
30
65
Free-Air Temperature (qC)
100
135
0
5
D007
10
15
Data Rate (Mbps)
20
25
D008
TA = 25°C
Figure 12. Input Glitch Suppression Time vs Free-Air
Temperature
14
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Figure 13. Output Jitter vs Data Rate
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ISOLATION BARRIER
8 Parameter Measurement Information
IN
Input
Generator
See Note A
50 Ω
VI
VCCI
VI
VCC/2
OUT
VCC/2
0V
tPHL
tPLH
VO
CL
See Note B
VOH
90%
VO
50%
10%
tf
tr
50%
VOL
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in
actual application.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 14. Switching Characteristics Test Circuit and Voltage Waveforms
VCC
0V
ISOLATION BARRIER
VCC
IN
VI
IN
3V
EN
Input
Generator
See Note A
VI
VO
0V
tPLZ
tPZL
VO
CL
See
Note B
VCC/2
VCC/2
VI
OUT
VCC
0.5 V
50%
VOL
50 Ω
ISOLATION BARRIER
Input
Generator
See Note A
R L = 1 kΩ ± 1%
VCC
OUT
VO
VCC/2
VI
VCC/2
0V
EN
CL
See
Note B
50 Ω
tPZH
R L = 1 kΩ ± 1%
VOH
50%
VO
0.5 V
tPHZ
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
0V
Figure 15. Enable/Disable Propagation Delay Time Test Circuit and Waveform
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Parameter Measurement Information (continued)
VI
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
A.
VCC
ISOLATION BARRIER
VCC
IN
2.7 V
VI
OUT
0V
tfs
VO
fs high
VO
CL
See Note A
VOH
50%
fs low V
OL
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 16. Failsafe Delay Time Test Circuit and Voltage Waveforms
IN
S1
C = 0.1 µF ±1%
Isolation Barrier
VCCI
GNDI
VCCO
C = 0.1 µF ±1%
Pass-fail criteria –
output must remain
stable.
OUT
+
CL
See Note A
GNDO
VOH or VOL
–
+ VCM –
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 17. Common-Mode Transient Immunity Test Circuit
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9 Detailed Description
9.1 Overview
The isolator in Figure 18 is based on a capacitive isolation-barrier technique. The I/O channel of the device
consists of two internal data channels, a high-frequency (HF) channel with a bandwidth from 100 kbps up to 25
Mbps, and a low-frequency (LF) channel covering the range from 100 kbps down to DC.
In principle, a single-ended input signal entering the HF channel is split into a differential signal through the
inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transient pulses,
which then are converted into CMOS levels by a comparator. The transient pulses at the input of the comparator
can be either above or below the common-mode voltage VREF depending on whether the input bit transitioned
from 0 to 1 or 1 to 0. The comparator threshold is adjusted based on the expected bit transition. A decision logic
(DCL) at the output of the HF channel comparator measures the durations between signal transients. If the
duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency
signal), the DCL forces the output-multiplexer to switch from the high-frequency to the low-frequency channel.
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these
signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a
sufficiently high frequency, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter
(LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output
multiplexer.
9.2 Functional Block Diagram
Isolation Barrier
OSC
Low t Frequency
Channel
(DC...100 kbps)
PWM
VREF
LPF
0
Polarity and Threshold
Selection
IN
OUT
1 S
High t Frequency
Channel
(100 kbps...25 Mbps)
DCL
VREF
Polarity and Threshold Selection
Figure 18. Conceptual Block Diagram of a Digital Capacitive Isolator
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9.3 Feature Description
The ISO734x-Q1 family of devices are available in multiple channel configurations and default output state
options to enable wide variety of application uses.
ORDERABLE DEVICE
ISO7340CQDWQ1 and
ISO7340CQDWRQ1
ISO7340FCQDWQ1 and
ISO7340FCQDWRQ1
ISO7341CQDWQ1 and
ISO7341CQDWRQ1
ISO7341FCQDWQ1 and
ISO7341FCQDWRQ1
ISO7342CQDWQ1 and
ISO7342CQDWRQ1
ISO7342FCQDWQ1 and
ISO7342FCQDWRQ1
(1)
CHANNEL DIRECTION
RATED ISOLATION
MAXIMUM DATA RATE
High
4 Forward,
0 Reverse
3 Forward,
1 Reverse
DEFAULT OUTPUT
Low
High
3000 VRMS / 4242 VPK (1)
25 Mbps
Low
High
2 Forward,
2 Reverse
Low
See the Safety-Related Certifications section for detailed isolation ratings.
9.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge, and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO734xQ1 family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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9.4 Device Functional Modes
Table 1 lists the functional modes for the ISO734x-Q1 family of devices.
Table 1. Function Table (1)
VCCI
VCCO
PU
(1)
(2)
(3)
INPUT
(INx)
OUTPUT ENABLE
(ENx)
H
L
PU
OUTPUT
(OUTx)
ISO734xCQDWQ1 AND
ISO734xCQDWRQ1
ISO734xFCQDWQ1 AND
ISO734xFCQDWRQ1
H or Open
H
H
H or Open
L
L
X
L
Z
Z
Open
H or Open
H (2)
L (3)
PD
PU
X
H or Open
H (2)
L (3)
X
PU
X
L
Z
Z
X
PD
X
X
Undetermined
Undetermined
VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 3 V); PD = Powered down (VCC ≤ 2.1 V); X = Irrelevant; H =
High level; L = Low level ; Z = High Impedance
In fail-safe condition, output defaults to high level
In fail-safe condition, output defaults to low level
9.4.1 Device I/O Schematics
Input (Devices Without Suffix F)
VCCI
VCCI
Input (Devices With Suffix F)
VCCI
VCCI
VCCI
VCCI
VCCI
5 mA
500 W
500 W
INx
INx
5 mA
Output
Enable
VCCO
VCCO
VCCO VCCO
VCCO
5 mA
500 W
40 W
OUTx
ENx
Figure 19. Device I/O Schematics
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The ISO734x-Q1 family of devices use single-ended TTL-logic switching technology. The supply voltage range is
from 3 V to 5.5 V for both supplies, VCC1 and VCC2. When designing with digital isolators, keep in mind that
because of the single-ended design structure, digital isolators do not conform to any specific interface standard
and are only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed
between the data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the
interface type or standard.
10.2 Typical Application
10.2.1 Isolated Data Acquisition System for Process Control
The -Q1 family of devices combined with Texas Instruments' precision analog-to-digital converter and mixed
signal micro-controller can create an advanced isolated data acquisition system as shown in Figure 20.
ISO-BARRIER
5VISO
5VISO
0.1 F
22
AVDD
11
RTD
12
Bridge
17
0.1 F
DVDD
AIN1+
A0
AIN1±
A1
AIN2+
DOUT
13
14
16
Current
shunt
15
14
7
13
27
12
28
11
5VISO
AIN2±
AIN3+
REF±
9,15
5VISO
GAIN0
GAIN1
AIN4+
SPEED
AIN4±
PWDN
AGND
21
VCC2
VCC1
EN2
EN1
OUTA
OUTB
INA
ISO7341
OUTC
INB
INC
IND
OUTD
GND2
GND1
19
16
0.1 F
10
23
14
24
13
25
12
26
11
9,15
DGND
VCC1
VCC2
EN
NC
OUTA
OUTB
INA
ISO7340
INB
OUTC
INC
OUTD
IND
GND2
GND1
3.3 V
0.1 F
1
7
2
0.1 F
3
11
4
12
5
14
6
13
P3.0
DVcc
3.3 V
CLK
MSP430
F2132
SOMI
XIN
P3.7
P3.6
15
P3.4
5
P3.5
6
18
17
16
DVss
1
7
XOUT
P3.1
2,8
20
0.1 F
AIN3±
10
8
ADS1234
REF+
Thermo
couple
3.3 V
16
1
SCLK
18
5VISO
0.1 F
0.1 F
4
3
4
5
6
2,8
2
Figure 20. Isolated Data-Acquisition System for Process Control
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Typical Application (continued)
10.2.1.1 Design Requirements
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO734-Q1 family of devices only requires two external bypass capacitors to operate.
10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Typical Supply Current Equations
For the equations in this section, the following is true:
• ICC1 and ICC2 are typical supply currents measured in mA
• f is data rate measured in Mbps
• CL is the capacitive load measured in pF
10.2.1.2.1.1 ISO7340-Q1
At VCC1 = VCC2 = 5 V:
ICC1 = 0.54366 + (0.0873 × f)
ICC2 = 2.74567 + (0.08433 × f) + (0.01 × f × CL)
(1)
(2)
At VCC1 = VCC2 = 3.3 V:
ICC1 = 0.3437 + (0.04922 × f)
ICC2 = 2.1068 + (0.04374 × f) + (0.007045 × f × CL)
(3)
(4)
10.2.1.2.1.2 ISO7341-Q1
At VCC1 = VCC2 = 5 V:
ICC1 = 1.7403 + (0.1006 × f) + (0.001711 × f × CL)
ICC2 = 2.502 + (0.09629 × f) + (0.00687 × f × CL)
(5)
(6)
At VCC1 = VCC2 = 3.3 V:
ICC1 = 1.2915 + (0.046 × f) + (0.00185 × f × CL)
ICC2 = 1.8833 + (0.0566 × f) + (0.004514 × f × CL)
(7)
(8)
10.2.1.2.1.3 ISO7342-Q1
At VCC1 = VCC2 = 5 V:
ICC1, ICC2 = 2.1254 + (0.08694 × f) + (0.004868 × f × CL)
(9)
At VCC1 = VCC2 = 3.3 V:
ICC1, ICC2 = 1.5912 + (0.0410 × f) + (0.003785 × f × CL)
2 mm max
from VCC1
(10)
2 mm max
from VCC2
ISO7340
0.1 µF
2 mm max
from VCC1
0.1 µF
ISO7341
0.1 µF
VCC1
16
2
15
INA
3
14
OUTA
INB
4
13
OUTB
INC
5
12
OUTC
IND
6
11
OUTD
7
10
0.1 µF
16
2
15
INA
3
14
OUTA
INB
4
13
OUTB
INC
5
12
OUTD
6
11
7
10
8
9
GND1
GND1
NC
GND2
EN
8
9
GND2
GND1
Figure 21. Typical ISO7340-Q1 Circuit Hook-up
Copyright © 2015–2017, Texas Instruments Incorporated
VCC2
1
VCC2
1
VCC1
2 mm max
from VCC2
GND2
OUTC
IND
EN2
EN1
GND1
GND2
Figure 22. Typical ISO7341-Q1 Circuit Hook-up
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Typical Application (continued)
2 mm max
from VCC1
2 mm max
from VCC2
ISO7342
0.1 µF
VCC1
0.1 µF
VCC2
1
16
2
15
INA
3
14
OUTA
INB
4
13
OUTB
OUTC
5
12
INC
OUTD
6
11
IND
7
10
8
9
GND1
GND2
EN2
EN1
GND1
GND2
Figure 23. Typical ISO7342-Q1 Circuit Hook-up
10.2.1.3 Application Curves
The typical eye diagrams of the ISO734x-Q1 family of devices indicate low jitter and a wide open eye at the
maximum data rate of 25 Mbps.
Figure 24. Eye Diagram at 25 Mbps, 5 V and 25°C
22
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Figure 25. Eye Diagram at 25 Mbps, 3.3 V and 25°C
Copyright © 2015–2017, Texas Instruments Incorporated
Product Folder Links: ISO7340-Q1 ISO7341-Q1 ISO7342-Q1
ISO7340-Q1, ISO7341-Q1, ISO7342-Q1
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SLLSEK5B – JULY 2015 – REVISED MAY 2017
Typical Application (continued)
10.2.2 Typical Application for Module With 16 Inputs
The ISO7341x-Q1 device and several other components from Texas Instruments can be used to create an
isolated serial peripheral interface (SPI) for input module with 16 inputs.
VS
3.3 V
0.1 F
2
VCC D2 3
MBR0520L
1:1.33
4
SN6501
10 F
GND D1
0.1 F
1
IN
OUT
1
TLV70733
3
EN
GND
2
3.3VISO
10 F
2
10 F
4, 5
MBR0520L
1 F
VIN
VOUT
6
22 F
REF5025
4
GND
ISO-BARRIER
0.1 F
0.1 F
0.1 F
0.1 F
1
4.7 k
2
7
DVCC
5
6
P1.4
XOUT
XIN
MSP430
G2132
(14-PW)
SCLK
SDO
SDI
DVss
6
3
7
4
8
5
9
6
16
VCC1
VCC2
EN1
EN2
INA
INB
OUTA
ISO7341
INC
OUTD
GND1
4
2, 8
OUTB
OUTC
IND
GND2
9, 15
4.7 k
3
10
14
23
13
24
12
25
11
26
2
28
32
AINP MXO VBD
31
VA REFP
CS
CH0
SCLK
20
16 Analog
Inputs
ADS7953
SDI
CH15
SDO
BDGND
27
AGND
1, 22
5
REFM
30
Figure 26. Isolated SPI for an Analog Input Module With 16 Inputs
10.2.2.1 Design Requirements
Refer to Isolated Data Acquisition System for Process Control for the design requirements.
10.2.2.2 Detailed Design Procedure
Refer to Isolated Data Acquisition System for Process Control for the detailed design procedures.
10.2.2.3 Application Curves
Refer to Isolated Data Acquisition System for Process Control for the application curves.
Copyright © 2015–2017, Texas Instruments Incorporated
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Typical Application (continued)
10.2.3 Typical Application for RS-232 Interface
Typical isolated RS-232 interface implementation is shown in Figure 27.
VIN
3.3 V
0.1 F
2
VCC
D2
MBR0520L
1:2.1
3
1
SN6501
10 F 0.1 F
GND D1
1
10 F
4, 5
OUT
IN
5VISO
5
LP2985-50
3
ON
MBR0520L
4
BP
GND
2
10 nF
3.3 F
0.1 F
ISO-BARRIER
0.1 F
0.1 F
16
1 F
0.1 F
16
1
4.7 k
2
DVCC
5
6
XOUT
XIN
7
UCA0TXD
MSP430
F2132
UCA0RXD
DVSS
P3.0
P3.1
15
3
16
5
12
4
11
6
VCC1
VCC2
EN1
INA
EN2
ISO7342
OUTC
INB
OUTD
GND1
4
2, 8
OUTA
INC
OUTB
IND
1
4.7 k
10
2
1 F
3
14
11
12
12
13
10
11
9
VCC
VS+
VS-
C1+
C2+
TRS232
C1-
C2T1OUT
T1IN
R1IN
R1OUT
T2OUT
T2IN
R2OUT
R2IN
6
1 F
4
5
14
13
7
8
1 F
TxD
RxD
RST
CST
GND
GND2
15
9, 15
ISOGND
Figure 27. Isolated RS-232 Interface
10.2.3.1 Design Requirements
Refer to Isolated Data Acquisition System for Process Control for the design requirements.
10.2.3.2 Detailed Design Procedure
Refer to Isolated Data Acquisition System for Process Control for the detailed design procedures.
10.2.3.3 Application Curves
Refer to Isolated Data Acquisition System for Process Control for the application curves.
11 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501-Q1.
For such applications, detailed power supply design and transformer selection recommendations are available in
SN6501-Q1 Transformer Driver for Isolated Power Supplies.
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SLLSEK5B – JULY 2015 – REVISED MAY 2017
12 Layout
12.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 28). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see the Digital Isolator Design Guide.
12.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and the self-extinguishing flammability-characteristics.
12.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 28. Recommended Layer Stack
Copyright © 2015–2017, Texas Instruments Incorporated
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• Isolation Glossary
• Digital Isolator Design Guide
• SN6501-Q1 Transformer Driver for Isolated Power Supplies
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ISO7340-Q1
Click here
Click here
Click here
Click here
Click here
ISO7341-Q1
Click here
Click here
Click here
Click here
Click here
ISO7342-Q1
Click here
Click here
Click here
Click here
Click here
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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ISO7340-Q1, ISO7341-Q1, ISO7342-Q1
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SLLSEK5B – JULY 2015 – REVISED MAY 2017
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2015–2017, Texas Instruments Incorporated
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PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
7.6
7.4
NOTE 4
B
2.65 MAX
B
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
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www.ti.com
SLLSEK5B – JULY 2015 – REVISED MAY 2017
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Nov-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO7340CQDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7340CQ
ISO7340CQDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7340CQ
ISO7340FCQDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7340FCQ
ISO7340FCQDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7340FCQ
ISO7341CQDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7341CQ
ISO7341CQDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7341CQ
ISO7341FCQDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7341FCQ
ISO7341FCQDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7341FCQ
ISO7342CQDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7342CQ
ISO7342CQDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7342CQ
ISO7342FCQDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7342FCQ
ISO7342FCQDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7342FCQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Nov-2016
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ISO7340CQDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7340FCQDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7341CQDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7341FCQDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7342CQDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7342FCQDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO7340CQDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
ISO7340FCQDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
ISO7341CQDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
ISO7341FCQDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
ISO7342CQDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
ISO7342FCQDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
Pack Materials-Page 2
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