Texas Instruments | ISO308x Isolated 5-V Full- and Half-Duplex RS-485 Transceivers (Rev. I) | Datasheet | Texas Instruments ISO308x Isolated 5-V Full- and Half-Duplex RS-485 Transceivers (Rev. I) Datasheet

Texas Instruments ISO308x Isolated 5-V Full- and Half-Duplex RS-485 Transceivers (Rev. I) Datasheet
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ISO3080, ISO3082, ISO3086, ISO3088
SLOS581I – MAY 2008 – REVISED APRIL 2017
ISO308x Isolated 5-V Full- and Half-Duplex RS-485 Transceivers
1 Features
3 Description
•
•
•
•
•
•
•
•
•
The ISO3080 and ISO3086 devices are isolated fullduplex differential line drivers and receivers while the
ISO3082 and ISO3088 devices are isolated halfduplex differential line transceivers for TIA/EIA
485/422 applications.
•
Meets or Exceeds TIA/EIA RS-485 Requirements
Signaling Rates up to 20 Mbps
1/8 Unit Load – Up to 256 Nodes on a Bus
Thermal Shutdown Protection
Low Bus Capacitance – 16 pF (Typical)
50 kV/μs Typical Transient Immunity
Fail-safe Receiver for Bus Open, Short, Idle
3.3-V Inputs are 5-V Tolerant
Bus-Pin ESD Protection
– 12-kV HBM Between Bus Pins and GND2
– 6-kV HBM Between Bus Pins and GND1
Safety-Related Certifications:
– 4000-VPK Basic Insulation, 560 VPK VIORM per
DIN V VDE V 0884-10 (VDE V 0884-10):
2006-12 and DIN EN 61010-1
– 2500 VRMS Isolation per UL 1577
– 4000 VPK Isolation per CSA Component
Acceptance Notice 5A and IEC 60950-1
These devices are ideal for long transmission lines
because the ground loop is broken to allow for a
much larger common-mode voltage range. The
symmetrical isolation barrier of the device is tested to
provide 2500 VRMS of isolation for 60 s per UL 1577
between the bus-line transceiver and the logic-level
interface.
Any cabled I/O can be subjected to electrical noise
transients from various sources. These noise
transients can cause damage to the transceiver
and/or nearby sensitive circuitry if they are of
sufficient magnitude and duration. These isolated
devices can significantly increase protection and
reduce the risk of damage to expensive control
circuits.
The ISO3080, ISO3082, ISO3086, and ISO3088
device are qualified for use from –40°C to +85°C.
2 Applications
•
•
•
•
•
•
Security Systems
Chemical Production
Factory Automation
Motor and Motion Control
HVAC and Building Automation Networks
Networked Security Stations
R
3
4
RE
DE 5
D
6
GALVANIC ISOLATIO N
ISO3080, IOS3086 Function Diagram
14
13
12
Device Information(1)
PART NUMBER
BODY SIZE (NOM)
ISO3080
ISO3082
SOIC (16)
ISO3086
10.30 mm × 7.50 mm
ISO3088
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
ISO3082, IOS3088 Function Diagram
A
DE
B
D
Z
R
RE
11
PACKAGE
5
6
3
4
GALVANIC ISOLATION
1
13
12
B
A
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO3080, ISO3082, ISO3086, ISO3088
SLOS581I – MAY 2008 – REVISED APRIL 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
7
1
1
1
2
4
5
Absolute Maximum Ratings ..................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Insulation Specifications............................................ 6
Safety-Related Certifications..................................... 6
Safety Limiting Values .............................................. 7
Electrical Characteristics: Driver ............................... 7
Electrical Characteristics: Receiver .......................... 8
Supply Current ........................................................ 9
Switching Characteristics: Driver ............................ 9
Switching Characteristics: Receiver........................ 9
Insulation Characteristics Curves ......................... 10
Typical Characteristics .......................................... 11
Parameter Measurement Information ................ 13
8
Detailed Description ............................................ 17
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
17
17
18
18
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application ................................................. 20
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 23
12 Device and Documentation Support ................. 24
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (December 2015) to Revision I
Page
•
Changed the L(I01) and L(I02) parameters to external clearance and external creepage, respectively ............................... 6
•
Changed the VPR parameter to apparent charge .................................................................................................................. 6
•
Switched the R and D pins of the master device in the Typical RS-485 Network With Full-Duplex Transceivers figure .... 20
•
Added the Receiving Notification of Documentation Updates section ................................................................................. 24
•
Changed the Electrostatic Discharge Caution statement .................................................................................................... 24
Changes from Revision G (July 2015) to Revision H
Page
•
Changed the CDM value in ESD Ratings From: ±200 To: ±1000 ......................................................................................... 5
•
Changed the MON value of L(IO1) in Insulation and Safety-Related Package Characteristics From: 8.34 To: 8 mm ........ 6
•
Changed the MON value of L(IO2) in Insulation and Safety-Related Package Characteristics From: 8.1 To: 8 mm .......... 6
•
Moved the last list item " Routing the high-speed traces..." to the second list items in Layout Guidelines section............. 22
Changes from Revision F (May 2015) to Revision G
Page
•
Deleted "Rated mains voltage ≤ 400 VRMS" from IEC 60664-1 Ratings Table ....................................................................... 6
•
Changed "Maximum case temperature" To: "Maximum safety temperature" in Safety Limiting............................................ 7
•
Changed the Layout Guidelines section .............................................................................................................................. 22
2
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Changes from Revision E (September 2011) to Revision F
Page
•
Added ESD Rating table, Thermal Information table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1
•
Changed Features list item From: IEC 60747-5-2 (VDE 0884, Rev. 2) To: DIN V VDE V 0884-10 (VDE V 0884-10):
2006-12................................................................................................................................................................................... 1
•
VDE standard changed to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12....................................................................... 1
•
Changed IEC 60664-1 Ratings Table. Basic isolation group SPECIFICATION entry From: IIIa To: II ................................. 6
Changes from Revision D (January 2011) to Revision E
Page
•
Changed Features list item From: 16 kV HBM To: 12 kV HBM ............................................................................................. 1
•
Changed ESD HBM spec value from ±16 to ±12 in ESD Ratings ......................................................................................... 5
Changes from Revision C (October 2009) to Revision D
Page
•
Added TSTG row to the Absolute Maximum Ratings ............................................................................................................... 5
•
Added "Dynamic" conditions to Recommended Operating Conditions VID spec with reference to ISO3086
Recommended Minimum Differential Input Voltage vs Signaling Rate .................................................................................. 5
•
Changed for 3 V to 3.3 V in note 1 of the Recommended Operating Conditions table ......................................................... 5
•
Changed File Number from '1698195' to '220991 in Regulatory Information ....................................................................... 6
•
Changed θJA from 212 ° C/W to 168 ° C/W in conditions statement for IS spec.; and MAX current from 210 mA to
157 mA in Safety Limiting....................................................................................................................................................... 7
•
Deleted VI = VCCI or 0 V from CMTI spec. Conditions statement. Added "Figure 13" in Electrical Characteristics: Driver ... 7
•
Changed top row, UNIT column, split into 2 rows, top row µs and second row ns in Switching Characteristics: Driver....... 9
•
Changed graph for " DW-16 θJC Thermal Derating Curve per IEC 60747-5-2 " , Thermal Derating Curve......................... 10
•
Added the ISO3086 Recommended Minimum Differential Input Voltage vs Signaling Rate graph..................................... 11
•
Added note to bottom of first page of the Parameter Measurement Information ................................................................. 13
•
Added Footnotes to the Driver Function Table and Receiver Function Table ..................................................................... 18
Changes from Revision B (December 2008) to Revision C
•
Page
Changed Recommended Operating Conditions table note From: For 3-V operation, VCC1 or VCC2 is specified from
3.15 V to 3.6V. To: For 3-V operation, VCC1 is specified from 3.15 V to 3.6V........................................................................ 5
Changes from Revision A (June 2008) to Revision B
Page
•
Changed Features bullet From: 4000-VPEAK Isolation, To: 4000-VPEAK Isolation,, 560-VPEAK VIORM ...................................... 1
•
Added the CSA column to Regulatory Information................................................................................................................. 6
Changes from Original (May 2008) to Revision A
Page
•
Deleted the CSA column from Regulatory Information. ......................................................................................................... 6
•
Changed the file number in the VDE column in Regulatory Information From: 40014131 To: 40016131............................. 6
Copyright © 2008–2017, Texas Instruments Incorporated
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5 Pin Configuration and Functions
ISO3080 and ISO3086 DW Package
16-Pin SOIC
Top View
VCC1
GND1
R
RE
DE
D
GND1
GND1
1
2
16
15
VCC2
GND2
3
4
5
6
7
8
14
13
12
A
B
Z
Y
GND2
11
10
9
ISO3082 and ISO3088 DW Package
16-Pin SOIC
Top View
VCC1
GND1
R
RE
DE
D
GND1
GND1
GND2
1
2
16
15
3
4
5
6
7
8
14
13
12
11
10
9
VCC2
GND2
NC
B
A
NC
GND2
GND2
Pin Functions
PIN
NAME
A
B
ISO3080,
ISO3086
ISO3082,
ISO3088
I/O
14
—
I
—
12
I/O
13
—
I
DESCRIPTION
Receiver noninverting input on the bus-side
Transceiver noninverting Input or output (I/O) on the bus-side
Receiver inverting Input on the bus-side
—
13
I/O
D
6
6
I
Driver input
DE
5
5
I
Enables (when high) or disables (when low or open) driver output of ISO308x
2
2
7
7
8
8
GND1
GND2
9
9
10
10
15
15
11
Transceiver inverting input or output (I/O) on the bus-side
—
Ground connection for VCC1
—
Ground connection for VCC2
—
No connect
NC
—
R
3
3
O
Receiver output
RE
4
4
I
Disables (when high or open) or enables (when low) receiver output of ISO308x
14
VCC1
1
1
—
Power supply, VCC1
VCC2
16
16
—
Power supply, VCC2
Y
11
—
O
Driver noninverting output
Z
12
—
O
Driver inverting output
4
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SLOS581I – MAY 2008 – REVISED APRIL 2017
6 Specifications
6.1 Absolute Maximum Ratings
See
(1)
.
VCC
Input supply voltage (2)
VO
Voltage at any bus I/O pin
VIT
Voltage input, transient pulse (through 100 Ω, see Figure 21)
VI
Voltage input at any D, DE or RE pin
IO
Receiver output current
TJ
Maximum junction temperature
Tstg
Storage temperature
(1)
(2)
VCC1, VCC2
A, B, Y, and Z
MIN
MAX
UNIT
–0.3
6
V
–9
14
V
–50
50
V
–0.5
7
V
±10
mA
150
°C
150
°C
–65
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values.
6.2 ESD Ratings
VALUE
V(ESD)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
Charged device model (CDM), per JEDEC specification JESD22-C101
(1)
(2)
Bus pins and GND1
±6000
Bus pins and GND2
±12000
All pins
±4000
(2)
UNIT
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
(1)
VCC1
Logic-side supply voltage
VCC2
Bus-side supply voltage (1)
VOC
Voltage at either bus I/O pin
A, B
VIH
High-level input voltage
VIL
Low-level input voltage
VID
Differential input voltage
RL
Differential input resistance
IO
Output current
TA
Ambient temperature
(1)
TYP
3.15
MAX
UNIT
5.5
V
5.5
V
–7
12
V
D, DE, RE
2
VCC
D, DE, RE
0
0.8
–12
12
4.5
A with respect to B
Dynamic (ISO3086)
5
See Figure 10
54
Driver
Receiver
60
V
V
Ω
–60
60
–8
8
–40
85
mA
°C
For 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For 3.3-V operation, VCC1 is specified from 3.15 V to 3.6 V.
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6.4 Thermal Information
ISO308x
THERMAL METRIC (1)
DW (SOIC)
UNIT
16 PINS
Low-K thermal resistance (2)
168
High-K thermal resistance
79.6
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
39.7
°C/W
RθJB
Junction-to-board thermal resistance
44.7
°C/W
ψJT
Junction-to-top characterization parameter
11.8
°C/W
ψJB
Junction-to-board characterization parameter
44.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
(2)
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.
6.5 Insulation Specifications
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
External clearance (1)
Shortest terminal-to-terminal distance through air
8
mm
CPG
External creepage (1)
Shortest terminal-to-terminal distance across the
package surface
8
mm
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
0.008
mm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11)
≥400
V
Material group
II
Overvoltage category
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM
Rated mains voltage ≤ 150 VRMS
I-IV
Rated mains voltage ≤ 300 VRMS
I-III
(2)
Maximum repetitive peak isolation voltage AC voltage (bipolar)
560
VPK
4000
VPK
VIOTM
Maximum transient isolation voltage
VTEST = VIOTM, t = 60 s (qualification);
t = 1 s (100% production)
qpd
Apparent charge (3)
Method b1, VPR = VIORM × 1.5,
100% Production test with t = 1 s
≤5
pC
CIO
Barrier capacitance, input to output (4)
VI = 0.4 sin (4E6πt)
2
pF
12
Isolation resistance, input to output (4)
VIO = 500 V, TA = 25°C, all pins on each side of the
barrier tied together creating a 2-terminal device
>10
Ω
VIO = 500 V at TS = 150°C
>109
Ω
RIO
(1)
(2)
(3)
(4)
Pollution degree
2
Climatic category
40/125/21
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall
be ensured by means of suitable protective circuits.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device
6.6 Safety-Related Certifications
VDE
CSA
UL
Certified according to DIN V VDE V 0884-10 (VDE
V 0884-10):2006-12
Approved under CSA Component
Acceptance Notice 5A and IEC 60950-1
Recognized under UL 1577
Component Recognition Program
Basic insulation,
4000 VPK Maximum transient overvoltage,
560 VPK Maximum repetitive peak isolation voltage
4000 VPK Isolation rating,
560 VPK Basic working voltage per CSA
60950-1-07 and IEC 60950-1 (2nd Ed)
Single Protection, 2500 VRMS
Certificate number: 40016131
Master contract number: 220991
File number: E181974
6
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6.7 Safety Limiting Values
Safety limiting (1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure
of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
IS
Safety input, output, or supply
current
TS
Safety temperature
(1)
MIN
TYP
RθJA = 79.6°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C,
see Figure 1
MAX
UNIT
286
mA
150
°C
The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air
thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air
thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount
packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient
temperature plus the power times the junction-to-air thermal resistance.
6.8 Electrical Characteristics: Driver
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IO = 0 mA, no load
RL = 54 Ω, See Figure 11
| VOD |
Differential output voltage
magnitude
Δ|VOD|
Change in magnitude of the
differential output voltage
See Figure 11 and Figure 12
VOC(SS)
Steady-state common-mode
output voltage
ΔVOC(SS)
RL = 100 Ω (RS-422), See Figure 11
Vtest from –7 V to +12 V, See Figure 12
MIN
TYP
MAX
VCC
3
4.3
1.5
2.3
2
2.3
V
1.5
–0.2
0
0.2
See Figure 13
1
2.6
3
Change in steady-state commonmode output voltage
See Figure 13
–0.1
VOC(pp)
Peak-to-peak common-mode
output voltage
See Figure 13
II
Input current
D, DE, VI at 0 V or VCC1
High-impedance state output
current
IOS
Short-circuit output current
CMTI
Common-mode transient
immunity
V
V
ISO3080
ISO3086
–10
10
μA
1
μA
VY or VZ = –7 V.
VCC = 0 V or 5 V,
DE = 0 V, Other input at 0 V
VA or VB at 12 V, Other input at 0 V
V
See the receiver bias input
current parameter
VY or VZ = 12 V,
VCC = 0 V or 5 V,
DE = 0 V, Other input at 0 V
VA or VB at –7 V, Other input at 0 V
–1
–200
See Figure 22 and Figure 23
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0.1
0.5
ISO3082, ISO3088
IOZ
UNIT
25
200
50
mA
kV/μs
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6.9 Electrical Characteristics: Receiver
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT(+)
Positive-going input threshold
voltage
IO = –8 mA
VIT(–)
Negative-going input threshold
voltage
IO = 8 mA
Vhys
Hysteresis voltage (VIT+ – VIT–)
VOH
High-level output voltage
MIN
–200
TYP
MAX
UNIT
–85
–10
mV
–115
mV
30
mV
VCC1 –
0.4
3.1
4
4.8
VID = 200 mV, IO = –8 mA,
See Figure 17
3.3-V VCC1
3.3-V VCC1
0.15
0.4
5-V VCC1
0.15
0.4
5-V VCC1
VOL
Low-level output voltage
VID = –200 mV, IO = 8 mA,
See Figure 17
IO(Z)
High-impedance state output
current
VI = –7 to 12 V, Other input = 0 V
–1
V
1
VA or VB = 12 V, Other input at 0 V
0.04
0.1
VA or VB = 12 V, VCC = 0, Other input at 0 V
0.06
0.13
V
μA
II
Bus input current
IIH
High-level input current, RE
VIH = 2 V
–10
10
μA
IIL
Low-level input current, RE
VIL = 0.8 V
–10
10
μA
RID
Differential input resistance
A, B
CD
Differential input capacitance
Test input signal is a 1.5-MHz sine wave with
1-VPP amplitude. CD is measured across A
and B
7
pF
CI
Input capacitance to ground
VI = 0.4 sin (4E6πt)
2
pF
VA or VB = –7 V, Other input at 0 V
VA or VB = –7 V, VCC = 0, Other input at 0 V
8
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–0.1
–0.04
–0.05
–0.03
48
mA
kΩ
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6.10 Supply Current
over recommended operating condition (unless otherwise noted)
PARAMETER
ICC1
TEST CONDITIONS
TYP
RE at 0 V or VCC, DE at 0 V
3.3-V VCC1
or VCC1
Logic-side supply current
ICC2
MIN
Bus-side supply current
MAX
UNIT
8
mA
RE at 0 V or VCC, DE at 0 V
5-V VCC1
or VCC1
10
RE at 0 V or VCC, DE at 0 V, No load
15
mA
6.11 Switching Characteristics: Driver
over recommended operating conditions (unless otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay
TYP
MAX
ISO3080/82
TEST CONDITIONS
0.7
1.3
μs
ISO3086/88
25
45
ns
20
200
3
7.5
0.9
1.5
μs
ns
PWD (1)
Pulse skew (|tPHL –
tPLH|)
ISO3080/82
Differential output
signal rise and fall
time
ISO3080/82
tr, tf
tPZH,
tPZL
Propagation delay,
high-impedance-tohigh-level output and
high-impedance-tolow-level output
See Figure 15 and
ISO3080/82 Figure 16,
DE at 0 V
tPHZ,
tPLZ
(1)
ISO3086/88
MIN
See Figure 14
0.5
ISO3086/88
7
15
50% VO
2.5
7
90% VO
1.8
ISO3086/88
Propagation delay,
ISO3080/82
high-level-to-highSee Figure 15 and Figure 16, DE at 0 V
impedance output
and low-level to high- ISO3086/88
impedance output
UNIT
ns
μs
25
55
95
225
25
55
ns
ns
Also known as pulse skew
6.12 Switching Characteristics: Receiver
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
90
125
4
12
UNIT
tPLH, tPHL
Propagation delay
PWD (1)
Pulse width distortion |tPHL – tPLH|
tr, tf
Output signal rise and fall time
tPHZ,
tPZH
Propagation delay, high-level-tohigh-impedance output and highimpedance-to-high-level output
See Figure 19, DE at 0 V
22
ns
tPZL,
tPLZ
Propagation delay, highimpedance-to-low-level output
and low-level-to-high-impedance
output
See Figure 20, DE at 0 V
22
ns
(1)
See Figure 18
1
ns
ns
Also known as pulse skew.
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6.13 Insulation Characteristics Curves
300
Safety Limiting Current (mA)
VCC1 = VCC2 = 5.5 V
200
100
0
0
50
100
150
Case Temperature (°C)
200
D001
Figure 1. Thermal Derating Curve for Limiting Current per VDE
10
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60
30
50
25
Supply Current (mA)
Supply Current (mA)
6.14 Typical Characteristics
40
ICC1 (3.3 V)
ICC2 (5 V)
30
20
10
0
0
0
50
100
Data Rate (kbps)
150
0
200
50
D002
Figure 2. ISO3080 Supply Current vs Data Rate With Load
100
Data Rate (kbps)
150
200
D003
Figure 3. ISO3080 Supply Current vs Data Rate With No
Load
50
60
ICC1 (3.3 V)
ICC2 (5 V)
50
40
40
ICC1 (3.3 V)
ICC2 (5 V)
30
20
Supply Current (mA)
Supply Current (mA)
ICC1 (3.3 V)
ICC2 (5 V)
15
5
10
30
20
10
10
0
0
0
50
100
Data Rate (kbps)
150
200
0
50
D004
Figure 4. ISO3082 Supply Current vs Data Rate With Load
80
70
70
60
60
50
ICC1 (3.3 V)
ICC2 (5 V)
40
30
20
100
Data Rate (kbps)
150
200
D005
Figure 5. ISO3082 Supply Current vs Data Rate With No
Load
Supply Current (mA)
Supply Current (mA)
20
ICC1 (3.3 V)
ICC2 (5 V)
50
40
30
20
10
10
0
0
0
5
10
Data Rate (Mbps)
15
20
D007
Figure 6. ISO3086 Supply Current vs Data Rate With Load
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0
5
10
Data Rate (Mbps)
15
20
D006
Figure 7. ISO3086 Supply Current vs Data Rate With No
Load
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80
70
70
60
60
Supply Current (mA)
Supply Current (mA)
Typical Characteristics (continued)
50
ICC1 (3.3 V)
ICC2 (5 V)
40
30
20
ICC1 (3.3 V)
ICC2 (5 V)
50
40
30
20
10
10
0
0
0
5
10
Data Rate (Mbps)
15
20
0
5
D008
Figure 8. ISO3088 Supply Current vs Data Rate With Load
10
Data Rate (Mbps)
15
20
D009
Figure 9. ISO3088 Supply Current vs Data Rate With No
Load
1
VID - Differential Input Voltage - pk
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
2
4
6
8
10 12 14
Signaling Rate - Mbps
16
18
20
Figure 10. ISO3086 Recommended Minimum Differential Input Voltage vs Signaling Rate
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7 Parameter Measurement Information
VCC2
VCC1
IOA
DE
DE
A
0 or
VCC1
D
VOD
B
+
0 V or 3 V
VOD
–
B
60 W
GND 2
375 W
VOA
VOB
GND 2
GND 1
–7 V to 12 V
IOB
GND 2
GND 1
VI
375 W
A
II
Figure 11. Driver VOD Test and Current Definitions
Figure 12. Driver VOD With Common-Mode Loading
Test Circuit
NOTE
Unless otherwise stated, test circuits are shown for half-duplex devices, ISO3082 and
ISO3088. For full-duplex devices, the driver output pins are Y and Z.
VCC1
I OA
DE
27 W
A
II
Input
B
VB
27 W
I OB
GND2
VOB
VOC
VOA
VOC(SS)
VOC(p-p)
V OC
GND2
GND1
VA
VOD
B
GND1
VI
A
Input
Generator: PRR= 100 kHz, 50 % duty
cycle, t r < 6ns , t f < 6 ns , ZO = 50 W
Figure 13. Test Circuit and Waveform Definitions For The Driver Common-Mode Output Voltage
DE
VCC1
3V
A
D
Input
Generator
B
VI
50 W
GND 1
Generator: PRR = 100 kHz, 50 % duty cycle,
t r < 6ns , t f <6 ns , ZO = 50
VOD
CL = 50 pF
RL = 54 W
±20%
±1%
C L includes fixture and
instrumentation capacitance
50%
VI
50%
tPHL
tPLH
VOD
90%
50%
10%
VOD(H)
90%
tr
tf
50%
10%
VOD(L)
Figure 14. Driver Switching Test Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
3V
A
3 V if testing A output
,
0 V if testing B output
3 V or 0 V
D
S1
VO
50%
0V
DE
Input
V
Generator I
50%
VI
RL = 110 W
±1%
CL = 50 pF ±20%
CL includes fixture and
instrumentation
capacitance
50 W
tPZH
VOH
90%
50%
VO
~0 V
~
tPHZ
GND 1
Generator PRR = 50 kHz, 50% duty cycle,
tr <6ns, tf <6ns, ZO = 50 W
Figure 15. Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
3V
0 V if testing A output
,
3 V if testing B output
RL = 110 W
±1%
A
S1
D
3V
VI
3 V or 0 V
tPZL
CL = 50 pF ±20%
VI
50 W
50%
0V
B
DE
Input
Generator
50%
tPLZ
VO
5V
50%
CL includes fixture and
instrumentation
capacitance
GND 2
10%
VOL
Generator: PRR =50 kHz ,50% duty cycle,
t r< 6ns, t < 6ns, Z = 50
f
Figure 16. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveform
IA
A
R
VA
VA+ VB
B
VIC
VB
IO
VID
VO
IB
2
Figure 17. Receiver Voltage and Current Definitions
3 V
A
Input
Generator
VI
VI
R VO
50 W
1.5 V
B
RE
Generator: PRR=100 kHz, 50% duty cycle,
t < 6ns, t < 6ns, ZO = 50 W
r
f
50%
CL = 15 pF
±20%
CL includes fixture and
instrumentation capacitance
0 V
tPHL
tPLH
VO
50%
90%
50%
10%
50%
tr
tf
V OH
V OL
Figure 18. Receiver Switching Test Circuit and Waveforms
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Parameter Measurement Information (continued)
1.5 V
R VO
B
0V
Input
Generator
VCC
A
RE
3V
1 kW ±1%
S1
VI
CL = 15 pF ±20 %
50%
50%
CL includes fixture
and instrumentation
capacitance
t pHZ
tPZH
90%
VO
VI
V OH
50%
50 W
!0 V
Generator:PRR=100 kHz, 50% duty cycle ,
t r<6ns, t f <6ns, Z O = 50 W
Figure 19. Receiver Enable Test Circuit and Waveforms, Data Output High
R VO
B
1.5 V
Input
Generator
VCC
A
0V
VI
RE
1 kW ±1%
S1
3V
VI
50%
50%
CL = 15 pF ±20%
0V
CL includes fixture
and instrumentation
capacitance
tPZL
tPLZ
VCC
50%
V
O
50 W
10%
VOL
Generator: PRR =100 kHz, 50% dutycycle,
tr< 6 ns, t f < 6ns, ZO= 50 W
Figure 20. Receiver Enable Test Circuit and Waveforms, Data Output Low
0V
A
RE
R
B
Pulse Generator
15 ms duration
1% duty cycle
tr, tf £100 ns
100 W ±1%
+
_
D
DE
3V
Note:This test is conducted to test survivability only.
Data stability at the R output is not specified.
Figure 21. Transient Overvoltage Test Circuit
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Parameter Measurement Information (continued)
C = 0.1 mF
±1%
2V
VCC1
VCC2
GND1
C = 0.1 mF ±1%
A
DE
D
54 W
S1
B
VOH or VOL
0.8 V
R
VOH or VOL
RE
1 kW
GND1
GND2
CL = 15 pF
(includes probe and
jig capacitance)
V TEST
Figure 22. Half-Duplex Common-Mode Transient Immunity Test Circuit
C = 0.1 mF
±1%
2V
VCC1
VCC2
Y
C = 0.1 mF ±1%
DE
GND1
D
VOH or VOL
54 W
S1
Z
A
0.8 V
1.5 V or 0 V
54 W
VOH or VOL
RE
B
1 kW
0 V or 1.5 V
GND2
GND1
CL = 15 pF
(includes probe and
jig capacitance)
VTEST
Figure 23. Full-Duplex Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The ISO3080 and ISO3086 devices are isolated full-duplex differential line drivers and receivers while the
ISO3082 and ISO3088 devices are isolated half-duplex differential line transceivers for TIA/EIA 485/422
applications. They are rated to provide galvanic isolation of up to 2500 VRMS for 60 s as per the standard. They
have active-high driver enables and active-low receiver enables to control the data flow. They are available in
two speed grades suitable for data transmission up to 200 kbps and 20 Mbps.
When the driver enable pin, DE, is logic high, the differential outputs Y and Z follow the logic states at data input
D. A logic high at D causes Y to turn high and Z to turn low. In this case the differential output voltage defined as
VOD = V(Y) – V(Z) is positive. When D is low, the output states reverse, Z turns high, Y becomes low, and VOD is
negative. When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant.
The DE pin has an internal pulldown resistor to ground, thus when left open the driver is disabled (highimpedance) by default. The D pin has an internal pullup resistor to VCC, thus, when left open while the driver is
enabled, output Y turns high and Z turns low.
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = V(A) – V(B) is positive and higher than the positive input threshold, VIT+, the receiver output, R,
turns high. When VID is negative and less than the negative and lower than the negative input threshold, VIT– ,
the receiver output, R, turns low. If VID is between VIT+ and VIT– the output is indeterminate. When RE is logic
high or left open, the receiver output is high-impedance and the magnitude and polarity of VID are irrelevant.
Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is disconnected
from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven (idle bus).
GALVANIC ISOLATIO N
8.2 Functional Block Diagrams
3
4
R
RE
DE 5
D
6
14
13
12
A
B
Z
11
Y
DE
D
R
RE
5
6
3
4
GALVANIC ISOLATION
Figure 24. ISO3080, IOS3086 Functional Diagram
13
12
B
A
Figure 25. ISO3082, IOS3088 Functional Diagram
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8.3 Feature Description
Table 1 provides an overview of the device features.
Table 1. Device Features
(1)
DEVICE
RATED ISOLATION (1)
TYPE
DATA RATE
ISO3080
4000 VPK / 2500 VRMS
Full-duplex
200 kbps
ISO3086
4000 VPK / 2500 VRMS
Full-duplex
20 Mbps
ISO3082
4000 VPK / 2500 VRMS
Half-duplex
200 kbps
ISO3088
4000 VPK / 2500 VRMS
Half-duplex
20 Mbps
See Safety-Related Certifications table for detailed isolation ratings.
8.4 Device Functional Modes
Table 2 lists the driver functional modes and Table 3 lists the receiver functional modes.
Table 2. Driver Function Table (1)
(1)
(2)
OUTPUTS (2)
VCC1
VCC2
INPUT
(D)
ENABLE INPUT
(DE)
Y/A
PU
PU
H
H
H
L
PU
PU
L
H
L
H
PU
PU
X
L
Hi-Z
Hi-Z
PU
PU
X
OPEN
Hi-Z
Hi-Z
PU
PU
OPEN
H
H
L
PD
PU
X
X
Hi-Z
Hi-Z
PU
PD
X
X
Hi-Z
Hi-Z
PD
PD
X
X
Hi-Z
Hi-Z
Z/B
PU = Powered Up; PD = Powered Down; H = Logic High; L= Logic Low; X = Irrelevant, Hi-Z = High Impedance (off)
Driver output pins are Y and Z for full-duplex devices and A and B for half-duplex devices.
Table 3. Receiver Function Table (1)
(1)
18
DIFFERENTIAL INPUT
VID = (VA – VB)
ENABLE
(RE)
OUTPUT
(R)
PU
–0.01 V ≤ VID
L
H
PU
–0.2 V < VID < –0.01 V
L
?
PU
PU
VID ≤ –0.2 V
L
L
PU
PU
X
H
Hi-Z
PU
PU
X
OPEN
Hi-Z
PU
PU
Open circuit
L
H
PU
PU
Short circuit
L
H
PU
PU
Idle (terminated) bus
L
H
PD
PU
X
X
Hi-Z
PU
PD
X
L
H
VCC1
VCC2
PU
PU
PU = Powered Up; PD = Powered Down; H = Logic High; L= Logic Low; X = Irrelevant, Hi-Z = High Impedance (off), ? = Indeterminate
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8.4.1 Device I/O Schematics
Figure 26. Device I/O Schematics
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO308x family consists of RS-485 transceivers commonly used for asynchronous data transmissions. Fullduplex implementation requires two signal pairs (four wires), and allows each node to transmit data on one pair
while simultaneously receiving data on the other pair. For half-duplex transmission, only one pair is shared for
both transmission and reception of data. To eliminate line reflections, each cable end is terminated with a
termination resistor, R(T), whose value matches the characteristic impedance, Z0, of the cable. This method,
known as parallel termination, allows for higher data rates over longer cable length.
9.2 Typical Application
R
R
R
R
R
R
RE
A
RE
A
RE
A
DE
B
DE
B
DE
B
D
D
D
a) Independent driver and
receiver enable signals
D
D
b) Combined enable signals for
use as directional control pin
D
c) Receiver always on
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Figure 27. Half-Duplex Transceiver Configurations
Y
D
D
Z
A
R(T)
R(T)
B
R
R
DE
RE
Master
RE
R
Slave
B
R
A
DE
Z
R(T)
R(T)
A
B
Z
Y
D
D
Y
R Slave
D
R RE DE D
Figure 28. Typical RS-485 Network With Full-Duplex Transceivers
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Typical Application (continued)
9.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that can be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes. Table 4 lists the
design parameters.
Table 4. Design Parameters
PARAMETER
VALUE
Pullup and pulldown resistors
1 kΩ to 10 kΩ
Decoupling capacitors
100 nF
9.2.2 Detailed Design Procedure
The data rate and cable length have an inverse relationship which means the higher the data rate, the shorter
the cable length; and conversely, the lower the data rate, the longer the cable length. When connecting a node to
the bus, the distance between the transceiver inputs and the cable trunk, known as the stub, should be as short
as possible. Stubs present a nonterminated piece of bus line which can introduce reflections as the length of the
stub increases. As a general guideline, the electrical length, or round-trip delay, of a stub should be less than
one-tenth of the rise time of the driver. The RS-485 standard specifies that a compliant driver must be able to
driver 32 unit loads (ULs), where 1 UL represents a load impedance of approximately 12 kΩ. Because the
ISO308x family consists of 1/8 UL transceivers, connecting up to 256 receivers to the bus is possible.
9.2.3 Application Curve
Figure 29. ISO308x Output
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10 Power Supply Recommendations
To help ensure reliable operation at all data rates and supply voltages, a 0.1-μF bypass capacitor is
recommended at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to
the supply pins as possible. If only a single primary-side power supply is available in an application, isolated
power can be generated for the secondary-side with the help of a transformer driver such as Texas Instruments'
SN6501. For such applications, detailed power supply design and transformer selection recommendations are
available in SN6501 Transformer Driver for Isolated Power Supplies.
11 Layout
11.1 Layout Guidelines
ON-chip IEC-ESD protection is good for laboratory and portable equipment but never sufficient for EFT and
surge transients occurring in industrial environments. Therefore, robust and reliable bus node design requires the
use of external transient protection devices. Because ESD and EFT transients have a wide frequency bandwidth
from approximately 3-MHz to 3-GHz, high-frequency layout techniques must be applied during PCB design. A
minimum of four layers is required to accomplish a low EMI PCB design (see Figure 30).
• Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power
plane, and low-frequency signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
• Place the protection circuitry close to the bus connector to prevent noise transients from penetrating your
board.
• Use VCC and ground planes to provide low-inductance. High-frequency currents might follow the path of least
inductance and not necessarily the path of least resistance.
• Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
• Apply 0.1-µF bypass capacitors as close as possible to the VCC-pins of transceiver, UART, and controller ICs
on the board.
• Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to
minimize effective via-inductance.
• Use 1-kΩ to 10-kΩ pullup and pulldown resistors for enable lines to limit noise currents in these lines during
transient events.
• Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified
maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the
transceiver and prevent it from latching up.
• While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.
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Layout Guidelines (continued)
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 30. Recommended Layer Stack
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Communication Module Reference Design for Functional Isolated RS-485, CAN, and I2C Data Transmission
• Digital Isolator Design Guide
• Dual Isolated Half-Duplex RS-485 Repeater
• Isolation Glossary
• Programmable Logic Controller (PLC) I/O Module Front- End Controller with Tiva C Series ARM® Cortex®-M4
MCU
• Small Form Factor, Digital Isolator-Based Half-Duplex RS- 485 Interface Module Reference Design
• SN6501 Transformer Driver for Isolated Power Supplies
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ISO3080
Click here
Click here
Click here
Click here
Click here
ISO3082
Click here
Click here
Click here
Click here
Click here
ISO3086
Click here
Click here
Click here
Click here
Click here
ISO3088
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
ARM, Cortex are registered trademarks of ARM Ltd..
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
24
Submit Documentation Feedback
Copyright © 2008–2017, Texas Instruments Incorporated
Product Folder Links: ISO3080 ISO3082 ISO3086 ISO3088
ISO3080, ISO3082, ISO3086, ISO3088
www.ti.com
SLOS581I – MAY 2008 – REVISED APRIL 2017
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2008–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: ISO3080 ISO3082 ISO3086 ISO3088
25
ISO3080, ISO3082, ISO3086, ISO3088
SLOS581I – MAY 2008 – REVISED APRIL 2017
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
7.6
7.4
NOTE 4
B
2.65 MAX
B
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
26
Submit Documentation Feedback
Copyright © 2008–2017, Texas Instruments Incorporated
Product Folder Links: ISO3080 ISO3082 ISO3086 ISO3088
ISO3080, ISO3082, ISO3086, ISO3088
www.ti.com
SLOS581I – MAY 2008 – REVISED APRIL 2017
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
Copyright © 2008–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: ISO3080 ISO3082 ISO3086 ISO3088
27
ISO3080, ISO3082, ISO3086, ISO3088
SLOS581I – MAY 2008 – REVISED APRIL 2017
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
28
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Copyright © 2008–2017, Texas Instruments Incorporated
Product Folder Links: ISO3080 ISO3082 ISO3086 ISO3088
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO3080DW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ISO3080
ISO3080DWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ISO3080
ISO3080DWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ISO3080
ISO3082DW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ISO3082
ISO3082DWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ISO3082
ISO3082DWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ISO3082
ISO3082DWRG4
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ISO3082
ISO3086DW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ISO3086
ISO3086DWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ISO3086
ISO3086DWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ISO3086
ISO3088DW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ISO3088
ISO3088DWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ISO3088
ISO3088DWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ISO3088
ISO3088DWRG4
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ISO3088
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Nov-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ISO3080DWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO3082DWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO3086DWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO3088DWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Nov-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO3080DWR
SOIC
DW
16
2000
350.0
350.0
43.0
ISO3082DWR
SOIC
DW
16
2000
350.0
350.0
43.0
ISO3086DWR
SOIC
DW
16
2000
350.0
350.0
43.0
ISO3088DWR
SOIC
DW
16
2000
350.0
350.0
43.0
Pack Materials-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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