Texas Instruments | ISO733x-Q1 Robust EMC, Low Power, Triple-Channel Digital Isolators | Datasheet | Texas Instruments ISO733x-Q1 Robust EMC, Low Power, Triple-Channel Digital Isolators Datasheet

Texas Instruments ISO733x-Q1 Robust EMC, Low Power, Triple-Channel Digital Isolators Datasheet
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ISO7330-Q1, ISO7331-Q1
SLLSER7 – NOVEMBER 2015
ISO733x-Q1 Robust EMC, Low Power, Triple-Channel Digital Isolators
1 Features
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM Classification Level 3A
– Device CDM Classification Level C6
Signaling Rate: 25 Mbps
Integrated Noise Filter on the Inputs
Default Output High and Low Options
Low Power Consumption: Typical ICC per Channel
at 1 Mbps:
– ISO7330-Q1: 1 mA (5-V Supplies),
0.8 mA (3.3-V Supplies)
– ISO7331-Q1: 1.4 mA (5-V Supplies),
1 mA (3.3-V Supplies)
Low Propagation Delay: 32 ns
Typical (5-V Supplies)
Operates from 3.3 V and 5-V Supplies
3.3-V and 5-V Level Translation
70-kV/μs Transient Immunity,
Typical (5-V Supplies)
Robust Electromagnetic Compatibility (EMC)
– System-level ESD, EFT, and Surge Immunity
– Low Emissions
Wide Body SOIC-16 Package
Isolation Barrier Life: > 25 Years
Safety and Regulatory Approvals:
– 4242-VPK Isolation per DIN V VDE V 0884-10
and DIN EN 61010-1
– 3000-VRMS Isolation for 1 minute per UL 1577
– CSA Component Acceptance Notice 5A, IEC
60950-1 and IEC 61010-1 End Equipment
Standards
– Planned CQC Certification per GB4943.1-2011
2 Applications
•
Opto-Coupler Replacement in:
– Industrial FieldBus
– ProfiBus
– ModBus
– DeviceNet™ Data Buses
– Servo Control Interface
– Motor Control
– Power Supplies
– Battery Packs
3 Description
The ISO733x-Q1 family of devices provides galvanic
isolation up to 3000 VRMS for 1 minute per UL 1577
and 4242 VPK per VDE V 0884-10. These devices
have three isolated channels comprised of logic input
and output buffers separated by a silicon dioxide
(SiO2) insulation barrier.
The ISO7330-Q1 has all three channels in the same
direction while ISO7331-Q1 has two channels in
forward and one channel in reverse direction. In case
of input power or signal loss, the default output is low
for orderable part numbers with suffix F and high for
orderable part numbers without suffix F. See the
Device Functional Modes section for further details.
Used in conjunction with isolated power supplies,
these devices prevent noise currents on a data bus or
other circuits from entering the local ground and
interfering with or damaging sensitive circuitry. The
ISO733x-Q1 family of devices has integrated noise
filter for harsh industrial environment where short
noise pulses may be present at the device input pins.
The ISO733x-Q1 family of devices has TTL input
thresholds and operates from 3-V to 5.5-V supply
levels. Through innovative chip design and layout
techniques, electromagnetic compatibility of the
ISO733x-Q1 family of devices has been significantly
enhanced to enable system-level ESD, EFT, Surge
and Emissions compliance.
Device Information(1)
PART NUMBER
ISO7330-Q1
PACKAGE
SOIC (16)
ISO7331-Q1
BODY SIZE (NOM)
10.30 mm × 7.50
mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
VCCI
Isolation
Capacitor
VCCO
INx
OUTx
ENx
GNDI
GNDO
VCCI and GNDI are supply and ground
connections respectively for the input
channels.
VCCO and GNDO are supply and ground
connections respectively for the output.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7330-Q1, ISO7331-Q1
SLLSER7 – NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
4
4
4
4
5
5
6
6
6
7
7
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics—5-V Supply .....................
Supply Current Characteristics—5-V Supply ............
Electrical Characteristics—3.3-V Supply ..................
Supply Current Characteristics—3.3-V Supply .........
Power Dissipation Characteristics ............................
Switching Characteristics—5-V Supply...................
Switching Characteristics—3.3-V Supply................
Typical Characteristics ............................................
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
13
16
Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Application ................................................. 17
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 20
12 Device and Documentation Support ................. 21
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Related Links ........................................................
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
21
13 Mechanical, Packaging, and Orderable
Information ........................................................... 22
Parameter Measurement Information ................ 10
Detailed Description ............................................ 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
November 2015
*
Initial release.
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SLLSER7 – NOVEMBER 2015
5 Pin Configuration and Functions
ISO7330-Q1 DW Package
16-Pin SOIC
Top View
ISO7331-Q1 DW Package
16-Pin SOIC
Top View
VCC1
1
16
VCC2
VCC1
1
16
VCC2
GND1
2
15
GND2
GND1
2
15
GND2
INA
INB
3
14
OUTA
3
14
OUTA
4
13
OUTB
INA
INB
4
13
OUTB
INC
5
12
OUTC
OUTC
5
12
INC
NC
6
11
NC
NC
6
11
NC
EN
EN1
7
10
EN2
GND1
8
9
NC
7
10
GND1
8
9
GND2
GND2
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
ISO7330-Q1
ISO7331-Q1
EN
10
—
I
Output enable. OUTA, OUTB, and OUTC are enabled when EN is high or
disconnected and disabled when EN is low.
EN1
—
7
I
Output enable 1. OUTC is enabled when EN1 is high or disconnected and
disabled when EN1 is low.
EN2
—
10
I
Output enable 2. OUTA and OUTB are enabled when EN2 is high or
disconnected and disabled when EN2 is low.
2
2
8
8
GND1
—
Ground connection for VCC1
—
Ground connection for VCC2
9
9
15
15
INA
3
3
I
Input, channel A
INB
4
4
I
Input, channel B
INC
5
12
I
Input, channel C
GND2
6
NC
7
6
—
No Connect. These pins have no internal connection.
14
O
Output, channel A
13
13
O
Output, channel B
12
5
O
Output, channel C
VCC1
1
1
—
Power supply, VCC1
VCC2
16
16
—
Power supply, VCC2
11
11
OUTA
14
OUTB
OUTC
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage (2)
VCC
Voltage
VCC1 , VCC2
(2)
INx, OUTx, ENx
MIN
MAX
–0.5
6
–0.5
(3)
VCC+0.5
UNIT
V
V
IO
Output current
±15
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal and are peak voltage values.
Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±4000
Charged-device model (CDM), per AEC Q100-011
±1500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
NOM
Supply voltage
IOH
High-level output current
IOL
Low-level output current
VIH
High-level input voltage
2
5.5
VIL
Low-level input voltage
0
0.8
tui
Input pulse duration
1 / tui
Signaling rate
TJ
Junction temperature (1)
TA
Ambient temperature
(1)
3
MAX
VCC1, VCC2
5.5
–4
V
mA
4
40
mA
V
V
ns
0
–40
UNIT
25
25
Mbps
136
°C
125
°C
To maintain the recommended operating conditions for TJ, see the Thermal Information table.
6.4 Thermal Information
ISO733x-Q1
THERMAL METRIC (1)
DW (SOIC)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
78.3
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
40.9
°C/W
RθJB
Junction-to-board thermal resistance
42.9
°C/W
ψJT
Junction-to-top characterization parameter
15.3
°C/W
ψJB
Junction-to-board characterization parameter
42.4
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics—5-V Supply
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
IOH = –4 mA; see Figure 11
TEST CONDITIONS
VCCO (1)– 0.5
4.7
IOH = –20 μA; see Figure 11
VCCO (1) – 0.1
5
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
IN = VCC
IIL
Low-level input current
IN = 0 V
CMTI
Common-mode transient immunity
VI = VCC or 0 V; see Figure 14.
(1)
MAX
UNIT
V
IOL = 4 mA; see Figure 11
0.2
0.4
IOL = 20 μA; see Figure 11
0
0.1
V
480
mV
μA
10
μA
–10
25
70
kV/μs
VCCO is supply voltage, VCC1 or VCC2, for the output channel being measured.
6.6 Supply Current Characteristics—5-V Supply
All inputs switching with square wave clock signal for dynamic ICC measurement. VCC1 and VCC2 at 5 V ± 10% (over
recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUPPLY
CURRENT
MIN
TYP
MAX
ICC1
0.5
1.1
ICC2
0.4
0.9
ICC1
0.5
1.1
ICC2
2.6
4.2
ICC1
1.1
1.9
ICC2
4.3
6
ICC1
2.1
3.3
ICC2
7
9.3
ICC1
0.7
1.6
ICC2
0.7
1.3
ICC1
1.8
3
ICC2
2.4
3.6
ICC1
2.8
4.1
ICC2
3.8
5.1
ICC1
4.3
6.2
ICC2
5.8
7.8
UNIT
ISO7330-Q1
Disable
VI = VCC or 0 V, EN = 0 V
DC to 1 Mbps
DC Input: VI = VCC or 0 V,
AC Input: CL = 15 pF
Supply current for VCC1 and VCC2
10 Mbps
CL = 15 pF
25 Mbps
CL = 15 pF
Disable
VI = VCC or 0 V, EN1 = EN2 = 0 V
mA
ISO7331-Q1
DC to 1 Mbps
DC Input: VI = VCC or 0 V,
AC Input: CL = 15 pF
10 Mbps
CL = 15 pF
25 Mbps
CL = 15 pF
Supply current for VCC1 and VCC2
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mA
5
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SLLSER7 – NOVEMBER 2015
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6.7 Electrical Characteristics—3.3-V Supply
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
IOH = –4 mA; see Figure 11
TEST CONDITIONS
VCCO (1) – 0.5
3
IOH = –20 μA; see Figure 11
VCCO (1) – 0.1
3.3
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
IN = VCC
IIL
Low-level input curre
IN = 0 V
CMTI
Common-mode transient immunity
VI = VCC or 0 V; see Figure 14
(1)
MAX
V
IOL = 4 mA; see Figure 11
0.2
0.4
IOL = 20 μA; see Figure 11
0
0.1
425
V
mV
10
μA
μA
–10
25
UNIT
50
kV/μs
VCCO is supply voltage, VCC1 or VCC2, for the output channel being measured.
6.8 Supply Current Characteristics—3.3-V Supply
All inputs switching with square wave clock signal for dynamic ICC measurement. VCC1 and VCC2 at 3.3 V ± 10% (over
recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUPPLY
CURRENT
MIN
TYP
MAX
ICC1
0.3
0.6
ICC2
0.3
0.6
ICC1
0.3
0.6
ICC2
2
3.1
ICC1
0.7
1.1
ICC2
3.1
4.3
ICC1
1.2
2
ICC2
4.8
6.3
ICC1
0.5
0.9
ICC2
0.5
0.8
ICC1
1.3
2.1
ICC2
1.7
2.6
ICC1
1.9
2.7
ICC2
2.6
3.5
ICC1
2.9
4.2
ICC2
3.9
5.2
UNIT
ISO7330-Q1
Disable
VI = VCC or 0 V, EN = 0 V
DC to 1 Mbps
DC Input: VI = VCC or 0 V,
AC Input: CL = 15 pF
Supply current for VCC1 and VCC2
10 Mbps
CL = 15 pF
25 Mbps
CL = 15 pF
Disable
VI = VCC or 0 V, EN = 0 V
mA
ISO7331-Q1
DC to 1 Mbps
DC Input: VI = VCC or 0 V,
AC Input: CL = 15 pF
Supply current for VCC1 and VCC2
10 Mbps
CL = 15 pF
25 Mbps
CL = 15 pF
mA
6.9 Power Dissipation Characteristics
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 12.5-MHz 50% duty cycle square wave (unless otherwise noted)
MAX
UNIT
PD
Maximum Power Dissipation by ISO7330-Q1
PARAMETER
70
mW
PD1
Maximum Power Dissipation by Side-1 of
ISO7330-Q1
20
mW
PD2
Maximum Power Dissipation by Side-2 of
ISO7330-Q1
50
mW
PD
Maximum Power Dissipation by ISO7331-Q1
84
mW
PD1
Maximum Power Dissipation by Side-1 of
ISO7331-Q1
35
mW
PD2
Maximum Power Dissipation by Side-2 of
ISO7331-Q1
49
mW
6
TEST CONDITIONS
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MIN
TYP
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6.10 Switching Characteristics—5-V Supply
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay time
See Figure 11
PWD (1)
Pulse width distortion |tPHL – tPLH|
See Figure 11
tsk(o) (2)
tsk(pp)
(3)
Channel-to-channel output skew time
MIN
TYP
MAX
20
32
58
ns
4
ns
Same direction channels
2.5
Opposite direction channels
17
Part-to-part skew time
23
UNIT
ns
ns
tr
Output signal rise time
See Figure 11
3
tf
Output signal fall time
See Figure 11
2
tPHZ
Disable propagation delay, high-to-high impedance output
See Figure 12
7
12
ns
tPLZ
Disable propagation delay, low-to-high impedance output
See Figure 12
7
12
ns
7
12
11000
23000 (4)
11000
23000 (4)
7
12
Enable propagation delay, high
impedance-to-high output
tPZH
Enable propagation delay, high
impedance-to-low output
tPZL
tfs
(1)
(2)
(3)
(4)
ISO733xCQDWQ1 and
ISO733xCQDWRQ1
ISO733xFCQDWQ1 and
ISO733xFCQDWRQ1
ISO733xCQDWQ1 and
ISO733xCQDWRQ1
ISO733xFCQDWQ1 and
ISO733xFCQDWRQ1
Fail-safe output delay time from input power loss
ns
ns
See Figure 12
ns
See Figure 12
ns
See Figure 13
μs
7
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
The enable signal rate should be ≤ 43 Kbps
6.11 Switching Characteristics—3.3-V Supply
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay time
See Figure 11
PWD (1)
Pulse width distortion |tPHL – tPLH|
See Figure 11
tsk(o) (2)
tsk(pp)
(3)
MIN
TYP
MAX
22
36
66
ns
2.5
ns
Same direction channels
Channel-to-channel output skew time
3
Opposite direction channels
16
Part-to-part skew time
27
UNIT
ns
ns
tr
Output signal rise time
See Figure 11
3
tf
Output signal fall time
See Figure 11
2
tPHZ
Disable propagation delay, high-to-high impedance output
See Figure 12
9
18
ns
tPLZ
Disable propagation delay, low-to-high impedance output
See Figure 12
9
18
ns
9
18
13000
24000 (4)
13000
24000 (4)
9
18
tPZH
tPZL
tfs
(1)
(2)
(3)
(4)
Enable propagation delay, high
impedance-to-high output
Enable propagation delay, high
impedance-to-low output
ISO733xCQDWQ1 and
ISO733xCQDWRQ1
ISO733xFCQDWQ1 and
ISO733xFCQDWRQ1
ISO733xCQDWQ1 and
ISO733xCQDWRQ1
ISO733xFCQDWQ1 and
ISO733xFCQDWRQ1
Fail-safe output delay time from input power loss
ns
ns
See Figure 12
ns
See Figure 12
See Figure 13
ns
7
μs
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
The enable signal rate should be ≤ 41 Kbps
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6.12 Typical Characteristics
8
5
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
6
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
4
Supply Current (mA)
Supply Current (mA)
7
4.5
5
4
3
2
3.5
3
2.5
2
1.5
1
1
0.5
0
0
0
5
10
TA = 25°C
15
20
Data Rate (Mbps)
25
30
0
CL = 15 pF
10
TA = 25°C
Figure 1. ISO7330-Q1 Supply Current vs Data Rate
(With 15-pF Load)
15
20
Data Rate (Mbps)
25
30
D002
CL = No Load
Figure 2. ISO7330-Q1 Supply Current vs Data Rate
(With No Load)
7
5
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
5
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
4.5
4
Supply Current (mA)
6
Supply Current (mA)
5
D001
4
3
2
3.5
3
2.5
2
1.5
1
1
0.5
0
0
0
5
10
TA = 25°C
15
20
Data Rate (Mbps)
25
30
0
CL = 15 pF
15
20
Data Rate (Mbps)
25
30
D004
CL = No Load
Figure 4. ISO7331-Q1 Supply Current vs Data Rate
(With No Load)
0.9
6
VCC at 3.3 V
VCC at 5 V
VCC at 3.3 V
VCC at 5 V
0.8
Low-Level Output Voltage (V)
High-Level Output Voltage (V)
10
TA = 25°C
Figure 3. ISO7331-Q1 Supply Current vs Data Rate
(With 15-pF Load)
5
5
D003
4
3
2
1
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
-15
-10
-5
High-Level Output Current (mA)
0
TA = 25°C
5
10
Low-Level Output Current (mA)
15
D006
TA = 25°C
Figure 5. High-Level Output Voltage vs High-level Output
Current
8
0
D005
Figure 6. Low-Level Output Voltage vs Low-Level Output
Current
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Typical Characteristics (continued)
2.48
45
VCC Rising
VCC Falling
2.46
2.44
2.42
2.40
2.38
41
39
37
35
33
31
29
27
2.36
-50
0
50
100
Free-Air Temperature (qC)
25
-40
150
-10
20
50
80
Free-Air Temperature (qC)
D007
Figure 7. Power Supply Undervoltage Threshold vs Free-Air
Temperature
110
135
D008
Figure 8. Propagation Delay Time vs Free-Air Temperature
250
29
tGS at 3.3 V
tGS at 5 V
27
Peak-to-Peak Output Jitter (ps)
Input Glitch Suppression Time (ns)
tPHL at 3.3 V
tPHL at 5 V
tPLH at 3.3 V
tPLH at 5 V
43
Propagation Delay Time (ns)
Power Supply Under-Voltage Threshold (V)
2.50
25
23
21
19
17
15
-40
Output Jitter at 3.3 V
Output Jitter at 5 V
200
150
100
50
0
-10
20
50
80
Free-Air Temperature (qC)
110
135
0
5
D009
10
15
Data Rate (Mbps)
20
25
D010
TA = 25°C
Figure 9. Input Glitch Suppression Time vs Free-Air
Temperature
Figure 10. Output Jitter vs Data Rate
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Isolation Barrier
7 Parameter Measurement Information
IN
Input
Generator
Note A
50 W
VI
VCCI
VI
OUT
50%
50%
0V
tPLH
VO
CL
Note B
tPHL
90%
10%
50%
VO
VOH
50%
VOL
tr
tf
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate the Input Generator signal. It is not
needed in actual application.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 11. Switching Characteristic Test Circuit and Voltage Waveforms
VCCO
VCC
Isolation Barrier
RL = 1 kΩ ±1%
IN
0V
VI
OUT
EN
VCC / 2
0V
tPLZ
tPZL
VO
VCCO
VO
CL
VCC / 2
0.5 V
50%
VOL
See Note B
Input
Generator
VI
50 Ω
See Note A
Isolation Barrier
VCC
IN
3V
VO
OUT
EN
CL
See Note B
VI
VI
VCC / 2
0V
Input
Generator
VCC / 2
tPZH
VOH
RL = 1 kΩ ±1%
VO
50 W
50%
0.5 V
tPHZ
See Note A
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
0V
Figure 12. Enable and Disable Propagation Delay Time Test Circuit and Waveform
10
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Parameter Measurement Information (continued)
VI
VCCI
IN = 0 V (Devices without suffix F)
IN = VCCI (Devices with suffix F)
A.
ISOLATION BARRIER
VCCI
IN
2.7 V
VI
OUT
0V
t fs
VO
fs high
VO
CL
See Note A
VOH
50%
fs low V
OL
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 13. Fail-Safe Output Delay-Time Test Circuit and Voltage Waveforms
S1
IN
C = 0.1 μ F ±1%
Isolation Barrier
VCCI
GNDI
VCCO
C = 0.1 μ F ±1%
Pass-fail criteria –
output must remain
stable.
OUT
+
CL
Note A
VOH or VOL
GNDO
–
+ VCM –
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 14. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The isolator in Figure 15 is based on a capacitive isolation barrier technique. The I/O channel of the device
consists of two internal data channels, a high-frequency (HF) channel with a bandwidth from 100 kbps up to 25
Mbps, and a low-frequency (LF) channel covering the range from 100 kbps down to DC.
In principle, a single-ended input signal entering the HF channel is split into a differential signal via the inverter
gate at the input. The following capacitor-resistor networks differentiate the signal into transient pulses, which
then are converted into CMOS levels by a comparator. The transient pulses at the input of the comparator can
be either above or below the common mode voltage VREF depending on whether the input bit transitioned from 0
to 1 or 1 to 0. The comparator threshold is adjusted based on the expected bit transition. A decision logic (DCL)
at the output of the HF channel comparator measures the durations between signal transients. If the duration
between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the
DCL forces the output-multiplexer to switch from the high-frequency to the low-frequency channel.
8.2 Functional Block Diagram
Isolation Barrier
OSC
Low t Frequency
Channel
(DC...100 kbps)
PWM
VREF
LPF
0
Polarity and
Threshold Selection
IN
OUT
1 S
High t Frequency
Channel
(100 kbps...25 Mbps)
VREF
DCL
Polarity and Threshold Selection
Figure 15. Conceptual Block Diagram of a Digital Capacitive Isolator
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these
signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a
sufficiently high frequency, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter
(LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output
multiplexer.
12
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8.3 Feature Description
ORDERABLE DEVICE
CHANNEL DIRECTION
ISO7330CQDWQ1 and
ISO7330CQDWRQ1
ISO7330FCQDWQ1 and
ISO7330FCQDWRQ1
ISO7331CQDWQ1 and
ISO7331CQDWRQ1
ISO7331FCQDWQ1 and
ISO7331FCQDWRQ1
(1)
RATED ISOLATION
MAX DATA RATE
DEFAULT OUTPUT
High
3 Forward,
0 Reverse
Low
3000 VRMS / 4242 VPK
(1)
25 Mbps
High
2 Forward,
1 Reverse
Low
See the Regulatory Information section for detailed Isolation Ratings
8.3.1 High Voltage Feature Description
8.3.1.1 Package Insulation Specifications
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
L(I01)
Minimum air gap (clearance)
Shortest terminal-to-terminal distance through air
8
mm
L(I02)
Minimum external tracking
(creepage)
Shortest terminal-to-terminal distance across the
package surface
8
mm
CTI
Tracking resistance (comparative
tracking index)
DIN EN 60112 (VDE 0303-11); IEC 60112
DTI
Minimum internal gap (internal
clearance)
Distance through the insulation
VIO = 500 V, TA = 25°C
>400
V
13
µm
12
Ω
11
Ω
>10
RIO
Isolation resistance, input to
output (1)
CIO
Isolation capacitance, input to
output (1)
VIO = 0.4 sin (2πft), f = 1 MHz
2
pF
CI
Input capacitance (2)
VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V
2
pF
(1)
(2)
VIO = 500 V, 100°C ≤ TA ≤ max
>10
All pins on each side of the barrier tied together creating a two-terminal device.
Measured from input pin to ground.
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance.
Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to
help increase these specifications.
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8.3.1.2 Insulation Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER (1)
SPECIFICATION
UNIT
VIOWM
Maximum isolation working voltage
TEST CONDITIONS
1000
VRMS
VIORM
Maximum repetitive peak voltage per
DIN V VDE V 0884-10
1414
VPK
Input-to-output test voltage per
DIN V VDE V 0884-10
VPR
After Input/Output safety test subgroup 2/3,
VPR = VIORM × 1.2, t = 10 s,
Partial discharge < 5 pC
1697
Method a, After environmental tests subgroup 1,
VPR = VIORM × 1.6, t = 10 s,
Partial Discharge < 5 pC
2262
Method b1,
VPR = VIORM × 1.875, t = 1 s (100% Production test)
Partial discharge < 5 pC
2651
VPK
VIOTM
Maximum transient overvoltage per
DIN V VDE V 0884-10
VTEST = VIOTM
t = 60 sec (qualification)
t= 1 sec (100% production)
4242
VPK
VIOSM
Maximum surge isolation voltage per
DIN V VDE V 0884-10
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.3 × VIOSM = 7800 VPK (qualification)
6000
VPK
VISO
Withstand isolation voltage per UL 1577
VTEST = VISO = 3000 VRMS, t = 60 sec (qualification)
VTEST = 1.2 × VISO = 3600 VRMS, t = 1 sec (100%
production)
3000
VRMS
RS
Insulation resistance
VIO = 500 V at TS
>109
Ω
Pollution degree
(1)
2
Climatic Classification 40/125/21
Table 1. IEC 60664-1 Ratings Table
PARAMETER
TEST CONDITIONS
Basic isolation group
SPECIFICATION
Material group
Installation classification
II
Rated mains voltage ≤ 300 VRMS
I–IV
Rated mains voltage ≤ 600 VRMS
I–III
Rated mains voltage ≤ 1000 VRMS
I–II
8.3.1.3 Regulatory Information
VDE
CSA
UL
CQC
Certified according to DIN V VDE
V 0884-10 (VDE V 088410):2006-12 and DIN EN 61010-1
(VDE 0411-1):2011-07
Approved under CSA
Component Acceptance Notice
5A, IEC 60950-1, and IEC
61010-1
Basic Insulation
Maximum Transient Overvoltage,
4242 VPK ;
Maximum Surge Isolation
Voltage, 6000 VPK;
Maximum Repetitive Peak
Isolation Voltage', 1414 VPK
800 VRMS Basic Insulation and
400 VRMS Reinforced Insulation
working voltage per CSA 609501-07+A1+A2 and IEC 60950-1
Single protection, 3000 VRMS
2nd Ed.+A1+A2;
300 VRMS Basic Insulation
working voltage per CSA 610101-12 and IEC 61010-1 3rd Ed.
Certificate number: 40016131
Master contract number: 220991 File number: E181974
(1)
14
Recognized under UL 1577
Component Recognition
Program
Planned to be certified according to
GB4943.1-2011
(1)
Reinforced Insulation, Altitude ≤
5000 m, Tropical Climate, 250
VRMS maximum working voltage
Certification planned
Production tested ≥ 3600 VRMS for 1 second in accordance with UL 1577.
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8.3.1.4 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
IS
Safety input, output, or supply
current
TS
Maximum safety temperature
MIN
TYP
MAX
RθJA = 78.3 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
290
RθJA = 78.3 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
443
150
UNIT
mA
°C
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum
Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface-Mount
Packages. The power is the recommended maximum input voltage times the current. The junction temperature is
then the ambient temperature plus the power times the junction-to-air thermal resistance.
500
Safety Limiting Current (mA)
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
400
300
200
100
0
0
50
100
150
Ambient Temperature (qC)
200
D011
Figure 16. Thermal Derating Curve per VDE
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8.4 Device Functional Modes
Table 2 lists the functional modes for the ISO733x-Q1 family of devices.
Table 2. Function Table (1)
VCCI
VCCO
PU
(1)
(2)
(3)
INPUT
(INx)
OUTPUT ENABLE
(ENx)
H
L
PU
OUTPUT
(OUTx)
ISO733xCQDWQ1 AND
ISO733xCQDWRQ1
ISO733xFCQDWQ1 AND
ISO733xFCQDWRQ1
H or Open
H
H
H or Open
L
L
X
L
Z
Z
Open
H or Open
H (2)
L (3)
PD
PU
X
H or Open
H (2)
L (3)
X
PU
X
L
Z
Z
X
PD
X
X
Undetermined
Undetermined
VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 3 V); PD = Powered down (VCC ≤ 2.1 V); X = Irrelevant; H =
High level; L = Low level; Open = Not connected
In fail-safe condition, output defaults to high level
In fail-safe condition, output defaults to low level
8.4.1 Device I/O Schematics
Input (Devices Without Suffix F)
VCCI
VCCI
Input (Devices With Suffix F)
VCCI
VCCI
VCCI
VCCI
VCCI
5 mA
500 W
500 W
INx
INx
5 mA
Output
Enable
VCCO
VCCO
VCCO VCCO
VCCO
5 mA
500 W
40 W
OUTx
ENx
Figure 17. Device I/O Schematics
16
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO733x-Q1 family of devices uses single-ended TTL-logic switching technology. Its supply voltage range is
from 3 V to 5.5 V for both supplies, VCC1 and VCC2. When designing with digital isolators, keep in mind that
because of the single-ended design structure, digital isolators do not conform to any specific interface standard
and are only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed
between the data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the
interface type or standard.
9.2 Typical Application
The ISO7331-Q1 device combined with Texas Instruments' Piccolo™ microcontroller, analog-to-digital receiver,
transformer driver, and voltage regulator can create an isolated serial peripheral interface (SPI) as shown in
Figure 18.
VS
3.3 V
0.1 µF
2
VCC D2 3
MBR0520L
1:1.33
4
OUT
1
3.3VISO
TPS76333-Q1
SN6501-Q1
GND D1
IN
3
1
10 µF
0.1 µF
EN
GND
2
10 µF
MBR0520L
4, 5
2
1 µF
VIN
VOUT
6
REF5025A-Q1
10 µF
4
22 µF
GND
ISO Barrier
0.1 µF
0.1 µF
0.1 µF
0.1 µF
1
4.7 k
29, 57
7
VDDIO
TMS320F28035PAGQ
SPICLKA
SPISIMOA
SPISOMIA
33
36
34
VSS
6, 28
VCC1
EN1
16
VCC2
EN2
6 NC
NC
ISO7331-Q1
3
INA
OUTA
4
INB
OUTB
5
OUTC
INC
GND1
2, 8
4.7 k
8
10
7
36
5
4
AINP MXO +VBD +VA REFP
11
14
CS
32
13
33
12
34
CH0
SCLK
28
16 Analog
Inputs
ADS7953-Q1
SDI
SDO
GND2
9, 15
CH15
BDGND
27
AGND
1, 22
11
REFM
30
Multiple pins and discrete components are omitted for clarity.
Figure 18. Isolated SPI for an Analog Input Module With 16 Inputs and a Single Slave
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Typical Application (continued)
9.2.1 Design Requirements
9.2.1.1 Typical Supply Current Equations
For the equations in this section, the following is true:
• ICC1 and ICC2 are typical supply currents measured in mA
• f is the data rate measured in Mbps
• CL is the capacitive load measured in pF
9.2.1.1.1 ISO7330-Q1
At VCC1 = VCC2 = 5 V
ICC1 = 0.46544 + (0.006455 × f)
ICC2 = 2.28021 + (0.08242 × f) + (0.006237 × f × CL)
(1)
(2)
At VCC1 = VCC2 = 3.3 V
ICC1 = 0.29211 + (0.03588 × f)
ICC2 = 1.8414 + (0.02886 × f) + (0.00548 × f × CL)
(3)
(4)
9.2.1.1.2 ISO7321-Q1
At VCC1 = VCC2 = 5 V
ICC1 = 1.661 + (0.07916 × f) + (0.00169 × f × CL)
ICC2 = 2.04 + (0.0778 × f) + (0.00422 × f × CL)
(5)
(6)
At VCC1 = VCC2 = 3.3 V
ICC1 = 1.2402 + (0.03127 × f) + (0.001954 × f × CL)
ICC2 = 1.53839 + (0.02933 × f) + (0.0037285 × f × CL)
(7)
(8)
9.2.2 Detailed Design Procedure
9.2.2.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO733xQ1 family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
18
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Typical Application (continued)
9.2.3 Application Curves
The following typical eye diagrams of the ISO733x-Q1 family of devices indicate low jitter and wide open eye at
the maximum data rate of 25 Mbps.
Figure 20. Eye Diagram at 25 Mbps, 3.3 V and 25°C
Figure 19. Eye Diagram at 25 Mbps, 5 V and 25°C
9.2.4 Systems Examples
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO733x-Q1 family of devices only requires two external bypass capacitors to operate.
2 mm maximum from VCC1
ISO7330
0.1 µF
VCC1
ISO7331
0.1 µF
0.1 µF
VCC1
VCC2
1
16
2
15
INA
3
14
OUTA
INB
4
13
OUTB
INC
5
12
OUTC
NC
6
11
NC
7
10
GND1
2 mm maximum from VCC2
2 mm maximum from VCC1
2 mm maximum from VCC2
0.1 µF
VCC2
1
16
2
15
INA
3
14
OUTA
INB
4
13
OUTB
OUTC
5
12
INC
6
11
7
10
8
9
GND1
GND2
NC
GND2
NC
NC
EN2
EN1
EN
8
9
GND1
GND1
GND2
GND2
Figure 21. Typical ISO7330-Q1 Circuit Hook-up
Figure 22. Typical ISO7331-Q1 Circuit Hook-up
10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-µF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501-Q1.
For such applications, detailed power supply design and transformer selection recommendations are available in
SN6501-Q1 datasheet (SLLSEF3) .
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11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 23). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see the application note SLLA284, Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 UL94V-0 printed circuit boards. This PCB is preferred over cheaper
alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 23. Recommended Layer Stack
20
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• ADS79xx-Q1 8-, 10-, and 12-Bit, 1-MSPS, 4-, 8-, 12-, and 16-Channel, Single-Ended, Micropower, Serial
Interface, Analog-to-Digital Converters, SBAS652
• Digital Isolator Design Guide, SLLA284
• ISO73xx Triple/Quad Digital Isolator Evaluation Module, SLLU209
• Isolation Glossary, SLLA353
• REF50xxA-Q1 Low-Noise, Very Low Drift, Precision Voltage Reference, SBOS456
• SN6501-Q1 Transformer Driver for Isolated Power Supplies, SLLSEF3
• TPS76333-Q1 Low-Power 150-mA Low-Dropout Linear Regulators, SGLS247
• TMS320F28035 Piccolo™ Microcontrollers, SPRS584
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ISO7330-Q1
Click here
Click here
Click here
Click here
Click here
ISO7331-Q1
Click here
Click here
Click here
Click here
Click here
12.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
DeviceNet, Piccolo, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ISO7330-Q1 ISO7331-Q1
21
ISO7330-Q1, ISO7331-Q1
SLLSER7 – NOVEMBER 2015
www.ti.com
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ISO7330-Q1 ISO7331-Q1
ISO7330-Q1, ISO7331-Q1
www.ti.com
SLLSER7 – NOVEMBER 2015
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
7.6
7.4
NOTE 4
B
2.65 MAX
B
0.38
TYP
0.25
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4221009/A 08/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MO-013, variation AA.
www.ti.com
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ISO7330-Q1 ISO7331-Q1
23
ISO7330-Q1, ISO7331-Q1
SLLSER7 – NOVEMBER 2015
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/A 08/2013
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
24
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ISO7330-Q1 ISO7331-Q1
ISO7330-Q1, ISO7331-Q1
www.ti.com
SLLSER7 – NOVEMBER 2015
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/A 08/2013
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ISO7330-Q1 ISO7331-Q1
25
PACKAGE OPTION ADDENDUM
www.ti.com
13-Dec-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO7330CQDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7330CQ
ISO7330CQDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7330CQ
ISO7330FCQDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7330FCQ
ISO7330FCQDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7330FCQ
ISO7331CQDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7331CQ
ISO7331CQDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7331CQ
ISO7331FCQDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7331FCQ
ISO7331FCQDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7331FCQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
13-Dec-2015
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ISO7330CQDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7330FCQDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7331CQDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7331FCQDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO7330CQDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
ISO7330FCQDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
ISO7331CQDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
ISO7331FCQDWRQ1
SOIC
DW
16
2000
350.0
350.0
43.0
Pack Materials-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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