Texas Instruments | ISO3086T Isolated 5-V RS-485 Transceiver With Integrated Transformer Driver (Rev. D) | Datasheet | Texas Instruments ISO3086T Isolated 5-V RS-485 Transceiver With Integrated Transformer Driver (Rev. D) Datasheet

Texas Instruments ISO3086T Isolated 5-V RS-485 Transceiver With Integrated Transformer Driver (Rev. D) Datasheet
Sample &
Buy
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
Reference
Design
ISO3086T
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
ISO3086T Isolated 5-V RS-485 Transceiver With Integrated Transformer Driver
1 Features
3 Description
•
•
•
•
•
The ISO3086T is an isolated differential line
transceiver with integrated oscillator outputs that
provide the primary voltage for an isolation
transformer. The device is a full-duplex differential
line transceiver for RS-485 and RS-422 applications
that can easily be configured for half-duplex operation
by connecting pin 11 to pin 14, and pin 12 to pin 13.
1
•
•
•
•
•
•
Meets or Exceeds TIA/EIA-485-A
Signaling Rate up to 20 Mbps
1/8 Unit Load – Up to 256 Nodes on a Bus
Thermal Shutdown Protection
Typical Efficiency > 60% (ILOAD = 100 mA) - see
SLUU469
Low Bus Capacitance 7 pF (Typ)
50-kV/µs Typical Transient Immunity
Fail-safe Receiver for Bus Open, Short, Idle
Logic Inputs are 5-V Tolerant
Bus-Pin ESD Protection
– 11-kV HBM Between Bus-Pins and GND2
– 6-kV HBM Between Bus-Pins and GND1
Safety and Regulatory Approvals
– 4242 VPK Basic Insulation per DIN V VDE V
0884-10 and DIN EN 61010-1
– 2500 VRMS Isolation for 1 minute per UL 1577
– CSA Component Acceptance Notice 5A, IEC
60950-1 and IEC 61010-1 Standards
These devices are ideal for long transmission lines
since the ground loop is broken to allow for a much
larger common-mode voltage range. The symmetrical
isolation barrier of the device is tested to provide
4242 VPK of isolation for 1 minute per VDE between
the bus-line transceiver and the logic-level interface.
Any cabled I/O can be subjected to electrical noise
transients from various sources. These noise
transients can cause damage to the transceiver
and/or near-by sensitive circuitry if they are of
sufficient magnitude and duration. These isolated
devices can significantly increase protection and
reduce the risk of damage to expensive control
circuits.
The ISO3086T is specified for use from –40°C to
85°C.
2 Applications
•
•
•
•
•
Device Information(1)
Isolated RS-485/RS-422 Interfaces
Factory Automation
Motor/Motion Control
HVAC and Building Automation Networks
Networked Security Stations
PART NUMBER
ISO3086T
PACKAGE
SOIC (16)
BODY SIZE (NOM)
10.30 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application Circuit
4
X-FMR
8
7
6
3
2
LDO
D1
1
C4 C5
2
C1
5
1
3
IN
OUT
5
EN
C6
GND NC
1
D2
1
VCC2
D1
16
C3
2
C2
Control
Circuitry
D2
4 V
CC1
3
GND1
5
R
6
RE
7
DE
8
D
A
B
Z
Y
14
Isolated Supply to
other Components
13
12
RS-485 Bus
Interface
11
15
GND2
9, 10
ISO3086T
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO3086T
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
3
4
4
4
4
5
5
5
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Power Rating.............................................................
Electrical Characteristics: Driver ...............................
Electrical Characteristics: Receiver ..........................
Transformer Driver Characteristics ...........................
Supply Current and Common-Mode Transient
Immunity.....................................................................
6.10 Switching Characteristics: Driver ............................
6.11 Switching Characteristics: Receiver........................
6.12 Typical Characteristics ............................................
7
6
6
6
7
Parameter Measurement Information ................ 10
8
Detailed Description ............................................ 14
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
14
15
17
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application ................................................. 20
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 24
12 Device and Documentation Support ................. 25
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July 2011) to Revision D
Page
•
Added Feature Item "Meets or Exceeds TIA/EIA-485"........................................................................................................... 1
•
VDE standard changed to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 ...................................................................... 1
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision B (July 2011) to Revision C
Page
•
Added Note 1 to the TRANSFORMER DRIVER CHARACTERISTICS table ........................................................................ 5
•
Changed the TRANSFORMER DRIVER CHARACTERISTICS table - fSt Test Conditions From: .VCC1 = 9V To: VCC1
= 2.4 and Changed the TYP value From: 230 To: 350 kHz ................................................................................................... 6
Changes from Revision A (March 2011) to Revision B
•
Page
Deleted the MIN and MAX values from rows, tr_d, tf_D, and tBBM of the TRANSFORMER DRIVER
CHARACTERISTICS table ..................................................................................................................................................... 6
Changes from Original (January 2011) to Revision A
Page
•
Changed the Features and Description.................................................................................................................................. 1
•
Changed the data sheet From: Preview To: Production ........................................................................................................ 1
•
Added Figure 34 Typical Application Circuit........................................................................................................................... 3
2
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ISO3086T
ISO3086T
www.ti.com
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
5 Pin Configuration and Functions
DW Package
16-Pin SOIC
Top View
D1
D2
1
16
2
15
GND1
VCC1
R
RE
DE
D
3
4
14
13
5
12
6
11
7
10
8
9
VCC2
GND2
A
B
Z
Y
NC
GND2
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
A
14
I
Non-inverting Receiver Input
B
13
I
Inverting Receiver Input
D1
1
O
Transformer Driver Terminal 1, Open Drain Output
D2
2
O
Transformer Driver Terminal 2, Open Drain Output
D
8
I
Driver Input
DE
7
I
Driver Enable Input
GND1
3
–
Logic-side Ground
GND2
9, 15
–
Bus-side Ground. Both pins are internally connected.
NC
10
–
No Connect. This pin is not connected to any internal circuitry.
R
5
O
Receiver Output
RE
6
I
Receiver Enable Input. This pin has complementary logic.
VCC1
4
–
Logic-side Power Supply
VCC2
16
–
Bus-side Power Supply
Y
11
O
Non-inverting Driver Output
Z
12
O
Inverting Driver Output
6 Specifications
6.1 Absolute Maximum Ratings
See
(1)
MIN
VCC1, VCC2
Input supply voltage
(2)
VA,VB,VY,VZ Voltage at any bus I/O terminal (A, B, Y, Z)
MAX
UNIT
–0.3
6
V
–9
14
V
14
V
V
VD1,VD2
Voltage at D1, D2
V(TRANS)
Voltage input, transient pulse through 100Ω, see Figure 27 (A, B,Y, Z)
–50
50
VI
Voltage input at D, DE or RE terminal
–0.5
7
V
IO
Receiver output current
–10
10
mA
ID1, ID2
Transformer Driver Output Current
450
mA
TJ
Maximum junction temperature
170
°C
TSTG
Storage temperature
150
°C
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values.
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ISO3086T
3
ISO3086T
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
www.ti.com
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS001 (1)
Electrostatic
discharge
V(ESD)
Bus pins and GND1
±6000
Bus pins and GND2
±11000
All pins
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
V
±1500
Machine model (MM), ANSI/ESDS5.2-1996
(1)
(2)
UNIT
±200
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
3.3 V Operation
VCC1
Logic-side supply voltage
VCC2
Bus-side supply voltage
VI or VIC
Voltage at any bus terminal (separately or common-mode)
VIH
High-level input voltage
VIL
Low-level input voltage
VID
Differential input voltage
RL
Differential load resistance
5 V Operation
RE
D, DE
MIN
NOM
MAX
UNIT
3
3.3
3.6
4.5
5
5.5
4.5
5
5.5
V
–7
12
V
2
VCC1
V
V
0.7 VCC1
RE
0
0.8
D, DE
V
0.3 VCC1
A with respect to B
–12
Dynamic
12
V
See Figure 16
54
Driver
Ω
60
–60
60
–8
8
IO
Output Current
TA
Ambient temperature
–40
85
TJ
Operating junction temperature
–40
150
°C
1 / tUI
Signaling Rate
20
Mbps
Receiver
mA
°C
6.4 Thermal Information
ISO3086T
THERMAL METRIC
(1)
DW (SOIC)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
80.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
43.8
°C/W
RθJB
Junction-to-board thermal resistance
49.7
°C/W
ψJT
Junction-to-top characterization parameter
13.8
°C/W
ψJB
Junction-to-board characterization parameter
41.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Power Rating
over operating free-air temperature range (unless otherwise noted)
PARAMETER
PD
4
Maximum device power dissipation
TEST CONDITIONS
VALUE
UNIT
VCC1 = VCC2 = 5.5V, TJ = 150°C, RL = 54Ω,
CL = 50pF (Driver), CL = 15pF (Receiver),
Input a 10 MHz 50% duty cycle square wave
to Driver and Receiver
490
mW
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ISO3086T
ISO3086T
www.ti.com
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
6.6 Electrical Characteristics: Driver
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IO = 0 mA, no load
|VOD|
RL = 54 Ω (RS-485), See Figure 17
Differential output voltage magnitude
RL = 100 Ω (RS-422), See Figure 17
Vtest from –7 V to +12 V, SeeFigure 18
Δ|VOD|
Change in magnitude of the differential
output voltage
VOC(SS)
Steady-state common-mode output voltage
Figure 19
Change in steady-state common-mode
output voltage
VOC(pp)
Peak-to-peak common-mode output voltage See Figure 19
II
Input current
IOZ
VY or VZ = 12 V,
High-impedance state output current, Y or Z VCC2 = 0 V or 5 V, DE = 0 V
pin
VY or VZ = –7 V,
VCC2 = 0 V or 5 V, DE = 0 V
IOS (1)
(1)
Short-circuit output current
TYP
MAX
VCC2
3
4.3
1.5
2.3
2
2.3
V
–0.2
0
0.2
V
1
2.6
3
V
0.1
V
10
µA
–0.1
0.5
D, DE, VI at 0 V or VCC1
V
–10
Other bus pin
at 0 V
Other bus pin
at 0 V
–7 V ≤ VY or VZ ≤ 12 V
UNIT
1.5
See Figure 17 and Figure 18
ΔVOC(SS)
MIN
1
µA
–1
–250
250
mA
TYP
MAX
UNIT
–85
–10
mV
This device has thermal shutdown and output current limiting features to protect in short-circuit fault condition.
6.7 Electrical Characteristics: Receiver
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT(+)
Positive-going input threshold voltage
IO = –8 mA
VIT(–)
Negative-going input threshold voltage
IO = 8 mA
Vhys
Hysteresis voltage (VIT+ – VIT–)
MIN
–200
–115
mV
30
mV
VCC1–0.4
3.1
4
4.8
VOH
High-level output voltage
VID = 200 mV, IO = –8 mA,
See Figure 23
VCC1 = 3.3 V
VOL
Low-level output voltage
VID = 200 mV, IO = 8 mA,
See Figure 23
VCC1 = 3.3 V
0.15
0.4
VCC1 = 5 V
0.15
0.4
IO(Z)
High-impedance state output current
VO = 0 or VCC1, RE = VCC1
VCC1 = 5 V
–1
VA or VB = 12 V
IA, IB
Bus input current
VA or VB = 12 V, VCC2 = 0
VA or VB = –7 V
V
Other input
at 0 V
VA or VB = –7 V, VCC2 = 0
1
40
100
60
130
–100
–40
–100
–30
IIH
High-level input current, RE
VIH = 2. V
–10
10
IIL
Low-level input current, RE
VIL = 0.8 V
–10
10
RID
Differential input resistance
A, B
CID
Differential input capacitance
VI = 0.4 sin (4E6πt) + 0.5 V
96
V
µA
µA
µA
kΩ
7
pF
6.8 Transformer Driver Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
fOSC
RON
Oscillator frequency
Switch on resistance
TEST CONDITIONS
MIN
TYP MAX
VCC1 = 5 V ± 10%, D1 and D2 connected to
transformer
350
450
610
VCC1 = 3.3 V ± 10%, D1 and D2 connected to
transformer
300
400
550
1
2.5
D1 and D2 connected to 50Ω pull-up resistors
kHz
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ISO3086T
UNIT
Ω
5
ISO3086T
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
www.ti.com
Transformer Driver Characteristics (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
tr_D
D1, D2 output rise time
tf_D
D1, D2 output fall time
fSt
Startup frequency
tBBM
(1)
TEST CONDITIONS
VCC1 = 5 V ± 10%, see Figure 29,
MIN
TYP MAX
(1)
VCC1 = 3.3 V ± 10%, see Figure 29,
80
(1)
VCC1 = 3.3 V ± 10%, see Figure 29,
55
(1)
Break before make time delay
350
(1)
VCC1 = 3.3 V ± 10%, see Figure 29,
ns
80
VCC1 = 2.4 V, D1 and D2 connected to transformer
VCC1 = 5 V ± 10%, see Figure 29,
ns
70
(1)
VCC1 = 5 V ± 10%, see Figure 29,
UNIT
kHz
38
(1)
ns
140
D1 and D2 connected to 50Ω pull-up resistors
6.9 Supply Current and Common-Mode Transient Immunity
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP MAX
VCC1 = 3.3 V ±10%
5
8
VCC1 = 5 V ±10%
7
12
RE = 0 V or VCC1, DE = 0 V (driver disabled), No load
10
15
RE = 0 V or VCC1, DE = VCC1 (driver enabled), D = 0 V or VCC1, No Load
10
15
ICC1 (1)
Logic-side quiescent
supply current
DE and RE = 0 V or VCC1 (Driver and Receiver
Enabled or Disabled), D = 0 V or VCC1, No load
ICC2 (1)
Bus-side quiescent
supply current
CMTI
Common-mode
transient immunity
(1)
MIN
See Figure 28, VI = VCC1 or 0 V
25
50
UNIT
mA
mA
kV/µs
ICC1 and ICC2 are measured when device is connected to external power supplies, VCC1 and VCC2. In this case, D1 and D2 are open and
disconnected from external transformer.
6.10 Switching Characteristics: Driver
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay
PWD (1)
Pulse width distortion (|tPHL – tPLH|)
tr, tf
Differential output signal rise time and fall time
tPZH,
tPHZ
Propagation delay, high-impedance-to-high-level output,
Propagation delay, high-level-to-high-impedance output
tPLZ,
tPZL
Propagation delay, low-level to high-impedance output,
Propagation delay, high-impedance to low-level output
(1)
MIN
TYP
MAX
25
45
1
7.5
7
15
See Figure 21
DE at 0 V
25
55
ns
See Figure 22,
DE at 0 V
25
55
ns
See Figure 20
UNIT
ns
Also known as pulse skew
6.11 Switching Characteristics: Receiver
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
tPLH, tPHL
Propagation delay
tsk(p)
Pulse skew (|tPHL – tPLH|)
tr, tr
Output signal rise and fall time
tPHZ,
tPZH
Propagation delay, high-level to high-impedance output
Propagation delay, high-impedance to high-level output
See Figure 25, DE at 0 V
11
22
tPLZ,
tPZL
Propagation delay, low-level to high-impedance output
Propagation delay, high-impedance to low-level output
See Figure 26, DE at 0 V
11
22
6
See Figure 24
103
125
3
15
UNIT
ns
1
ns
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ISO3086T
ISO3086T
www.ti.com
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
6.12 Typical Characteristics
25
60
No Load
TA = 25°C,
16
PRBS Data 2 - 1
ICC2 @ 5 V
50
ICC2 @ 5 V
ICC - Supply Current - mA
ICC - Supply Current - mA
20
15
10
ICC1 @ 5 V
5
5
30
20
10
15
Signaling Rate - Mbps
5
10
15
Signaling Rate - Mbps
20
Figure 2. Supply Current vs Signaling Rate (With Load)
30
34
VCC1 = VCC2 = 5 V,
RL = 54 W,
CL = 50 pF
32
Driver Propagation Delay - ns
Driver Propagation Delay - ns
ICC1 @ 3.3 V
0
0
20
Figure 1. Supply Current vs Signaling Rate (No Load)
28
ICC1 @ 5 V
10
ICC1 @ 3.3 V
0
0
Driver: RL = 54 W, CL = 50 pF,
Receiver: CL = 15 pF,
TA = 25°C,
16
PRBS Data 2 - 1
40
tPHL
26
tPLH
24
VCC1 = 3.3 V,
VCC2 = 5 V,
RL = 54 W,
CL = 50 pF
30
tPHL
28
tPLH
26
24
22
22
20
-40
-15
10
35
60
TA - Free-Air Temperature - °C
20
-40
85
Figure 3. Driver Propagation Delay vs Free-Air Temperature
110
Reveiver Propagation Delay - ns
Reveiver Propagation Delay - ns
VCC1 = VCC2 = 5 V,
CL = 15 pF
104
103
tPHL
101
100
99
85
Figure 4. Driver Propagation Delay vs Free-Air Temperature
105
102
-15
10
35
60
TA - Free-Air Temperature - °C
tPLH
108
VCC1 = 3.3 V,
VCC2 = 5 V,
CL = 15 pF
106
tPHL
104
tPLH
102
98
97
-40
-15
10
35
60
TA - Free-Air Temperature - °C
85
Figure 5. Receiver Propagation Delay vs Free-Air
Temperature
100
-40
-15
10
35
60
TA - Free-Air Temperature - °C
85
Figure 6. Receiver Propagation vs Free-Air Temperature
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ISO3086T
7
ISO3086T
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
www.ti.com
Typical Characteristics (continued)
10
10
VCC1 = VCC2 = 5 V,
9.5
9
Driver Rise, Fall Time - ns
Driver Rise, Fall Time - ns
9.5 RL = 54 W,
CL = 50 pF
9
8.5
8
7.5
tr
7
tf
6.5
8
7
6
5
-40
85
-15
10
35
60
TA - Free-Air Temperature - °C
85
Figure 8. Driver Rise, Fall Time vs Free-Air Temperature
1200
1400
VCC1 = VCC2 = 5 V,
1300 C = 15 pF
L
1100
Receiver Rise, Fall Time - ps
1200
Receiver Rise, Fall Time - ps
tf
6.5
5.5
Figure 7. Driver Rise, Fall Time vs Free-Air Temperature
tr
7.5
6
-15
10
35
60
TA - Free-Air Temperature - °C
RL = 54 W,
CL = 50 pF
8.5
5.5
5
-40
VCC1 = 3.3 V,
VCC2 = 5 V,
tf
1100
1000
900
800
tr
700
VCC1 = 3.3 V,
VCC2 = 5 V,
CL = 15 pF
1000
600
tf
900
tr
800
700
500
400
-40
-15
10
35
60
TA - Free-Air Temperature - °C
600
-40
85
Figure 9. Receiver Rise, Fall Time vs Free-Air Temperature
-100
TA = 25°C
TA = 25°C,
VCC1 = 5 V
-90
VCC2 = 5 V
3
-80
IO - Output Current - mA
VOD - Differential Output Voltage - V
85
Figure 10. Receiver Rise, Fall Time vs Free-Air Temperature
3.5
2.5
VCC2 = 5.5 V
2
100 W
1.5
VCC2 = 4.5 V
1
-70
-60
-50
-40
-30
-20
0.5
0
0
50 W
10
20
30
40
50
IL - Load Current - mA
-10
60
0
0
70
Figure 11. Driver Differential Output Voltage vs Load
Current
8
-15
10
35
60
TA - Free-Air Temperature - °C
1
2
3
VO - Output Voltage - V
4
5
Figure 12. Receiver High-Level Output Current vs HighLevel Output Voltage
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ISO3086T
ISO3086T
www.ti.com
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
Typical Characteristics (continued)
90
60
TA = 25°C,
VCC2 = 5 V
TA = 25°C,
80 VCC1 = 5 V
40
II - Bus Input Current - mA
IO - Output Current - mA
70
60
50
40
30
20
0
-20
20
-40
10
-60
-7
0
0
1
2
3
VO - Output Voltage - V
4
5
Figure 13. Receiver Low-Level Output Current vs Low-Level
Output Voltage
-4
-1
2
5
8
VI - Bus Input Voltage - V
11
Figure 14. Input Bias Current vs Bus Input Voltage
1
2.1
VCC2 = 5 V,
0.9
VID - Differential Input Voltage - pk
VOD - Differential Output Voltage - V
RL = 54 W
2.08
2.06
2.04
2.02
2
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
1.98
-40
-15
10
35
60
TA - Free-Air Temperature - °C
0
0
85
Figure 15. Differential Output Voltage vs Free-Air
Temperature
2
4
6
8
10 12 14
Signaling Rate - Mbps
16
18
20
Figure 16. Recommended Minimum Differential Input
Voltage vs Signaling Rate
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ISO3086T
9
ISO3086T
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
www.ti.com
7 Parameter Measurement Information
VCC1
VCC2
IY
DE
Y
RL
VOD
D
D
0 or 3 V
.
Z
GND1
375 W
DE
Y
II
0 or
VCC1
+
VOD
-
Z
60 W
IZ
GND2
VI
375 W
GND2
VY
VZ
GND1
VTEST =
-7 V to 12 V
GND2
Figure 17. Driver VOD Test and Current Definitions
VCC1
IY
DE
27 W
±1%
Y
II
Input
D
VOD
Z
GND2
GND1
VI
27 W
±1%
IZ
VZ
GND1
Figure 18. Driver VOD With Common-Mode Loading
Test Circuit
Y
VY
Z
VZ
VOC
VOC(SS)
VOC(p-p)
VOC
VY
Input Generator: PRR= 100 kHz, 50 % duty
cycle, t r < 6ns , t f <6 ns , ZO = 50 W
GND2
Figure 19. Test Circuit and Waveform Definitions For The Driver Common-Mode Output Voltage
3V
DE
VCC1
Y
VOD
D
Input
Generator
VI
RL= 54 W
±1%
Z
50%
VI
CL = 50pF
± 20%
tpLH
50W
C L includes fixture and
GND1
instrumentation capacitance
Generator: PRR = 100 kHz, 50 % duty cycle,
t r < 6ns , t f <6 ns , ZO = 50W
50%
tpHL
90%
50 %
10 %
VOD
VOD(H)
90%
tr
tf
50 %
10%
VOD(L)
Figure 20. Driver Switching Test Circuit and Voltage Waveforms
Y
D
S1
3V Y
0V Z
S1
D
50%
0V
Z
50 W
CL includes fixture and
instrumentation
capacitance
GND1
Generator: PRR = 50 kHz, 50% duty
cycle, tr <6ns, tf <6ns, ZO = 50 W
tpZH
RL = 110 W
±1 %
C L = 50 pF ± 20 %
VI
50%
VI
DE
Input
Generator
3V
VO
90%
VO
VOH
50%
tpHZ
»0V
GND2
Figure 21. Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
10
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ISO3086T
ISO3086T
www.ti.com
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
Parameter Measurement Information (continued)
VCC2
3V
Y
D
S1
3V Y
0V Z
R L = 110 W
± 1%
VO
S1
D
Generator: PRR=50 kHz, 50% duty cycle,
t r < 6ns, t f < 6ns, ZO = 50 W
VI
50%
0V
tpZL
Z
DE
tpLZ
C L = 50 pF ± 20 %
Input
Generator
50%
VI
VO
CL includes fixture and
instrumentation
capacitance
50 W
GND1
VCC2
50%
10%
V OL
GND2
Figure 22. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveform
A
IA
R
VA
B
VIC
VA + V B
IO
VID
VB
VO
IB
2
Figure 23. Receiver Voltage and Current Definitions
3V
A
Input
Generator
VI
50 W
1.5 V
B
0V
CL includes fixture and
instrumentation capacitance
Generator: PRR =100 kHz , 50 % duty cycle,
t < 6ns , t < 6ns , Z = 50 W
O
r
f
50 %
tpHL
tpLH
CL = 15 pF
± 20 %
RE
50 %
VI
R VO
90 %
50 %
10 %
50 %
VO
tf
tr
V OH
V OL
Figure 24. Receiver Switching Test Circuit and Waveforms
V CC
A
1.5 V
R
B
0 V
RE
1 k W ±1%
VO
VI
VI
50 %
50 %
C L = 15 pF ± 20 %
CL includes fixture
and instrumentation
capacitance
Input
Generator
3V
S1
0V
tpHZ
tpZH
VO
90%
VOH
50 %
»0V
50 W
Generator: PRR =100 kHz , 50 % duty cycle ,
t r<6ns , t f<6ns , Z O = 50 W
Figure 25. Receiver Enable Test Circuit and Waveforms, Data Output High
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ISO3086T
11
ISO3086T
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
www.ti.com
Parameter Measurement Information (continued)
V CC
A
0 V
R
VO
B
1.5 V
1 kW ± 1 %
3V
S1
VI
C L = 15 pF ± 20 %
RE
50%
50%
0V
CL includes fixture
and instrumentation
capacitance
tpLZ
tpZL
VCC
Input
Generator
VI
50 W
50%
VO
10%
Generator : PRR =100 kHz , 50 % duty cycle ,
tr <6ns ,t f <6ns , Z O = 50 W
VOL
Figure 26. Receiver Enable Test Circuit and Waveforms, Data Output Low
0 V or 3 V
DE
A
Y
D
R
Z
100 W
±1%
+
–
Pulse Generator
15 ms duration
1% Duty Cycle
tr, tf £ 100 ns
B
100 W
±1%
RE
0 V or 3 V
+
–
Figure 27. Transient Over-Voltage Test Circuit
C = 0.1 m F
± 1%
2.0 V
V CC2
V CC 1
A
C = 0.1 m F ± 1%
DE
GND 1
D
54 W
S1
V OH or V OL
B
Y
0.8 V
1.5 V or 0 V
R
54 W
RE
V OH or V OL
Z
1 kW
0 V or 1.5 V
GND1
GND2
C L = 15 pF
( includes probe and
jig capacitance
)
V TEST
Figure 28. Common-Mode Transient Immunity Test Circuit
12
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ISO3086T
ISO3086T
www.ti.com
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
Parameter Measurement Information (continued)
tf_D
tr_D
90%
D1
10%
tBBM
tBBM
90 %
D2
10 %
tf_D
tr_D
Figure 29. Transition Times and Break-Before-Make Time Delay for D1, D2 Outputs
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ISO3086T
13
ISO3086T
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
www.ti.com
8 Detailed Description
8.1 Overview
ISO3086T is an isolated full-duplex differential transceiver with integrated transformer driver. The integrated
transformer driver supports elegant secondary power supply design. This device is rated to provide galvanic
isolation up to 4242 VPK per VDE and 2500 VRMS per UL. It has active-high driver enable and active-low receiver
enable to control the data flow. It is suitable for data transmission up to 20 Mbps.
When the driver enable pin, DE, is logic high, the differential outputs Y and Z follow the logic states at data input
D. A logic high at D causes Y to turn high and Z to turn low. In this case the differential output voltage defined as
VOD = V(Y) – V(Z) is positive. When D is low, the output states reverse, Z turns high, Y becomes low, and VOD is
negative. When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant.
The DE pin has an internal pulldown resistor to ground, thus when left open the driver is disabled (highimpedance) by default. The D pin has an internal pullup resistor to VCC, thus, when left open while the driver is
enabled, output Y turns high and Z turns low.
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = V(A) – V(B) is positive and higher than the positive input threshold, VIT+, the receiver output, R,
turns high. When VID is negative and lower than the negative input threshold, VIT– , the receiver output, R, turns
low. If VID is between VIT+ and VIT– the output is indeterminate. When RE is logic high or left open, the receiver
output is high-impedance and the magnitude and polarity of VID are irrelevant. Internal biasing of the receiver
inputs causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the
bus lines are shorted (short-circuit), or the bus is not actively driven (idle bus).
8.2 Functional Block Diagram
D2
1
2 OSC
5
R
6
RE
7
DE
D
14
8
GALVANIC ISOLATIO N
D1
14
A
13
12
B
Z
11
Y
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ISO3086T
ISO3086T
www.ti.com
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
8.3 Feature Description
8.3.1 Insulation and Safety Related Specifications for 16 DW Package
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Minimum air gap (Clearance (1))
Shortest terminal to terminal distance through air
8
mm
L(I02)
Minimum external tracking (Creepage (1))
Shortest terminal to terminal distance across the
package surface
8
mm
CTI
Comparative Tracking Index (Tracking
resistance)
DIN EN 60112 (VDE 0303-11); IEC 60112
DTI
Distance through the insulation
Minimum Internal Gap (Internal Clearance)
RIO
Isolation resistance
Input to output, VIO = 500 V, all pins on each
side of the barrier tied together creating a twoterminal device, TA = 25 °C
CIO
Barrier capacitance Input to output
CI
Input capacitance to ground
L(I01)
(1)
400
V
0.008
mm
>1012
Ω
VIO = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5
V
2
pF
VI = 0.4 sin (2πft), f = 1 MHz
2
pF
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed circuit board do not reduce this distance. Techniques such as inserting grooves and/or ribs on a printed circuit board are
used to help increase these specifications.
8.3.1.1 IEC 60664-1 Ratings Table
PARAMETER
TEST CONDITIONS
SPECIFICATION
Material group
II
Overvoltage category / Installation
classification for basic insulation
Rated mains voltage ≤ 150 VRMS
I-IV
Rated mains voltage ≤ 300 VRMS
I-III
8.3.1.2 DIN V VDE V 0884-10 Insulation Characteristics (1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
VIORM
VPR
TEST CONDITIONS
SPECIFICATION
UNIT
566
VPK
Method b1, VPR = VIORM × 1.875,
100% Production test with t = 1 s,
Partial discharge < 5 pC
1062
VPK
Method a, After environmental tests subgroup 1,
VPR = VIORM × 1.6, t = 10 s,
Partial discharge < 5pC
906
After Input/Output Safety Test Subgroup 2/3,
VPR = VIORM x 1.2, t = 10 s,
Partial discharge < 5 pC
680
Maximum working isolation voltage
Input to output test voltage
VIOTM
Maximum transient isolation voltage
t = 60 s (Qualification)
t = 1 s (100% Production)
4242
VPK
VIOSM
Maximum surge isolation voltage
Tested per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.3 x VIOSM = 4000 VPK (Qualification Test)
3077
VPK
RS
Isolation resistance
VIO = 500 V at TS = 150 °C
> 109
Ω
Pollution degree
(1)
2
Climatic Classification 40/125/21
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ISO3086T
15
ISO3086T
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
www.ti.com
8.3.1.3 Regulatory Information
VDE
CSA
UL
Certified according to DIN V VDE V 088410(VDE V 0884-10):2006-12 and DIN EN
61010-1 (VDE 0411-1)
Approved according to CSA Component
Acceptance Notice 5A, IEC 60959-1 and IEC
61010-1
Approved under UL 1577 Component
Recognition Program
Basic Insulation
Maximum Transient Isolation Voltage, 4242 VPK
Maximum Surge Isolation Voltage, 3077 VPK
Maximum Working Isolation Voltage, 566 VPK
3000 VRMS Isolation Rating;
Reinforced insulation per CSA 61010-1-04 and
IEC 61010-1 2nd Ed. 150 VRMS working voltage;
Basic insulation per CSA 61010-1-04 and IEC
61010-1 2nd Ed. 600 VRMS working voltage;
Basic insulation per CSA 60950-1-07 and IEC
60950-1 2nd Ed. 760 VRMS working voltage
Single Protection, 2500 VRMS (1)
Certificate Number: 40016131
Master Contract Number: 220991
File Number: E181974
(1)
Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
8.3.1.4 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the IO can allow low resistance to ground or the supply. Without current limiting, sufficient power is
dissipated to overheat the die and damage the isolation barrier—potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
IS
Safety input, output, or supply current
TS
Maximum safety temperature
DW-16
MIN
θJA = 80.5°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C
TYP
MAX
UNIT
327
mA
150
°C
The safety-limiting constraint is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Characteristics table is
that of a device installed on a High-K Test Board for Leaded Surface Mount Packages. The power is the
recommended maximum input voltage times the current. The junction temperature is then the ambient
temperature plus the power times the junction-to-air thermal resistance.
350
VCC1 = VCC2 = 5.5 V
Safety Limiting Current - mA
300
250
200
150
100
50
0
0
50
100
Temperature - °C
150
200
Figure 30. Thermal Derating Curve per VDE
16
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ISO3086T
ISO3086T
www.ti.com
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
8.4 Device Functional Modes
Table 1 and Table 2 are the function tables for the ISO3086T driver and receiver.
Table 1. Driver Function Table (1)
(1)
INPUT
ENABLE
(D)
(DE)
Y
OUTPUTS
Z
H
H
H
L
L
H
L
H
X
L
hi-Z
hi-Z
X
OPEN
hi-Z
hi-Z
OPEN
H
H
L
H = High Level, L= Low Level, X = Don’t Care, hi-Z = High Impedance (off)
Table 2. Receiver Function Table (1)
(1)
DIFFERENTIAL INPUT
VID = (VA – VB)
ENABLE
(RE)
OUTPUT
(R)
–0.01 V ≤ VID
L
H
–0.2 V < VID –0.01 V
L
?
VID ≤ –0.2 V
L
L
X
H
hi-Z
X
OPEN
hi-Z
Open circuit
L
H
Short Circuit
L
H
Idle (terminated) bus
L
H
H = High Level, L= Low Level, X = Don't Care, hi-Z = High Impedance (Off), ? = Indeterminate
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ISO3086T
17
ISO3086T
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
www.ti.com
8.4.1 Device I/O Schematics
B Input
A Input
VCC 2
VCC 2
16V
Input
36 kW
16V
36 kW
180 kW
180 k W
Input
16V
36 k W
16V
R Output
36 kW
Y and Z Outputs
VCC 1
VCC 2
16V
4W
Output
output
6 .5 W
16V
Figure 31. Equivalent Circuit Schematics
18
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ISO3086T
ISO3086T
www.ti.com
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
DE Input
D, RE Input
VCC 1
VCC 1
VCC 1
VCC 1
VCC 1
1 MW
input
500 W
input
500 W
1 MW
Figure 32. Equivalent Circuit Schematics
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ISO3086T
19
ISO3086T
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO308T consists of an RS-485 transceiver commonly used for asynchronous data transmissions. Fullduplex implementation requires two signal pairs (four wires), and allows each node to transmit data on one pair
while simultaneously receiving data on the other pair. To eliminate line reflections, each cable end is terminated
with a termination resistor, R(T), whose value matches the characteristic impedance, Z0, of the cable. This
method, known as parallel termination, allows for higher data rates over longer cable length.
Y
R
D
Z
A
R(T)
R(T)
B
R
R
DE
RE
Master
RE
D
Slave
B
R
A
DE
Z
R(T)
R(T)
A
B
Z
Y
D
D
Y
R Slave
D
R RE DE D
Figure 33. Half-Duplex Transceiver Configurations
9.2 Typical Application
4
X-FMR
8
3
2
7
6
1
5
LDO
D1
1
C4 C5
3
2
C1
IN
OUT
5
EN
C6
GND NC
1
D2
1
VCC2
D1
16
C3
2
C2
Control
Circuitry
D2
4 V
CC1
3
GND1
5
R
6
RE
7
DE
8
D
A
B
Z
Y
Isolated Supply to
other Components
14
13
12
RS-485 Bus
Interface
11
15
GND2
9, 10
ISO3086T
Figure 34. Typical Application Circuit
20
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ISO3086T
ISO3086T
www.ti.com
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
Typical Application (continued)
9.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
Table 3. Design Parameters
PARAMETER
VALUE
Pullup and Pulldown Resistors
1 kΩ to 10 kΩ
Decoupling Capacitors
100 nF
9.2.2 Detailed Design Procedure
9.2.2.1 Transient Voltages
Isolation of a circuit insulates it from other circuits and earth so that noise develops across the insulation rather
than circuit components. The most common noise threat to data-line circuits is voltage surges or electrical fast
transients that occur after installation and the transient ratings of the ISO3086T are sufficient for all but the most
severe installations. However, some equipment manufacturers use their ESD generators to test transient
susceptibility of their equipment and can easily exceed insulation ratings. ESD generators simulate static
discharges that may occur during device or equipment handling with low-energy but very high voltage transients.
Figure 35 models the ISO3086T bus IO connected to a noise generator. CIN and RIN is the device and any other
stray or added capacitance or resistance across the A or B pin to GND2, CISO and RISO is the capacitance and
resistance between GND1 and GND2 of the ISO3086T plus those of any other insulation (transformer, etc.), and
we assume stray inductance negligible. From this model, the voltage at the isolated bus return is shown in
Equation 1 and will always be less than 16 V from VN.
Z ISO
vGND2 = vN
ZISO + ZIN
(1)
If the ISO3086T are tested as a stand-alone device, RIN= 6 × 104Ω, CIN= 16 × 10-12 F, RISO= 109Ω and
CISO= 10-12 F.
In Figure 35 the resistor ratio determines the voltage ratio at low frequency and it is the inverse capacitance ratio
at high frequency. In the stand-alone case and for low frequency, use Equation 2, or essentially all of noise
appears across the barrier.
vGND2
RISO
109
=
=
vN
RISO + RIN
109 + 6 ´ 104
(2)
At very high frequency, Equation 3 is true, and 94% of VN appears across the barrier.
1
v GND2
CISO
1
1
=
=
=
= 0.94
1
1
1
C
vN
+
1 + ISO 1 +
16
CISO
CIN
CIN
(3)
As long as RISO is greater than RIN and CISO is less than CIN, most of transient noise appears across the isolation
barrier, as it should.
TI recommends not testing equipment transient susceptibility with ESD generators or consider product claims of
ESD ratings above the barrier transient ratings of an isolated interface. ESD is best managed through recessing
or covering connector pins in a conductive connector shell and installer training.
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ISO3086T
21
ISO3086T
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
www.ti.com
A, B, Y, or Z
CIN
RIN
VN
16 V
Bus Return (GND2)
CISO
RISO
System Ground(GND1)
Figure 35. Noise Model
9.2.3 Application Curve
At maximum working voltage, ISO3086T isolation barrier has more than 28 years of life.
WORKING LIFE -- YEARS
100
VIORM at 566 VPK
28
10
0
120
250
500
750
880
1000
WORKING VOLTAGE (V IORM ) -- VPK
Figure 36. Time-Dependent Dielectric Breakdown Test Results
22
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ISO3086T
ISO3086T
www.ti.com
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, TI recommends a 0.1-µF bypass capacitor at
input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. This device is used in applications where only a single primary-side power supply is available. Isolated
power can be generated for the secondary-side with the help of integrated transformer driver.
11 Layout
11.1 Layout Guidelines
ON-chip IEC-ESD protection is good for laboratory and portable equipment but never sufficient for EFT and
surge transients occurring in industrial environments. Therefore, robust and reliable bus node design requires the
use of external transient protection devices. Because ESD and EFT transients have a wide frequency bandwidth
from approximately 3-MHz to 3-GHz, high-frequency layout techniques must be applied during PCB design. A
minimum of four layers is required to accomplish a low EMI PCB design (see Figure 37).
• Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power
plane, and low-frequency signal layer.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
• Place the protection circuitry close to the bus connector to prevent noise transients from penetrating your
board.
• Use VCC and ground planes to provide low-inductance. High-frequency currents might follow the path of least
inductance and not necessarily the path of least resistance.
• Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
• Apply 0.1-µF bypass capacitors as close as possible to the VCC-pins of transceiver, UART, and controller ICs
on the board.
• Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to
minimize effective via-inductance.
• Use 1-kΩ to 10-kΩ pullup and pulldown resistors for enable lines to limit noise currents in these lines during
transient events.
• Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified
maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the
transceiver and prevent it from latching up.
• While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
If an additional supply voltage plane or signal layer is needed, add a second power and ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
NOTE
For detailed layout recommendations, see Application Note Digital Isolator Design Guide,
SLLA284.
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ISO3086T
23
ISO3086T
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
www.ti.com
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 37. Recommended Layer Stack
24
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ISO3086T
ISO3086T
www.ti.com
SLLSE27D – JANUARY 2011 – REVISED OCTOBER 2015
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Isolated, Full-Duplex, 20-Mbps, 3.3-V to 5-V RS-485 Interface (SLUU469)
• Digital Isolator Design Guide (SLLA284)
• Isolation Glossary (SLLA353)
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ISO3086T
25
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
ISO3086TDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ISO3086T
ISO3086TDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ISO3086T
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ISO3086TDWR
Package Package Pins
Type Drawing
SOIC
DW
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
10.75
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.7
2.7
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO3086TDWR
SOIC
DW
16
2000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DW 16
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
B
7.6
7.4
NOTE 4
2.65 MAX
B
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising