Texas Instruments | ISO1176T Isolated Profibus RS-485 Transceiver with Integrated Transformer Driver (Rev. G) | Datasheet | Texas Instruments ISO1176T Isolated Profibus RS-485 Transceiver with Integrated Transformer Driver (Rev. G) Datasheet

Texas Instruments ISO1176T Isolated Profibus RS-485 Transceiver with Integrated Transformer Driver (Rev. G) Datasheet
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ISO1176T
SLLSE28G – OCTOBER 2010 – REVISED OCTOBER 2015
ISO1176T Isolated Profibus RS-485 Transceiver with Integrated Transformer Driver
1 Features
•
1
•
•
•
•
•
•
•
•
Meets or Exceeds the Requirements of EN 50170
and TIA/EIA-485-A
Signaling Rates up to 40 Mbps
Easy Isolated Power Design with Integrated
Transformer Driver
Typical Efficiency > 60% (ILOAD = 100 mA) - see
SLUU471
Differential Output exceeds 2.1 V (54-Ω Load)
Low Bus Capacitance 10 pF (Maximum)
Fail-safe Receiver for Bus Open, Short, or Idle
50-kV/µs Typical Transient Immunity
Safety and Regulatory Approvals
– 4242 VPK Basic Insulation per DIN V VDE V
0884-10 and DIN EN 61010-1
– 2500 VRMS Isolation for 1 minute per UL 1577
– CSA Component Acceptance Notice 5A, IEC
60950-1 and IEC 61010-1 Standards
The galvanically isolated differential bus transceiver is
an integrated circuit designed for bi-directional data
communication on multipoint bus-transmission lines.
The transceiver combines a galvanically isolated
differential line driver and differential input line
receiver. The driver has an active-high enable with
isolated enable-state output on the ISODE pin (pin
10) to facilitate direction control. The driver differential
outputs and the receiver differential inputs connect
internally to form a differential input/output (I/O) bus
port that is designed to offer minimum loading to the
bus whenever the driver is disabled or VCC2 = 0.
Any cabled I/O can be subjected to electrical noise
transients from various sources. These noise
transients can cause damage to the transceiver
and/or near-by sensitive circuitry if they are of
sufficient magnitude and duration. The ISO1176T can
significantly reduce the risk of data corruption and
damage to expensive control circuits.
The device is characterized for operation over the
ambient temperature range of –40°C to 85°C.
•
2 Applications
•
•
•
•
•
•
Profibus®
Factory Automation
Networked Sensors
Motor/motion Control
HVAC and Building Automation Networks
Networked Security Stations
Device Information(1)
PART NUMBER
BODY SIZE (NOM)
SOIC (16)
10.30 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application
X-FMR
3 Description
4
8
3
2
7
6
LDO
D1
1
C4 C5
3
2
C1
1
The ISO1176T is an isolated differential line
transceiver with integrated oscillator outputs that
provide the primary voltage for an isolation
transformer. The device is ideal for long transmission
lines because the ground loop is broken to allow the
device to operate with a much larger common-mode
voltage range.
The symmetrical isolation barrier of each device is
tested to provide 4242VPK of isolation per VDE for 60
seconds between the line transceiver and the logiclevel interface.
PACKAGE
ISO1176T
5
OUT
IN
5
C6
EN
GND
NC
4
D2
1
2
4
C2
3
5
6
Control
Circuitry
D1
VCC2
16
C3
Isolated Supply to
other Components
D2
VCC1
B
GND1
A
R
ISODE
13
12
10
Profibus
Interface
RE
7
DE
GND2
D
GND2
8
14, 15
9, 11
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO1176T
SLLSE28G – OCTOBER 2010 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
7
1
1
1
2
4
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics: Power Rating ................... 5
Electrical Characteristics: ISODE-Pin ....................... 6
Electrical Characteristics: RS-485 Driver.................. 6
Electrical Characteristics: Receiver .......................... 7
Supply Current .......................................................... 7
Transformer Driver Characteristics ......................... 8
Switching Characteristics: RS-485 Driver ............... 9
Switching Characteristics: Receiver........................ 9
Typical Characteristics .......................................... 10
Parameter Measurement Information ................ 12
8
Detailed Description ............................................ 17
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
17
17
18
20
Application and Implementation ........................ 23
9.1 Application Information............................................ 23
9.2 Typical Application ................................................. 23
10 Power Supply Recommendations ..................... 26
11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
11.2 Layout Example .................................................... 27
12 Device and Documentation Support ................. 28
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
13 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (October 2012) to Revision G
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
VDE standard changed to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 ...................................................................... 1
•
Added Maximum Device Power Dissipation to Power Rating Table. .................................................................................... 5
Changes from Revision E (August 2011) to Revision F
•
Page
Changed From "ISO1176T Reference Design SLLU471" To: "ISO1176T Reference Design SLUU471"........................... 28
Changes from Revision D (May 2011) to Revision E
Page
•
Deleted the MIN and MAX values for tr_D, tf_D and tBBM specifications in the Transformer Driver Characteristics table. ....... 8
•
Changed test conditions from 1.9 V to 2.4 V, and changed TYP value from 230 to 350 for fSt specification in the
Transformer Driver Characteristics table................................................................................................................................ 8
Changes from Revision C (February 2011) to Revision D
Page
•
Added Figure 33 ..................................................................................................................................................................... 1
•
Moved the Pin Description closer to the Pin drawing............................................................................................................. 4
2
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Changes from Revision B (December 2010) to Revision C
Page
•
Deleted ROFF from the TRANSFORMER DRIVER CHARACTERISTICS table ..................................................................... 8
•
Added a Typ value of 23ns to Prop delay time for VCC1 = 5V in the RS-485 DRIVER SWITCHING
CHARACTERISTIC table ....................................................................................................................................................... 9
•
Added a Typ value of 25ns to Prop delay time for VCC1 = 3.3V in the RS-485 DRIVER SWITCHING
CHARACTERISTIC table ....................................................................................................................................................... 9
•
Changed θJA = 212°C/W To: θJA = 76°C/W, Changed the IS Max value From: 128mA To: 347mA, and changed
paragraph two in the IEC SAFETY LIMITING VALUES section .......................................................................................... 19
•
Changed Figure 29............................................................................................................................................................... 19
Changes from Revision A (December 2010) to Revision B
Page
•
Changed the Steady-state short-circuit output current - Test Conditions and values............................................................ 6
•
Changed the Oscillator frequency values............................................................................................................................... 8
•
Changed the D1, D2 output rise time values ......................................................................................................................... 8
Changes from Revision initial (October 2010) to Revision A
Page
•
Updated transformer driver characteristics............................................................................................................................. 8
•
Added Thermal Table data ................................................................................................................................................... 19
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SLLSE28G – OCTOBER 2010 – REVISED OCTOBER 2015
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5 Pin Configuration and Functions
DW Package
16-Pin SOIC
Top View
D1
D2
1
16
2
15
GND1
VCC1
R
RE
DE
D
3
4
14
13
5
12
6
11
7
10
8
9
VCC2
GND2
GND2
B
A
GND2
ISODE
GND2
Pin Functions
PIN
NAME
I/O
NO.
DESCRIPTION
A
12
I/O
Non-inverting Driver Output / Receiver Input
B
13
I/O
Inverting Driver Output / Receiver Input
D
8
I
Driver Input
D1
1
O
Transformer Driver Terminal 1, Open Drain Output
D2
2
O
Transformer Driver Terminal 2, Open Drain Output
DE
7
I
Driver Enable Input
GND1
3
—
Logic-side Ground
GND2
9, 11, 14, 15
—
Bus-side Ground. All pins are internally connected.
ISODE
10
O
Bus-side Driver Enable Output Status
R
5
O
Receiver Output
RE
6
I
Receiver Enable Input. This pin has complementary logic.
VCC1
4
—
Logic-side Power Supply
VCC2
16
—
Bus-side Power Supply
6 Specifications
6.1 Absolute Maximum Ratings
See
(1)
VCC1,
VCC2
Input supply voltage
(2)
Voltage at any bus I/O terminal
VO
MIN
MAX
UNIT
–0.5
7
V
–9
14
V
14
V
7
V
Voltage at D1, D2
VI
Voltage input at D, DE or RE terminal
–0.5
IO
Receiver output current
–10
10
mA
ID1, ID2 Transformer Driver Output Current
450
mA
TJ
Maximum junction temperature
170
°C
TSTG
Storage temperature
150
°C
(1)
(2)
4
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to the referenced network ground terminal and are peak voltage
values.
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6.2 ESD Ratings
VALUE
V(ESD)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS001 (1)
Bus pins to GND1
±6000
Bus pins to GND2
±10000
All pins
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
V
±1500
Machine model (MM), ANSI/ESDS5.2-1996
(1)
(2)
UNIT
±200
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Logic side supply voltage, VCC1 (with respect to GND1)
VCC
Bus side supply voltage, VCC2 (with respect to GND2)
VCM
Voltage at either bus I/O terminal
VIH
High-level input voltage
VIL
Low-level input voltage
VID
Differential input voltage
NOM
MAX
3
5.5
4.75
5.25
A, B
–7
12
RE
2
VCC1
D, DE
0
TA
Ambient temperature
TJ
Operating junction temperature
1 / tUI
Signaling Rate
V
V
0.8
D, DE
Output Current
V
0.7 VCC1
RE
IO
UNIT
V
0.3 VCC1
A with respect to B
–12
12
RS-485 driver
–70
70
–8
8
-40
85
Receiver
V
mA
°C
150
°C
40
Mbps
6.4 Thermal Information
ISO1176T
THERMAL METRIC (1)
DW (SOIC)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
76
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
37.9
°C/W
RθJB
Junction-to-board thermal resistance
44.6
°C/W
ψJT
Junction-to-top characterization parameter
12.1
°C/W
ψJB
Junction-to-board characterization parameter
37.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics: Power Rating
over operating free-air temperature range (unless otherwise noted)
PARAMETER
PD
Maximum device power dissipation
TEST CONDITIONS
VCC1 = 5.5 V, VCC2 = 5.25 V, TJ = 150°C, CL =
50 pf, RL = 54 Ω
Input a 20 MHz 50% duty cycle square wave
VALUE
UNIT
719
mW
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6.6 Electrical Characteristics: ISODE-Pin
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
TEST CONDITIONS
MIN
TYP
IOH = –8mA
VCC2 – 0.8
4.6
IOH = –20µA
VCC2 – 0.1
5
MAX
UNIT
V
IOL = 8mA
0.2
0.4
IOL = 20µA
0
0.1
V
6.7 Electrical Characteristics: RS-485 Driver
over recommended operating conditions (unless otherwise noted)
PARAMETER
VOD
Open-circuit differential output voltage
|VOD(SS)|
Steady-state differential output voltage
magnitude
|ΔVOD(SS)|
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC2
V
|VA – VB|, See Figure 9
1.5
See Figure 10 and Figure 14
2.1
See Figure 11, Common-mode loading
with Vtest from –7 V to +12 V
2.1
Change in steady-state differential output
voltage between logic states
See Figure 12 and Figure 13, RL = 54 Ω
-0.2
0.2
VOC(SS)
Steady-state common-mode output
voltage
See Figure 12 and Figure 13, RL = 54 Ω
2
3
ΔVOC(SS)
Change in steady-state common-mode
output voltage
See Figure 12 and Figure 13, RL = 54 Ω
–0.2
0.2
VOC(pp)
Peak-to-peak common-mode output
voltage
See Figure 12 and Figure 13, RL = 54 Ω
VOD(ring)
Differential output voltage over and under
shoot
See Figure 14 and Figure 17
II
Input current
D, DE at 0 V or VCC1
IO(OFF)
Power-off output current
VCC2 = 0 V
IOZ
High-impedance output current
DE at 0 V
IOS(P)
Peak short-circuit output current
IOS(SS)
Steady-state short-circuit output current
COD
Differential output capacitance
CMTI
Common-mode transient immunity
6
See
Figure 16,
DE at VCC1
V
V
V
0.5
10%
–10
10
VOD(pp)
µA
See receiver input current
See receiver input current
VOS = –7 V to 12 V
–250
VOS = 12 V, D at GND1
VOS = –7 V, D at VCC1
250
135
–135
mA
mA
See receiver CIN
See Figure 27
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25
kV/µs
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6.8 Electrical Characteristics: Receiver
over recommended operating conditions (unless otherwise noted)
PARAMETER
VIT(+)
Positive-going input threshold voltage
VIT(–)
Negative-going input threshold voltage
Vhys
Hysteresis voltage (VIT+ – VIT–)
VOH
High-level output voltage
VOL
Low-level output voltage
VOH
High-level output voltage
VOL
Low-level output voltage
TEST CONDITIONS
See Figure 23
VCC1 = 3.3 V ± 10%
and VCC2 = 5 V ±
5%
IO = 8mA
VID = 200 mV,
See Figure 23
VID = –200 mV,
See Figure 23
VCC1 = 5 V ± 10%
and VCC2 = 5 V ±
5%
VID = 200 mV,
See Figure 23
VID = –200 mV,
See Figure 23
IA, IB
IA(off),
IB(off)
Bus pin input current
MIN
IO = –8mA
VI = –7 or 12 V, Other input = 0 V
–200
TYP
MAX
UNIT
–80
–10
mV
–120
mV
25
mV
IOH = –8 mA
VCC1 – 0.4
3
IOH = –20 µA
VCC1 – 0.1
3.3
V
IOL = 8 mA
0.2
0.4
IOL = 20 µA
0
0.1
IOH = –8 mA
VCC1 – 0.8
4.6
IOH = –20 µA
VCC1 – 0.1
5
V
IOL = 8 mA
0.2
0.4
IOL = 20 µA
0
0.1
VCC2 = 4.75 V
or 5.25 V
V
V
–160
200
µA
µA
VCC2 = 0 V
II
Receiver enable input current
RE = 0 V
–50
50
IOZ
High-impedance state output current
RE = VCC1
–1
1
RID
Differential input resistance
A, B
60
CID
Differential input capacitance
Test input signal is a 1-MHz sine wave with 1-Vpp
amplitude. CD is measured across A and B.
7
CMR
Common mode rejection
See Figure 26
4
µA
kΩ
10
pF
V
6.9 Supply Current
over operating free-air temperature range (unless otherwise noted)
PARAMETER
ICC1
(1)
ICC2 (1)
(1)
Logic-side quiescent supply
current
Bus-side quiescent supply current
TEST CONDITIONS
VCC1 = 3.3 V ± 10%, DE, RE = 0V or VCC1,
No load
VCC1 = 5 V ± 10%, DE, RE = 0V or VCC1, No
load
VCC2 = 5 V ± 5%, DE, RE = 0V or VCC1, No
load
MIN
TYP
MAX
UNIT
4.5
8
mA
7
11
mA
13.5
18
mA
ICC1 and ICC2 are measured when device is connected to external power supplies. D1 and D2 are disconnected from external
transformer.
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6.10 Transformer Driver Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
fOSC
RON
tr_D
tf_D
fSt
tBBM
8
Oscillator frequency
Switch on resistance
D1, D2 output rise time
D1, D2 output fall time
Startup frequency
Break before make time delay
TEST CONDITIONS
MIN
TYP
MAX
VCC1 = 5 V ± 10%, D1 and D2 connected to
Transformer
350
450
610
VCC1 = 3.3 V ± 10%, D1 and D2 connected to
Transformer
300
400
550
D1 and D2 connected to 50Ω pullup resistors
1
2.5
VCC1 = 5 V ± 10%, See Figure 28, D1 and D2
connected to 50-Ω pullup resistors
80
VCC1 = 3.3 V ± 10%, See Figure 28, D1 and
D2 connected to 50-Ω pullup resistors
70
VCC1 = 5 V ± 10%, See Figure 28, D1 and D2
connected to 50-Ω pullup resistors
55
VCC1 = 3.3 V ± 10%, See Figure 28, D1 and
D2 connected to 50-Ω pullup resistors
80
VCC1 = 2.4 V, D1 and D2 connected to
Transformer
VCC1 = 3.3 V ± 10%, See Figure 28, D1 and
D2 connected to 50-Ω pullup resistors
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kHz
Ω
ns
ns
350
VCC1 = 5 V ± 10%, See Figure 28, D1 and D2
connected to 50-Ω pullup resistors
UNIT
kHz
38
ns
140
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6.11 Switching Characteristics: RS-485 Driver
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
See Figure 17
VCC1 = 5V ± 10%,
VCC2 = 5V ± 5%
23
35
ns
2
5
ns
25
40
ns
2
5
ns
tPLH, tPHL
Prop delay time
tsk(p)
Pulse skew (|tPHL – tPLH|)
tPLH, tPHL
Prop delay time
tsk(p)
Pulse skew (|tPHL – tPLH|)
See Figure 17
VCC1 = 3.3V ± 10%,
VCC2 = 5V ± 5%
tr
Differential output signal rise time
See Figure 17
2
3
7.5
ns
tf
Differential output signal fall time
See Figure 17
2
3
7.5
ns
tpDE
DE to ISODE prop delay
See Figure 21
30
ns
tt(MLH) , tt(MHL)
Output transition skew
See Figure 18
1
ns
tp(AZH), tp(BZH),
tp(AZL), tp(BZL)
Propagation delay, high-impedance-to-active
output
80
ns
tp(AHZ), tp(BHZ),
tp(ALZ), tp(BLZ)
Propagation delay, active-to-high-impedance
output
80
ns
| tp(AZL) – tp(BZH) |
| tp(AZH) – tp(BZL) |
Enable skew time
1.5
ns
t(CFB)
Time from application of short-circuit to
current fold back
See Figure 16
t(TSD)
Time from application of short-circuit to
thermal shutdown
See Figure 16, TA = 25°C
See Figure 19 and Figure 20,
CL = 50pf, RE at 0 V
0.55
0.5
µs
100
µs
6.12 Switching Characteristics: Receiver
over recommended operating conditions (unless otherwise noted)
PARAMETER
TYP
MAX
See Figure 23
VCC1 = 5 V ± 10%,
VCC2 = 5 V ± 5%
TEST CONDITIONS
50
65
ns
2
5
ns
See Figure 23
VCC1 = 3.3 V ± 10%,
VCC2 = 5 V ± 5%
53
70
ns
2
5
ns
Output signal rise time
2
4
ns
Output signal fall time
2
4
ns
13
25
ns
13
25
ns
13
25
ns
13
25
ns
tPLH, tPHL
Propagation delay time
tsk(p)
Pulse skew (|tPHL – tPLH|)
tPLH, tPHL
Propagation delay time
tsk(p)
Pulse skew (|tpHL - tpLH|)
tr
tf
tPZH
Propagation delay, high-impedance-to-highlevel output
tPHZ
Propagation delay, high-level-to-highimpedance output
tPZL
Propagation delay, high-impedance-to-lowlevel output
tPLZ
Propagation delay, low-level-to-highimpedance output
MIN
UNIT
DE at VCC1, See Figure 24
DE at VCC1, See Figure 25
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6.13 Typical Characteristics
90
35
No Load
TA = 25°C
30
ICC2 @ 5 V
80
RL = 54 W,
CL = 50 pF,
TA = 25°C
ICC - Supply Current - mA
ICC - Supply Current - mA
70
25
ICC2 @ 5 V
20
15
ICC1 @ 5 V
ICC1 @ 3.3 V
10
5
40
30
20
0
0
5
10
15
20
25
Data Rate - Mbps
30
35
40
Figure 1. RMS Supply Current (ICC1 and ICC2) vs Signaling
Rate With No Load
5
4
15
20
25
Data Rate - Mbps
30
35
40
15 pF Load
TA = 25°C
-89
-79
50 Ω
3
VCC2 = 4.75 V
2.5
2
1.5
-69
-59
-49
-39
-29
-19
1
0.5
-9
TA = 25 C
0
20
40
60
IL − Load Current − mA
1
0
80
1
2
3
4
5
VO - Output Voltage - V
Figure 3. Differential Output Voltage vs Load Current
Figure 4. Receiver High-Level Output Voltage Vs High-Level
Output Current
0.7
110
15 pF Load
TA = 25°C
100
VCC = 4.75 V
0.6
Driver Enable Skew − ns
90
80
70
60
50
40
30
20
0.5
VCC = 5.25 V
0.4
VCC = 5 V
0.3
0.2
0.1
10
0
10
100 Ω
IO - Output Current - mA
VCC2 = 5.25 V
3.5
0
0
-99
VCC2 = 5 V
4.5
0
1
2
3
VO - Output Voltage - V
4
0
−40
5
Figure 5. Receiver Low-Level Output Voltage vs Low-Level
Output Current
10
ICC1 @ 3.3 V
ICC1 @ 5 V
Figure 2. RMS Supply Current (ICC1 and ICC2) vs Signaling
Rate With Load
5
VOD − Differential Output Voltage − V
50
10
0
IO - Output Current - mA
60
RL = 110 Ω,
CL = 50 pF
−15
10
35
60
TA − Free-Air Temperature − °C
85
Figure 6. Driver Enable Skew vs Free-Air Temperature
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Typical Characteristics (continued)
58
28
56
26
Receiver Propagation Delay - ns
Driver Propagation Delay - ns
tPHL (VCC1 = 3.3 V)
tPLH (VCC1 = 3.3 V)
24
22
tPHL (VCC1 = 5 V)
20
tPHL (VCC1 = 5 V)
54
CL = 15 pH,
VCC2 = 5 V
tPHL (VCC1 = 3.3 V)
tPLH (VCC1 = 3.3 V)
52
50
48
tPHL (VCC1 = 5 V)
46
tPLH (VCC1 = 5 V)
44
18
-40
-15
10
35
60
TA - Free-Air Temperature - °C
42
-40
85
Figure 7. Driver Propagation Delay vs Free-Air Temperature
-15
10
35
60
TA - Free-Air Temperature - °C
85
Figure 8. Receiver Propagation Delay vs Free-Air
Temperature
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7 Parameter Measurement Information
VCC1
VCC1
IOA
DE
IOA
DE
A
A
II
0 or
VCC1
B
GND1
II
0 or
VCC1
VOD
D
IOB
GND2
B
GND2
GND1
VI
54 W
VOD
D
IOB
VI
VOA
VOB
GND1
VOB
GND2
GND 1
VOA
GND2
Figure 9. Open Circuit Voltage Test Circuit
Figure 10. VOD Test Circuit
VCC2
VCC1
IOA
RL
2
DE
DE
375 W
A
D
0 or 3 V
.
B
+
VOD
-
A
II
0 or
VCC1
60 W
VOD
D
- 7 V to12 V
B
GND1
RL
2
IOB
VI
375 W
GND2
GND2
VOB
GND1
Figure 11. Driver VOD with Common-mode
Loading Test Circuit
VOC
VOA
GND2
Figure 12. Driver VOD and VOC Without CommonMode Loading Test Circuit
VCC1
IOA
DE
RL
2
A
Input
Input
Generator : PRR = 500 kHz , 50 % duty
VI
cycle, t r < 6 ns , t f < 6 ns , ZO = 50 W
II
D
GND1
VOD
B
VOB
GND1
RL
2
IOB
GND2
VOA
A
VA
B
VB
VOC
VOC(p-p)
VOC
VOC (SS )
GND2
Figure 13. Steady-State Output Voltage Test Circuit and Voltage Waveforms
VOD(RING )
VOD (SS )
VOD ( pp)
0V differential
Figure 14. VOD(RING) Waveform and Definitions
12
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VCC1
IOA
DE
A
0 or
VCC1
II
VI
V OD
B
D
IOB
GND 2
GND 1
V OA
V OB
GND 1
54 W
GND 2
Figure 15. Input Voltage Hysteresis Test Circuit
DE
250
Output Current - mA
IOS
A
D
IOS
B
+
V_
OS
GND1
GND2
135
60
t(CFB)
time
t(TSD)
Figure 16. Driver Short-Circuit Test Circuit and Waveforms (Short Circuit applied at Time t=0)
3V
DE
VCC1
A
D
Input
Generator
B
VI
VOD
R L = 54 W
±1 %
VI
C L = 50 pF
± 20%
VOD
C L includes fixture and
instrumentation capacitance
GND1
1.5 V
tpHL
tpLH
50 W
Generator: PRR= 500 kHz , 50 % duty
cycle, t r < 6ns , t f < 6 ns ,ZO = 50 W
1.5 V
90%
90%
0V
10 %
VOD(H)
0V
10%
VOD(L)
tf
tr
Figure 17. Driver Switching Test Circuit and Waveforms
DE
VCC1
A
50 %
D
Input
Generator
VI
RL= 54 W CL = 50pF
± 20%
±1%
B
50 W
GND1
Generator : PRR= 500 kHz, 50 % duty
cycle, t r< 6ns , t f <6 ns ,ZO = 50 W
50 %
A
VO B tt(MHL)
GND2 V
OA VOB
tt(MLH)
50 %
50 %
CL includes fixture and
instrumentation capacitance
Figure 18. Driver Output Transition Skew Test Circuit and Waveforms
RL= 110 W
VCC2
A
V IN = 0V
CL = 50 pF
D
B
50 W
GND 1
1.5 V
t(ALZ)
t(AZL)
A
RL= 110 W
DE
Signal
Generator
DE
0V
VOA VOB
CL = 50 pF
50%
t(BZH)
B
VOL+ 0.5V
t(BHZ)
50%
VOH - 0.5 V
GND 2
Figure 19. Driver Enable/Disable Test, D at Logic Low Test Circuit and Waveforms
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RL= 110 W
0V
A
VIN = 3. 0V
CL = 50 pF
t(AHZ)
t(AZH)
B
R = 110 W
DE
Signal
Generator
1.5 V
DE
D
A
VCC2
VOA VOB
50 W
GND 1
VOH -0.5 V
50 %
t(BZL)
C L = 50 pF
t(BLZ)
B
VOL 0.5 V
50 %
GND 2
Figure 20. Driver Enable/Disable Test, D at Logic High Test Circuit and Waveforms
VCC1
GALVANIC ISOLATION
VIN = VCC1
VCC2
D
DE
Signal
Generator
tpDE_HL
tpDE_LH
CL = 15 pF
± 20%
50 %
50 %
ISODE
50 W
GND 1
50 %
50 %
DE
ISODE
GND 2
Figure 21. DE to ISODE Prop Delay Test Circuit and Waveforms
IO
V ID
VO
Figure 22. Receiver DC Parameter Definitions
Signal
Generator
Input B
50 W
PRR=100 kHz, 50% duty cycle,
t r <6ns, t f <6ns, ZO = 50 W
Signal
Generator
A
R
VID
B
C L = 15 pF
(includes probe and
jig capacitance)
50 W
1.5 V
50%
IO
Input A
0V
tpLH
VO
tpHL
V OH
90%
Output
1.5 V
10%
tr
tf
V OL
Figure 23. Receiver Switching Test Circuit and Waveforms
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VCC
D
VCC
DE
A
3V
RE
54 W
1.5 V
1.5 V
B
0V
tpZH
1 kW
R
tpHZ
0V
VOH -0.5 V
C L = 15 pF
Signal
Generator
1.5 V
(includes probe and
jig capacitance)
RE
VO
R
GND
50 W
PRR=100 kHz, 50% duty cycle,
tr<6ns, t f <6ns, ZO = 50 W
Figure 24. Receiver Enable Test Circuit and Waveforms, Data Output High
0V
D
VCC
DE
A
3V
RE
54 W
B
1.5 V
0V
R
tpLZ
tpZL
1 kW
VCC1
VOH
R
1.5 V
C L = 15 pF
VOL +0.5 V
(includes probe and
jig capacitance)
RE
Signal
Generator
1.5 V
VOL
50 W
PRR=100 kHz, 50% duty cycle,
tr<6ns, t f <6ns, Z O = 50 W
Figure 25. Receiver Enable Test Circuit and Waveforms, Data Output Low
A
VINPUT
freq = 1 to 50 MHz
ampl. = ±5 V
100 nF
50 W
470 nF
R
B
RE
50 W
2.2 kW
DE
V
R
Scope
2.2 kW
D
VOFFSET
= -2V to7V
Scope
GND
VCC
100 nF
Figure 26. Common-Mode Rejection Test Circuit
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C = 0.1 mF VCC1
±1%
DE
2.0V
GND 1
VCC2
C = 0.1 mF ±1%
A
D
S1
54 W
B
VOH or VOL
0.8V
R
VOH or VOL
Success / fail criterion :
stabile VOH or V OL outputs.
RE
1 kW
GND1
GND2
CL=15 pF
(includes probe and
jig capacitance)
VTEST
Figure 27. Common-Mode Transient Immunity Test Circuit
tf_D
tr_D
90%
D1
10%
tBBM
tBBM
90 %
D2
10 %
tf_D
tr_D
Figure 28. Transition Times and Break-Before-Make Time Delay for D1, D2 Outputs
16
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8 Detailed Description
8.1 Overview
The ISO1176T is an isolated half-duplex differential line transceiver that meets the requirements of EN 50170
and TIA/EIA 485/422 applications. It has integrated transformer driver for convenient secondary power supply
design. The device is rated to provide galvanic isolation of up to 4242 VPK per VDE and 2500 VRMS per UL 1577.
The device has active-high driver enable and active-low receiver enable functions to control the data flow. It has
maximum data transmission speed of 40 Mbps.
When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this case, the differential output voltage defined
as VOD = V(A) – V(B) is positive. When D is low, the output states reverse, B turns high, A becomes low, and VOD
is negative. When DE is low, both outputs turn high-impedance. In this condition, the logic state at D is irrelevant.
The DE pin has an internal pulldown resistor to ground, thus when left open the driver is disabled (highimpedance) by default. The D pin has an internal pullup resistor to VCC, thus, when left open while the driver is
enabled, output A turns high and B turns low.
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = V(A) – V(B) is positive and higher than the positive input threshold, VIT+, the receiver output, R,
turns high. When VID is negative and lower than the negative input threshold, VIT– , the receiver output, R, turns
low. If VID is between VIT+ and VIT– the output is indeterminate. When RE is logic high or left open, the receiver
output is high-impedance and the magnitude and polarity of VID are irrelevant. Internal biasing of the receiver
inputs causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the
bus lines are shorted (short-circuit), or the bus is not actively driven (idle bus).
8.2 Functional Block Diagram
D2
R
RE
1
2
5
6
8
D
DE
7
OSC
GALVANIC ISOLATIO N
D1
13
B
12
A
10
ISODE
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8.3 Feature Description
8.3.1 Insulation and Safety-Related Specifications for 16-DW Package
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Minimum air gap (Clearance) (1)
Shortest terminal to terminal distance through air
8
mm
L(I02)
Minimum external tracking (Creepage) (1)
Shortest terminal to terminal distance across the
package surface
8
mm
CTI
Comparative Tracking Index (Tracking
resistance)
DIN EN 60112 (VDE 0303-11); IEC 60112
400
DTI
Distance through the insulation
Minimum Internal Gap (Internal Clearance)
0.008
RIO
Isolation resistance
Input to output, VIO = 500 V, all pins on each side
of the barrier tied together creating a two-terminal
device, TA = 25 °C
>1012
Ω
CIO
Barrier capacitance Input to output
VIO = VCC/2 + 0.4 sin (2πft), f = 1MHz, VCC = 5 V
2
pF
CI
Input capacitance to ground
VI = 0.4 sin (2πft), f = 1MHz
2
pF
L(I01)
(1)
V
mm
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to make sure that the mounting pads of the isolator
on the printed circuit board do not reduce this distance. Techniques such as inserting grooves and/or ribs on a printed circuit board are
used to help increase these specifications.
8.3.2 IEC 60664-1 Ratings Table
PARAMETER
TEST CONDITIONS
SPECIFICATION
Material group
II
Overvoltage category / Installation
classification for basic insulation
Rated mains voltage ≤ 150Vrms
I-IV
Rated mains voltage ≤ 300Vrms
I-III
8.3.3 DIN V VDE V 0884-10 Insulation Characteristics (1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
VIORM
TEST CONDITIONS
Maximum working isolation voltage
VPR
Input to output test voltage
SPECIFICATION
UNIT
566
VPK
Method b1, VPR = VIORM × 1.875,
100% Production test with t = 1s,
Partial discharge < 5pC
1062
Method a, After environmental tests subgroup 1,
VPR = VIORM × 1.6, t = 10s, Partial discharge < 5pC
906
After Input/Output Safety Test Subgroup 2/3,
VPR = VIORM x 1.2, t = 10s, Partial discharge < 5pC
680
VPK
VIOTM
Maximum transient isolation voltage
t = 60s (qualification),
t = 1s (100% production)
4242
VPK
VIOSM
Maximum surge isolation voltage
Tested per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.3 x VIOSM = 4000 VPK (Qualification Test)
3077
VPK
RS
Insulation resistance
VIO = 500V at TS = 150°C
> 109
Ω
Pollution degree
(1)
18
2
Climatic Classification 40/125/21
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8.3.4 Regulatory Information
VDE
CSA
UL
Certified according to DIN V VDE V 0884- Approved according to CSA Component
10 (VDE V 0884-10):2006-12
Acceptance Notice 5A, IEC 60950-1 and IEC
61010-1
Approved under UL 1577 Component
Recognition Program
Basic Insulation
Maximum Transient Isolation Voltage,
4242 VPK
Maximum Surge Isolation Voltage, 3077
VPK
Maximum Working Voltage, 566 VPK
3000 VRMS Isolation Rating;
Reinforced insulation per CSA 61010-1-04 and
IEC 61010-1 2nd Ed. 150 VRMS working
voltage;
Basic insulation per CSA 61010-1-04 and IEC
61010-1 2nd Ed. 600 VRMS working voltage;
Basic insulation per CSA 60950-1-07 and IEC
60950-1 2nd Ed. 760 VRMS working voltage
Single Protection, 2500 VRMS (1)
Certificate Number: 40016131
Master Contract Number: 220991
File Number: E181974
(1)
Production tested ≥ 3000 Vrms for 1 second in accordance with UL 1577.
8.3.5 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system
failures.
PARAMETER
TEST CONDITIONS
IS
Safety input, output, or supply
current
DW-16
TS
Maximum safety temperature
DW-16
MIN
θJA = 76°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C
TYP
MAX
UNIT
347
mA
150
°C
The safety-limiting constraint is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Characteristics table is
that of a device installed on a High-K Test Board for Leaded Surface Mount Packages. The power is the
recommended maximum input voltage times the current. The junction temperature is then the ambient
temperature plus the power times the junction-to-air thermal resistance.
400
VCC1 = VCC2 = 5.5 V
Safety Limiting Current - mA
350
300
250
200
150
100
50
0
50
100
Temperature - °C
150
200
Figure 29. Thermal Derating Curve per VDE
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8.4 Device Functional Modes
Table 1 and Table 2 are the function tables for the ISO1176T driver and receiver.
Table 1. Driver Function Table (1)
(1)
VCC1
VCC2
INPUT
(D)
ENABLE INPUT
(DE)
ENABLE
OUTPUT
(ISODE)
OUTPUTS
PU
PU
H
H
H
H
L
PU
PU
L
H
H
L
H
PU
PU
X
L
L
Z
Z
PU
PU
X
open
L
Z
Z
PU
PU
open
H
H
H
L
PD
PU
X
X
L
Z
Z
PU
PD
X
X
L
Z
Z
PD
PD
X
X
L
Z
Z
A
B
PU = Powered Up, PD = Powered Down, H = High Level, L= Low Level, X = Don't Care, Z = High
Impedance (off)
Table 2. Receiver Function Table (1)
(1)
20
VCC1
VCC2
DIFFERENTIAL
INPUT
VID = (VA – VB)
ENABLE (RE)
OUTPUT (R)
PU
PU
–0.01V ≤ VID
L
H
PU
PU
-0.2V < VID <
–0.01V
L
?
PU
PU
VID ≤ –0.2V
L
L
PU
PU
X
H
Z
PU
PU
X
open
Z
PU
PU
Open circuit
L
H
PU
PU
Short Circuit
L
H
PU
PU
Idle (terminated)
bus
L
H
PD
PU
X
X
Z
PU
PD
X
L
H
PD
PD
X
X
Z
PU = Powered Up, PD = Powered Down, H = High Level, L= Low Level, X = Don’t Care, Z = High
Impedance (off), ? = Indeterminate
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8.4.1 Device I/O Schematics
DE Input
D , RE Input
V CC1
V CC1
V CC1
V CC1
V CC1
1 MW
500 W
500 W
1 MW
ISODE Output
3 .3 -V R Output
V CC2
V CC1
5.5 W
4W
11 W
6.4 W
5 -V R Output
V CC1
5.5 W
11 W
Figure 30. Equivalent Circuit Schematics
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A Input
B Input
V CC2
V CC2
16V
90 kW
Input
16V
16V
18 k W
90 kW
Input
18 kW
18 kW
16V
18 kW
A and B Outputs
V CC2
16V
Output
16V
Figure 31. Equivalent Circuit Schematics
22
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO1176T device consists of a RS-485 transceiver, commonly used for asynchronous data transmissions.
For half-duplex transmission, only one pair is shared for both transmission and reception of data. To eliminate
line reflections, each cable end is terminated with a termination resistor, R(T), whose value matches the
characteristic impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data
rates over longer cable length.
R
R
R
R
R
R
RE
A
RE
A
RE
A
DE
B
DE
B
DE
B
D
D
D
a) Independent driver and
receiver enable signals
D
D
b) Combined enable signals for
use as directional control pin
D
c) Receiver always on
Figure 32. Half-Duplex Transceiver Configurations
9.2 Typical Application
X-FMR
4
8
3
2
7
6
1
5
LDO
D1
1
C4 C5
3
2
C1
OUT
IN
5
C6
EN
GND
NC
4
D2
1
2
4
C2
3
5
6
Control
Circuitry
D1
VCC2
16
C3
Isolated Supply to
other Components
D2
VCC1
B
GND1
A
R
ISODE
13
12
10
Profibus
Interface
RE
7
DE
GND2
D
GND2
8
14, 15
9, 11
Figure 33. Typical Application
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Typical Application (continued)
9.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
Table 3. Design Parameters
PARAMETER
VALUE
Pullup and Pulldown Resistors
1 kΩ to 10 kΩ
Decoupling Capacitors
100 nF
9.2.2 Detailed Design Procedure
9.2.2.1 Transient Voltages
Isolation of a circuit insulates it from other circuits and earth so that noise develops across the insulation rather
than circuit components. The most common noise threat to data-line circuits is voltage surges or electrical fast
transients that occur after installation and the transient ratings of ISO1176T are sufficient for all but the most
severe installations. However, some equipment manufacturers use their ESD generators to test transient
susceptibility of their equipment and can exceed insulation ratings. ESD generators simulate static discharges
that may occur during device or equipment handling with low-energy but high voltage transients.
Figure 34 models the ISO1176T bus IO connected to a noise generator. CIN and RIN is the device and any other
stray or added capacitance or resistance across the A or B pin to GND2, CISO and RISO is the capacitance and
resistance between GND1 and GND2 of ISO1176T plus those of any other insulation (transformer, or similar),
and we assume stray inductance negligible. From this model, the voltage at the isolated bus return is shown in
Equation 1:
Z ISO
vGND2 = vN
ZISO + ZIN
(1)
and will always be less than 16 V from VN. If ISO1176T is tested as a stand-alone device, RIN = 6 × 104Ω, CIN =
16 × 10-12 F, RISO = 109Ω and CISO = 10-12 F.
SPACER
Note from Figure 34 that the resistor ratio determines the voltage ratio at low frequency and it is the inverse
capacitance ratio at high frequency. In the stand-alone case and for low frequency, as shown in Equation 2,
vGND2
RISO
109
=
=
vN
RISO + RIN
109 + 6 ´ 104
(2)
or essentially all of noise appears across the barrier. At high frequency, as shown in Equation 3,
1
v GND2
CISO
1
1
=
=
=
= 0.94
1
1
1
CISO
vN
+
1+
1+
16
CISO
CIN
CIN
(3)
and 94% of VN appears across the barrier. As long as RISO is greater than RIN and CISO is less than CIN, most of
transient noise appears across the isolation barrier, as it should.
We recommend the reader not test equipment transient susceptibility with ESD generators or consider product
claims of ESD ratings above the barrier transient ratings of an isolated interface. ESD is best managed through
recessing or covering connector pins in a conductive connector shell and installer training.
24
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ISO1176T
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SLLSE28G – OCTOBER 2010 – REVISED OCTOBER 2015
A,B, Y, or Z
C IN
R IN
VN
16 V
Bus Return(GND2)
C ISO
R ISO
System Ground (GND1)
Figure 34. Noise Model
9.2.3 Application Curve
At maximum working voltage, ISO1176T isolation barrier has more than 28 years of life.
WORKING LIFE -- YEARS
100
VIORM at 566 VPK
28
10
0
120
250
500
750
880
1000
WORKING VOLTAGE (V IORM ) -- VPK
Figure 35. Time-Dependent Dielectric Breakdown Test Results
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10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, TI recommends a 0.1-µF bypass capacitor at
input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. This device is used in applications where only a single primary-side power supply is available. Isolated
power can be generated for the secondary-side with the help of integrated transformer driver.
11 Layout
11.1 Layout Guidelines
ON-chip IEC-ESD protection is good for laboratory and portable equipment but never sufficient for EFT and
surge transients occurring in industrial environments. Therefore, robust and reliable bus node design requires the
use of external transient protection devices. Because ESD and EFT transients have a wide frequency bandwidth
from approximately 3-MHz to 3-GHz, high-frequency layout techniques must be applied during PCB design. A
minimum of four layers is required to accomplish a low EMI PCB design (see Figure 36).
• Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power
plane, and low-frequency signal layer.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
• Place the protection circuitry close to the bus connector to prevent noise transients from penetrating your
board.
• Use VCC and ground planes to provide low-inductance. High-frequency currents might follow the path of least
inductance and not necessarily the path of least resistance.
• Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
• Apply 0.1-µF bypass capacitors as close as possible to the VCC-pins of transceiver, UART, and controller ICs
on the board.
• Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to
minimize effective via-inductance.
• Use 1-kΩ to 10-kΩ pullup and pulldown resistors for enable lines to limit noise currents in these lines during
transient events.
• Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified
maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the
transceiver and prevent it from latching up.
• While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
If an additional supply voltage plane or signal layer is needed, add a second power and ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
NOTE
For detailed layout recommendations, see Application Note Digital Isolator Design Guide,
SLLA284.
26
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11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 36. Recommended Layer Stack
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SLLSE28G – OCTOBER 2010 – REVISED OCTOBER 2015
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Isolated, 40-Mbps, 3.3-V to 5-V Profibus Interface (SLUU471)
• Digital Isolator Design Guide (SLLA284)
• Isolation Glossary (SLLA353)
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
Profibus is a registered trademark of Profibus International.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Mar-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO1176TDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ISO1176T
ISO1176TDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ISO1176T
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
26-Mar-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ISO1176TDWR
Package Package Pins
Type Drawing
SOIC
DW
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
10.75
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.7
2.7
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO1176TDWR
SOIC
DW
16
2000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DW 16
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
B
7.6
7.4
NOTE 4
2.65 MAX
B
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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