Texas Instruments | ISO7420FCC Low-Power Dual Channel Digital Isolator (Rev. C) | Datasheet | Texas Instruments ISO7420FCC Low-Power Dual Channel Digital Isolator (Rev. C) Datasheet

Texas Instruments ISO7420FCC Low-Power Dual Channel Digital Isolator (Rev. C) Datasheet
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ISO7420FCC
SLLSED3C – JUNE 2013 – REVISED JULY 2015
ISO7420FCC Low-Power Dual Channel Digital Isolator
1 Features
3 Description
•
•
•
•
ISO7420FCC provides galvanic isolation up to 2500
VRMS for 1 minute per UL and 4242 VPK per VDE.
This device has two isolated channels. Each channel
has a logic input and output buffer separated by a
silicon dioxide (SiO2) insulation barrier. Used in
conjunction with isolated power supplies, this device
prevents noise currents on a data bus or other circuit
from entering the local ground and interfering with or
damaging sensitive circuitry. The suffix F indicates
low-output option in fail-safe conditions (see Table 2).
This device has integrated noise filter for harsh
environments where short noise pulses may be
present at the device input pins.
1
•
•
•
•
•
•
•
•
•
•
Signaling Rate: 50 Mbps (5-V Supplies)
Output is Low in Default Mode
Integrated Noise Filter on the Input Pins
Low Power Consumption: Typical ICC per Channel
– 1.8 mA at 1 Mbps, 3.9 mA at 25 Mbps (5-V
Supplies)
– 1.4 mA at 1 Mbps, 2.6 mA at 25 Mbps (3.3-V
Supplies)
Low Propagation Delay: 20 ns Typical (5-V
Supplies)
Channel-to-Channel Output Skew: 2 ns Maximum
3.3-V and 5-V Level Translation
Wide TA Range Specified: –40°C to 125°C
60-KV/μs Transient Immunity, Typical (5-V
Supplies)
Low Emissions
Isolation Barrier Life: > 25 Years
Operates from 2.7-V to 5.5-V Supply Levels
Narrow Body SOIC-8 Package
Safety and Regulatory Approvals
– 4242 VPK Isolation per DIN V VDE V 0884-10
(VDE V 0884-10):2006-12
– 2.5 KVRMS Isolation for 1 Minute per UL 1577
– CSA Component Acceptance Notice 5A, IEC
60950-1 and IEC 61010-1 End Equipment
Standards
– GB4943.1-2011 CQC Certification
ISO7420FCC has TTL input thresholds and operates
from 2.7-V to 5.5-V supplies. All inputs are 5-V
tolerant when supplied from a 2.7-V or 3.3-V supply.
Device Information(1)
PART NUMBER
ISO7420FCC
PACKAGE
SOIC (8)
BODY SIZE (NOM)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
2 Applications
•
Opto-Coupler Replacement in:
– Industrial FieldBus
– ProfiBus
– ModBus
– DeviceNet™ Data Buses
– Servo Control Interface
– Motor Control
– Power Supplies
– Battery Packs
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
ISO7420FCC
SLLSED3C – JUNE 2013 – REVISED JULY 2015
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
Absolute Maximum Ratings ..................................... 3
ESD Ratings.............................................................. 3
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics: VCC1 and VCC2 = 5 V ±
10% ............................................................................ 5
6.6 Electrical Characteristics: VCC1 and VCC2 = 3.3 V ±
10% ............................................................................ 5
6.7 Electrical Characteristics: VCC1 and VCC2 = 2.7 V .... 6
6.8 Power Dissipation Characteristics ............................ 6
6.9 Switching Characteristics: VCC1 and VCC2 = 5 V ±
10% ............................................................................ 7
6.10 Switching Characteristics: VCC1 and VCC2 = 3.3 V ±
10% ............................................................................ 7
6.11 Switching Characteristics: VCC1 and VCC2 = 2.7 V . 7
6.12 Typical Characteristics ............................................ 8
7
8
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
12
15
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application ................................................. 16
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2014) to Revision C
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
VDE standard changed to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 .................................................................... 1
•
Changed VDE standard changed to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 ...................................................... 1
•
Changed Note 1 Figure 12 .................................................................................................................................................. 10
•
Changed Figure 13 .............................................................................................................................................................. 10
Changes from Revision A (July 2013) to Revision B
Page
•
Changed the SAFETY AND REGULATORY APPROVALS list ............................................................................................. 1
•
Changed the VIH MAX value From: VCC To: 5.5V in the RECOMMENDED OPERATING CONDITIONS table ................... 4
•
Changed the VPR and VIOTM parameter From: DIN EN 60747-5-2 To: DIN EN 60747-5-5 in the INSULATION
CHARACTERISTICS table ................................................................................................................................................... 13
•
Changed the REGULATORY INFORMATION table ............................................................................................................ 13
•
Changed the title of Figure 16 From: θJC Thermal Derating Curve per DIN EN 60747-5-2 To: θJC Thermal Derating
Curve per DIN EN 60747-5-5 ............................................................................................................................................... 14
Changes from Original (June 2013) to Revision A
Page
•
Changed High-level output voltage MIN Value From: VCCx To: VCC2 ..................................................................................... 5
•
Changed High-level output voltage MIN Value From: VCCx To: VCC2 and removed Note 1 ................................................... 5
•
Changed High-level output voltage MIN Value From: VCCx To: VCC2 and removed Note 1 ................................................... 6
•
Changed Figure 3 X axis values ............................................................................................................................................ 8
2
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5 Pin Configuration and Functions
ISO7420: D Package
8-Pin SOIC
Top View
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
GND1
4
–
Ground connection for VCC1
GND2
5
–
Ground connection for VCC2
INA
2
I
Input, channel A
INB
3
I
Input, channel B
OUTA
7
O
Output, channel A
OUTB
6
O
Output, channel B
VCC1
1
–
Power supply, VCC1
VCC2
8
–
Power supply, VCC2
6 Specifications
6.1 Absolute Maximum Ratings
see
(1)
VCC1, VCC2
Supply voltage (2)
MIN
MAX
–0.5
6
VIO
Voltage at INx, OUTx
–0.5
IO
Output current
–15
TJ(Max)
Maximum junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
–65
VCC + 0.5
UNIT
V
(3)
V
15
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values.
Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
MIN
VCC1, VCC2
IOH
NOM
MAX
5.5
UNIT
Supply voltage
2.7
High-level output current (VCC ≥ 3 V)
–4
mA
High-level output current (VCC < 3 V)
-2
mA
IOL
Low-level output current
VIH
High-level input voltage
2
5.5
V
VIL
Low-level input voltage
0
0.8
V
tui
Input pulse duration
1 / tui
Signaling rate
TJ
(1)
TA
(1)
4
V
≥ 4.5-V Operation
20
< 4.5-V Operation
25
≥ 4.5-V Operation
0
< 4.5-V Operation
mA
ns
50
Mbps
0
40
Junction temperature
–40
136
°C
Ambient temperature
-40
125
°C
25
To maintain the recommended operating conditions for TJ, see the Power Dissipation Characteristics table.
6.4 Thermal Information
ISO7420FCC
THERMAL METRIC
(1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
115.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
60.1
°C/W
RθJB
Junction-to-board thermal resistance
56.4
°C/W
ψJT
Junction-to-top characterization parameter
17.2
°C/W
ψJB
Junction-to-board characterization parameter
55.8
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics: VCC1 and VCC2 = 5 V ± 10%
TA = –40°C to 125°C
PARAMETER
MIN
TYP
IOH = –4 mA; see Figure 12.
TEST CONDITIONS
VCC2 – 0.5
4.8
IOH = –20 μA; see Figure 12.
VCC2 – 0.1
5
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
INx = VCC1
IIL
Low-level input current
INx = 0 V
CMTI
Common-mode transient immunity
VI = VCC1 or 0 V; see Figure 14.
MAX
UNIT
V
IOL = 4 mA; see Figure 12.
0.2
0.4
IOL = 20 μA; see Figure 12.
0
0.1
V
450
mV
μA
10
μA
–10
25
60
kV/μs
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC I CC MEASUREMENT)
ICC1
DC to 1 Mbps
ICC2
ICC1
ICC2
ICC1
DC Input: VI = VCC1 or 0 V,
AC Input: CL = 15pF
10 Mbps
Supply current for VCC1 and VCC2
25 Mbps
ICC2
ICC1
CL = 15pF
50 Mbps
ICC2
0.5
1.1
3
4.6
1
1.5
4
6
1.7
2.5
6
8.5
2.7
4
8.5
12
mA
6.6 Electrical Characteristics: VCC1 and VCC2 = 3.3 V ± 10%
TA = –40°C to 125°C
PARAMETER
MIN
TYP
IOH = –4 mA; see Figure 12.
TEST CONDITIONS
VCC2 – 0.5
3
IOH = –20 μA; see Figure 12.
VCC2 – 0.1
3.3
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
INx = VCC1
IIL
Low-level input curre
INx = 0 V
CMTI
Common-mode transient immunity
VI = VCC1 or 0 V; see Figure 14.
MAX
V
IOL = 4 mA; see Figure 12.
0.2
0.4
IOL = 20 μA; see Figure 12.
0
0.1
425
V
mV
10
μA
μA
-10
25
UNIT
40
kV/μs
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC I CC MEASUREMENT)
ICC1
DC to 1 Mbps
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
DC Input: VI = VCC1 or 0 V,
AC Input: CL = 15pF
10 Mbps
Supply current for VCC1 and VCC2
25 Mbps
CL = 15pF
40 Mbps
0.3
0.8
2.4
3.3
0.6
1.2
3.1
4.5
1
2
4.2
6.1
1.3
2.3
5.3
7.5
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6.7 Electrical Characteristics: VCC1 and VCC2 = 2.7 V
TA = –40°C to 125°C
PARAMETER
MIN
TYP
IOH = –2 mA; see Figure 12.
TEST CONDITIONS
VCC2 – 0.3
2.5
IOH = –20 μA; see Figure 12.
VCC2 – 0.1
2.7
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
INx = VCC1
IIL
Low-level input current
INx = 0 V
CMTI
Common-mode transient immunity
VI = VCC1 or 0 V; see Figure 14.
MAX
UNIT
V
IOL = 4 mA; see Figure 12.
0.2
0.4
IOL = 20 μA; see Figure 12.
0
0.1
350
V
mV
10
μA
μA
–10
25
35
kV/μs
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC I CC MEASUREMENT)
ICC1
DC to 1 Mbps
ICC2
ICC1
DC Input: VI = VCC1 or 0 V,
AC Input: CL = 15pF
10 Mbps
ICC2
Supply current for VCC1 and VCC2
ICC1
25 Mbps
ICC2
ICC1
CL = 15pF
40 Mbps
ICC2
0.15
0.4
2.1
3.1
0.4
0.7
2.7
4
0.7
1.2
3.6
5
1
1.7
4.4
6.3
mA
6.8 Power Dissipation Characteristics
ISO7420FCC
THERMAL METRIC
D (SOIC)
UNIT
8 PINS
PD
6
Device power dissipation
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 50-Mbps 50% duty-cycle square wave
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120
mW
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6.9 Switching Characteristics: VCC1 and VCC2 = 5 V ± 10%
TA = –40°C to 125°C
PARAMETER
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse width distortion |tPHL – tPLH|
(2)
tsk(o)
tsk(pp)
TEST CONDITIONS
See Figure 12.
(3)
MAX
20
37
ns
2.5
5
ns
2
ns
12
ns
Part-to-part skew time
Output signal rise time
tf
Output signal fall time
tGS
Pulse width of glitches suppressed by the input filter
tfs
Fail-safe output delay time from input data or power loss
(3)
TYP
10
Channel-to-channel output skew time
tr
(1)
(2)
MIN
See Figure 12.
See Figure 13.
UNIT
2.5
ns
2.5
ns
12
ns
8
μs
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.10 Switching Characteristics: VCC1 and VCC2 = 3.3 V ± 10%
over operating free-air temperature range (unless otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse width distortion |tPHL – tPLH|
(2)
tsk(o)
tsk(pp)
(3)
TEST CONDITIONS
See Figure 12.
MAX
22
40
ns
3
ns
2
ns
19
ns
Part-to-part skew time
Output signal rise time
tf
Output signal fall time
tGS
Pulse width of glithes suppressed by the input filter
tfs
Fail-safe output delay time from input power loss
(3)
TYP
10
Channel-to-channel output skew time
tr
(1)
(2)
MIN
See Figure 12.
See Figure 13.
UNIT
3
ns
3
ns
12.5
ns
8
μs
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.11 Switching Characteristics: VCC1 and VCC2 = 2.7 V
TA = –40°C to 125°C
PARAMETER
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse width distortion |tPHL – tPLH|
tsk(o)
(2)
tsk(pp)
(3)
TEST CONDITIONS
See Figure 12.
MAX
26
45
ns
3
ns
2
ns
22
ns
Part-to-part skew time
Output signal rise time
tf
Output signal fall time
tGS
Pulse width of glitches suppressed by the input filter
tfs
Fail-safe output delay time from input power loss
(3)
TYP
15
Channel-to-channel output skew time
tr
(1)
(2)
MIN
See Figure 12.
See Figure 13.
UNIT
3
ns
3
ns
13.5
ns
8
μs
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.12 Typical Characteristics
5
ICC1
3.3VV
ICC1 atat3.3
ICC2
3.3VV
ICC2 atat3.3
ICC1 atat5 5VV
ICC1
ICC2 atat5 5VV
ICC2
Supply Current (mA)
4
3.5
10
TA = 25 °C
CL = 15 pF
ICC1
3.3VV
ICC1 atat3.3
ICC2
3.3VV
ICC2 atat3.3
ICC1 atat5 5VV
ICC1
ICC2 atat5 5VV
ICC2
8
Supply Current (mA)
4.5
3
2.5
2
1.5
TA = 25 °C
CL = 15 pF
6
4
1
2
0.5
0
0
0
10
20
30
40
0
50
Data Rate (Mbps)
10
20
30
Figure 1. Supply Current Per Channel vs Data Rate
1
Low-Level Output Voltage (V)
High-Level Output Voltage (V)
3
2
VCC
3.3VV
VCC atat3.3
1
0
0.4
0.2
0
0
–5
5
10
15
Low-Level Output Current (mA)
C003
Figure 3. High-Level Output Voltage vs High-Level Output
Current
C004
Figure 4. Low-Level Output Voltage vs Low-Level Output
Current
2.5
27
VCC
Rising
V
CC Rising
2.48
VCC
Falling
V
CC Falling
Propagation Delay Time (ns)
Power Supply Under Voltage Threshold (V)
0.6
0
–10
High-Level Output Current (mA)
2.46
2.44
2.42
2.4
2.38
2.36
2.34
25
23
21
19
17
ttpLH
3.3
3.3VV
pLH atat
ttpHL
3.3
3.3VV
pHL atat
ttpLH
5 5VV
pLH atat
ttpHL
5 5VV
pHL atat
15
13
±50
0
50
100
Free-Air Temperature (ƒC)
150
±40
±5
30
65
Free-Air Temperature (ƒC)
C005
Figure 5. VCC1 and VCC2 Undervoltage Threshold vs Free-Air
Temperature
8
V
VCC
CC atat55VV
0.8
VCC atat55VV
VCC
TA = 25 °C
–15
C002
TA = 25 °C
VCC
3.3VV
V
CC atat3.3
4
50
Figure 2. Supply Current for Both Channels vs Data Rate
6
5
40
Data Rate (Mbps)
C001
100
135
C006
Figure 6. Propagation Delay Time vs Free-Air Temperature
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Typical Characteristics (continued)
18
Input Glitch Rejection Time (ns)
1.2
Pk-Pk Output Jitter (ns)
1
0.8
0.6
0.4
0.2
Output Jitter at 3.3 V
Output Jitter at 5 V
TA = 25 °C
0
0
20
40
14
12
10
8
6
4
2.7VV
ttGR
GS atat2.7
ttGR
3.3VV
GS atat3.3
ttGR
GS atat5 5VV
2
0
60
Data Rate (Mbps)
16
±40
±15
10
35
60
85
110
135
Free-Air Temperature (ƒC)
C007
C008
Figure 7. Output Jitter vs Data Rate
Figure 8. Input Glitch Suppression Time vs Free-Air
Temperature
Figure 9. Eye Diagram at 50 Mbps, 5V at 25°C
Figure 10. Eye Diagram at 40 Mbps, 3.3V at 25°C
Figure 11. Eye Diagram at 40 Mbps, 2.7V at 25°C
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Isolation Barrier
7 Parameter Measurement Information
IN
Input
Generator
(1)
VI
50 W
VCC1
VI
OUT
VO
1.4 V
1.4 V
0V
CL
tPLH
(2)
tPHL
90%
10%
VCC/2
VO
VCC/2
VOH
VOL
tr
tf
S0412-01
(1)
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate the Input Generator signal. It is not
needed in actual application.
(2)
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 12. Switching Characteristic Test Circuit and Voltage Waveforms
VI
VCC
ISOLATION BARRIER
VCC
IN = VCC
A.
2.7 V
VI
0V
OUT
t fs
VO
CL
NOTE A
VOH
50%
VO
fs low V
OL
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 13. Fail-Safe Output Delay-Time Test Circuit and Voltage Waveforms
S1
C = 0.1 μ F ±1%
Isolation Barrier
VCC1
IN
GND1
VCC2
C = 0.1 μ F ±1%
Pass-fail criteria –
output must remain
stable.
OUT
+
(1)
CL
GND2
VOH or VOL
–
+ VCM –
(1)
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 14. Common-Mode Transient Immunity Test Circuit
10
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8 Detailed Description
8.1 Overview
The isolator in Figure 15 is based on a capacitive isolation barrier technique. The I/O channel of the device
consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to
50 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a singleended input signal entering the HF-channel is split into a differential signal via the inverter gate at the input. The
following capacitor-resistor networks differentiate the signal into transients, which then are converted into
differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output feeds an
output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between
signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case
of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high- to the low-frequency
channel.
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these
signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a
sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-pass
filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output
multiplexer.
8.2 Functional Block Diagram
Figure 15. Conceptual Block Diagram of a Digital Capacitive Isolator
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8.3 Feature Description
8.3.1 Insulation and Safety-Related Specifications for SOIC-8 Package
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
L(I01)
Minimum air gap (clearance)
Shortest terminal-to-terminal distance through air
4
mm
L(I02)
Minimum external tracking
(creepage)
Shortest terminal-to-terminal distance across the
package surface
4
mm
CTI
Tracking resistance (comparative
tracking index)
DIN EN 60112 (VDE 0303-11); IEC 60112
>400
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
0.014
V
mm
VIO = 500 V, TA = 25°C
12
>10
Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C
>1011
Ω
RIO
Isolation resistance, input to
output (1)
CIO
Barrier capacitance, input to
output (1)
VIO = 0.4 sin (2πft), f = 1 MHz
1
pF
CI
Input capacitance (2)
VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V
1
pF
(1)
(2)
All pins on each side of the barrier tied together creating a two-terminal device.
Measured from input pin to ground.
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance.
Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to
help increase these specifications.
12
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8.3.2 Insulation Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SPECIFICATION
UNIT
566
VPK
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 (1)
VIORM
VPR
Maximum working isolation voltage
Input-to-output test voltage
Method a, After environmental tests subgroup 1,
VPR = VIORM x 1.6, t = 10 s,
Partial Discharge < 5 pC
906
Method b1,
VPR = VIORM x 1.875, t = 1 s (100% Production test)
Partial discharge < 5 pC
1062
After Input/Output safety test subgroup 2/3,
VPR = VIORM x 1.2, t = 10 s,
Partial discharge < 5 pC
680
VPK
VIOTM
Maximum transient isolation voltage
VTEST = VIOTM
t = 60 sec (qualification)
t= 1 sec (100% production)
4242
VPK
RS
Isolation resistance
VIO = 500 V at TS = 150°C
>109
Ω
Pollution degree
2
UL 1577
VISO
(1)
VTEST = VISO = 2500 VRMS, t = 60 sec (qualification)
VTEST = 1.2 x VISO= 3000 VRMS, t = 1 sec (100%
production)
Isolation voltage
2500
VRMS
Climatic Classification 40/125/21
Table 1. IEC 60664-1 Ratings Table
PARAMETER
TEST CONDITIONS
SPECIFICATION
Material group
II
Installation classification
Rated mains voltage ≤ 150 VRMS
I–IV
Rated mains voltage ≤ 300 VRMS
I–III
8.3.3 Regulatory Information
VDE
CSA
UL
CQC
Certified according to DIN V VDE
Approved under CSA Component Recognized under UL 1577
V 0884-10 (VDE V 0884Acceptance Notice 5A, IEC 60950- Component Recognition
Certified according to GB4943.1-2011
10):2006-12 and DIN EN 610101, and IEC 61010-1
Program
1 (VDE 0411-1):2011-07
Basic Insulation
Maximum Transient Isolation
voltage, 4242 VPK;
Maximum Working Isolation
Voltage, 566 VPK
3000 VRMS Isolation Rating;
400 VRMS Basic and 200 VRMS
Reinforced Insulation maximum
working voltage per CSA 60950-107+A1 and IEC 60950-1 (2nd
Ed)+A1;
300 VRMS Basic and 150 VRMS
Reinforced Insulation maximum
working voltage per CSA 61010-112 and IEC 61010-1 (3rd Ed)
Single Protection, 2500
VRMS (1)
Basic Insulation, Altitude ≤ 5000m,
Tropical Climate, 250 VRMS maximum
working voltage
Certificate number: 40016131
Master contract number: 220991
File number: E181974
Certificate number:
CQC14001109540
(1)
Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
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8.3.4 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
IS
TS
TEST CONDITIONS
Safety input, output, or supply
current
MIN
TYP
MAX
θJA = 115.1°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
197
θJA = 115.1°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
302
θJA = 115.1°C/W, VI = 2.7 V, TJ = 150°C, TA = 25°C
402
Maximum Safety temperature
150
UNIT
mA
°C
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum
Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface-Mount
Packages. The power is the recommended maximum input voltage times the current. The junction temperature is
then the ambient temperature plus the power times the junction-to-air thermal resistance.
450
Safety Limiting Current (mA)
400
VCC1 = VCC2 = 2.7 V
350
300
VCC1 = VCC2 = 3.6 V
250
200
VCC1 = VCC2 = 5.5 V
150
100
50
0
0
50
100
150
Case Temparature (ƒC)
200
C000
Figure 16. θJC Thermal Derating Curve per VDE
14
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8.4 Device Functional Modes
Table 2. Function Table (1)
VCC1
VCC2
PU
(1)
(2)
INPUT
INA, INB
OUTPUT
OUTA, OUTB
H
H
PU
L
L
Open
L (2)
PD
PU
X
L (2)
X
PD
X
Undetermined
PU = Powered up (VCC ≥ 2.7 V); PD = Powered down (VCC ≤ 2.1 V);
X = Irrelevant; H = High level; L = Low level
In fail-safe condition, output defaults to low level
8.4.1 Device I/O Schematics
Output
Input
VCC2
VCC1
VCC1
8Ω
500 Ω
OUT
IN
13 Ω
7.5 uA
Figure 17. Device I/O Schematics
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
ISO7420FCC utilize single-ended TTL-logic switching technology. Its supply voltage range is from 2.7 V to 5.5 V
for both supplies, VCC1 and VCC2. When designing with digital isolators, it is important to keep in mind that due to
the single-ended design structure, digital isolators do not conform to any specific interface standard and are only
intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the
data controller (i.e. μC or UART), and a data converter or a line transceiver, regardless of the interface type or
standard.
9.2 Typical Application
ISO7420FCC can be used to isolate power MOSFETs from sensitive logic circuitry in Switch Mode Power
Supplies (SMPS) as shown in Figure 18. Low default output of ISO7420FCC is critical for proper operation of
power MOSFETs in such applications.
MOSFET A
MOSFET B
PWM
ISO7420FCC
UCC27423
Figure 18. Isolated Switch Mode Power Supply
9.2.1 Design Requirements
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO7420FCC only requires two external bypass capacitors to operate.
9.2.2 Detailed Design Procedure
9.2.2.1 Supply Current Equations
9.2.2.1.1 Maximum Supply Current Equations
(Calculated over recommended operating temperature range and Silicon process variation).
At VCC1 = VCC2 = 5 V ±10%:
ICC1(max) = 1.1 + 5.80E-02 × f
ICC2(max) = 4.6 + 6.55E-02 × f + 5.5E-03 × f × CL
(1)
(2)
At VCC1 = VCC2 = 3.3 V ± 10%:
ICC1(max) = 0.8 + 3.40E-02 × f
ICC2(max) = 3.3 + 4.60E-02 × f + 3.6E-03 × f × CL
(3)
(4)
At VCC1 = VCC2 = 2.7 V:
ICC1(max) = 0.4 + 3.20E-02 × f
ICC2(max) = 3.1 + 3.75E-02 × f + 2.7E-03 × f × CL
16
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(6)
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Typical Application (continued)
f is data rate of each channel measured in Mbps; CL is the capacitive load of each channel measured in pF;
ICC1(maximum) and ICC2(max) are measured in mA.
9.2.2.1.2 Typical Supply Current Equations
(Calculated for TA = 25°C and nominal Silicon process material).
At VCC1 = VCC2 = 5 V:
ICC1(typical) = 0.5 + 4.40E-02 × f
ICC2(typical) = 3 + 3.50E-02 × f + 5.0E-03 × f × CL
(7)
(8)
At VCC1 = VCC2 = 3.3 V:
ICC1(typical) = 0.3 + 2.60E-02 × f
ICC2(typical) = 2.4 + 2.25E-02 × f + 3.3E-03 × f × CL
(9)
(10)
At VCC1 = VCC2 = 2.7 V:
ICC1(typical) = 0.15 + 2.10E-02 × f
ICC2(typical) = 2.1 + 1.75E-02 × f + 2.7E-03 × f × CL
(11)
(12)
f is Data Rate of each channel measured in Mbps; CL is the Capacitive Load of each channel measured in pF;
ICC1(typ) and ICC2(typ) are measured in mA.
ISO7420FCC
VCC1
8
1
VCC2
0.1 µF
0.1 µF
INA
2
7
OUTA
INB
3
6
OUTB
GND1
4
5
GND2
Figure 19. ISO7420FCC Typical Circuit Hook-Up
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Typical Application (continued)
9.2.3 Application Curves
Figure 20 shows the INA input on Channel 1 and OUTA output on Channel 2 of an oscilloscope.
Figure 20. Typical Input and Output Waveforms
18
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10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, a 0.1 µF bypass capacitor is recommended at
input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501. For
such applications, detailed power supply design and transformer selection recommendations are available in
SN6501 datasheet (SLLSEA0).
11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 21). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the
stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see Application Note Digital Isolator Design Guide, SLLA284.
11.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the
requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower
dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its selfextinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces , pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 21. Recommended Layer Stack
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• SN6501 Transformer Driver for Isolated Power Supplies (SLLSEA0)
• LVDS Application and Data Handbook (SLLD009)
• Digital Isolator Design Guide (SLLA284)
• Isolation Glossary (SLLA353)
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
DeviceNet, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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24-Mar-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO7420FCCD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7420FC
ISO7420FCCDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7420FC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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24-Mar-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ISO7420FCCDR
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO7420FCCDR
SOIC
D
8
2500
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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