Texas Instruments | ISO742x Low-Power Dual Channel Digital Isolators (Rev. F) | Datasheet | Texas Instruments ISO742x Low-Power Dual Channel Digital Isolators (Rev. F) Datasheet

Texas Instruments ISO742x Low-Power Dual Channel Digital Isolators (Rev. F) Datasheet
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ISO7420E, ISO7420FE, ISO7421E, ISO7421FE
SLLSE45F – DECEMBER 2010 – REVISED JULY 2015
ISO742x Low-Power Dual Channel Digital Isolators
1 Features
3 Description
•
•
•
ISO742x provide galvanic isolation up to 2500 VRMS
for 1 minute per UL and 4242 VPK per VDE. These
devices have two isolated channels. Each channel
has a logic input and output buffer separated by a
silicon dioxide (SiO2) insulation barrier. Used in
conjunction with isolated power supplies, these
devices prevent noise currents on a data bus or other
circuit from entering the local ground and interfering
with or damaging sensitive circuitry. ISO7420 has
both channels in the same direction while ISO7421
has the two channels in opposite direction. In case of
input power or signal loss, default output is 'low' for
devices with suffix 'F' and 'high' for devices without
suffix 'F'. ISO742x have no integrated noise filter and
thus have fast propagation delays.
1
•
•
•
•
•
•
•
•
•
Signaling Rate > 50 Mbps
Default Output 'High' and 'Low' Options
Low Power Consumption: Typical ICC per Channel
(3.3-V Supplies):
– ISO7420: 1.4 mA at 1 Mbps, 2.5 mA at
25 Mbps
– ISO7421: 1.8 mA at 1 Mbps, 2.8 mA at
25 Mbps
Low Propagation Delay: 7 ns Typical
Low Pulse Skew: 200 ps Typical
Wide TA Range Specified: –40°C to 125°C
50-KV/μs Transient Immunity, Typical
Isolation Barrier Life: > 25 Years
Operates from 3-V to 5.5-V Supply Levels
3.3-V and 5-V Level Translation
Narrow Body SOIC-8 Package
Safety and Regulatory Approvals:
– 4242 VPK Isolation per DIN V VDE V 0884-10
and DIN EN 61010-1
– 2500 VRMS Isolation for 1 minute per UL 1577
– CSA Component Acceptance Notice 5A, IEC
60950-1 and IEC 61010-1 Standards
– CQC Certification per GB4943.1-2011
–
These devices have TTL input thresholds and
operate from 3-V to 5.5-V supplies. All inputs are 5-V
tolerant when supplied from a 3.3-V supply.
Device Information(1)
PART NUMBER
Opto-Coupler Replacement in:
– Industrial FieldBus
– ProfiBus
– ModBus
– DeviceNet™ Data Buses
– Servo Control Interface
– Motor Control
– Power Supplies
– Battery Packs
BODY SIZE (NOM)
ISO7420E
ISO7420FE
SOIC (8)
ISO7421E
4.90 mm x 3.91 mm
ISO7421FE
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
2 Applications
•
PACKAGE
VCCO
VCCI
Isolation
Capacitor
INx
OUTx
GNDI
GNDO
VCCI and GNDI are supply and ground
connections respectively for the input
channels.
VCCO and GNDO are supply and ground
connections respectively for the output
channels.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7420E, ISO7420FE, ISO7421E, ISO7421FE
SLLSE45F – DECEMBER 2010 – REVISED JULY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
Absolute Maximum Ratings ..................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics: VCC1 and VCC2 = 5 V ±
10% ............................................................................ 6
6.6 Electrical Characteristics: VCC1 = 5 V ± 10%, VCC2 =
3.3 V ± 10% ............................................................... 7
6.7 Electrical Characteristics: VCC1 = 3.3 V ± 10%, VCC2
= 5 V ± 10% ............................................................... 8
6.8 Electrical Characteristics: VCC1 and VCC2 = 3.3 V ±
10% ............................................................................ 9
6.9 Power Dissipation Characteristics ............................ 9
6.10 Switching Characteristics: VCC1 and VCC2 = 5 V ±
10% .......................................................................... 10
6.11 Switching Characteristics: VCC1 = 5 V ± 10%, VCC2
= 3.3 V ± 10% .......................................................... 10
6.12 Switching Characteristics: VCC1 = 3.3 V ± 10%,
VCC2 = 5 V ± 10% .................................................... 11
6.13 Switching Characteristics: VCC1 and VCC2 = 3.3 V ±
10% .......................................................................... 11
6.14 Typical Characteristics .......................................... 12
7
8
Parameter Measurement Information ................ 15
Detailed Description ............................................ 16
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
16
16
17
20
Applications and Implementation ...................... 21
9.1 Application Information............................................ 21
9.2 Typical Application ................................................. 21
10 Power Supply Recommendations ..................... 24
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 25
12 Device and Documentation Support ................. 26
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
13 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (January 2013) to Revision F
Page
•
Changed the datasheet format to the new TI standard.......................................................................................................... 1
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Deleted text from the Description: "CC-grade devices have integrated 10ns-filters for harsh environments where
short noise pulses may be present at the device input pins." ................................................................................................ 1
•
VDE standard changed to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 ...................................................................... 1
•
Deleted CC-grade from tPLH, tPHL in the Switching Characteristics table.............................................................................. 10
•
Deleted CC-grade from tPLH, tPHL in the Switching Characteristics table.............................................................................. 10
•
Deleted CC-grade from tPLH, tPHL in the Switching Characteristics table.............................................................................. 11
•
Deleted CC-grade from tPLH, tPHL in the Switching Characteristics table.............................................................................. 11
•
Changed the Available Options Table To the Feature Description table ............................................................................. 17
Changes from Revision D (December 2011) to Revision E
Page
•
Deleted devices ISO7420FCC and ISO7421FCC.................................................................................................................. 1
•
Changed the NOTE: text ...................................................................................................................................................... 17
•
Added table Note to VIORM .................................................................................................................................................... 18
•
Changed Z to Undetermined for the OUTPUT OUTA, OUTB column of the FUNCTION TABLE ....................................... 20
2
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SLLSE45F – DECEMBER 2010 – REVISED JULY 2015
Changes from Revision C (March 2011) to Revision D
Page
•
Changed SAFETY feature Bullet From: UL 1577 Approved; Other Approvals Pending To: All Agencies Approvals
Completed .............................................................................................................................................................................. 1
•
Changed the REGULATORY INFORMATION table ............................................................................................................ 18
Changes from Revision B (January 2011) to Revision C
Page
•
Added devices ISO7420FCC and ISO7421FCC.................................................................................................................... 1
•
Changed Feature bullet To: Low Propagation Delay: 7 ns Typical (E-Grade) ....................................................................... 1
•
Changed Feature bullet To: Low Pulse Skew: 200 Typical (E-Grade)................................................................................... 1
•
Changed the SAFETY and REGULATORY APPROVALS list............................................................................................... 1
•
Changed the data sheet DESCRIPTION................................................................................................................................ 1
•
Changed the Supply Current values for ISO7421x at 10, 25, and 50 Mbps .......................................................................... 6
•
Changed the Supply Current values for ISO7421x at 10, 25, and 50 Mbps .......................................................................... 7
•
Changed the Supply Current values for ISO7421x at 10, 25, and 50 Mbps .......................................................................... 8
•
Changed the Supply Current values for ISO7421x 25 and 50 Mbps ..................................................................................... 9
•
Added CC-grade and valued to tPLH, tPHL in the Switching Characteristics table ................................................................. 10
•
Added ISO7421x values for Pulse width distortion, Channel-to-channel output skew time, and Part-to-part skew time .... 10
•
Added CC-grade and valued to tPLH, tPHL in the Switching Characteristics table ................................................................. 10
•
Added ISO7421x values for Pulse width distortion and Channel-to-channel output skew time........................................... 10
•
Added CC-grade and valued to tPLH, tPHL in the Switching Characteristics table ................................................................. 11
•
Added CC-grade and valued to tPLH, tPHL in the Switching Characteristics table ................................................................. 11
•
Added graphs Figure 5, Figure 6, Figure 7, and Figure 8.................................................................................................... 12
•
Added graphs Figure 14 and Figure 15................................................................................................................................ 13
•
Changed Note 1 Figure 16 ................................................................................................................................................... 15
•
Changed Figure 17............................................................................................................................................................... 15
•
Changed the Available Options Table .................................................................................................................................. 17
•
Changed Isolation resistance test conditions ....................................................................................................................... 17
•
Changed the values of VIORM and VPR in the INSULATION CHARACTERISTICS table ..................................................... 18
•
Changed the value of VIOTM in the INSULATION CHARACTERISTICS table From: 4000 To: 4242 .................................. 18
•
Changed Figure 21............................................................................................................................................................... 19
•
Changed PU to X in the last row of the FUNCTION TABLE................................................................................................ 20
•
Added section: SUPPLY CURRENT EQUATIONS.............................................................................................................. 22
Changes from Revision A (December 2010) to Revision B
Page
•
Changed Feature bullet From: ISO7421: TBDmA at 1Mbps, TBDmA at 25Mbps To: ISO7421: 1.8mA at 1Mbps,
2.8mA at 25Mbps ................................................................................................................................................................... 1
•
Updated the ISO7421x Supply Current values for VCC1 and VCC2 = 5V ................................................................................. 6
•
Updated the ISO7421x Supply Current values for VCC1 = 5V and VCC2 = 3.3V ..................................................................... 7
•
Updated the ISO7421x Supply Current values for VCC1 = 3.3V and VCC2 = 5V ..................................................................... 8
•
Updated the ISO7421x Supply Current values for VCC1 and VCC2 = 3.3V.............................................................................. 9
Changes from Original (December 2010) to Revision A
•
Page
Changed the Max values for Supply current for VCC1 and VCC2, CL = 15pF........................................................................... 9
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SLLSE45F – DECEMBER 2010 – REVISED JULY 2015
www.ti.com
5 Pin Configuration and Functions
1
INA
2
INB
3
GND1
4
ISO7421 D Package
8-Pin SOIC
Top View
8
VCC2
7
OUTA
6
OUTB
5
GND2
VCC1
1
OUTA
2
INB
3
GND1
4
Isolation
VCC1
Isolation
ISO7420 D Package
8-Pin SOIC
Top View
8
VCC2
7
INA
6
OUTB
5
GND2
Pin Functions
PIN
NAME
I/O
DESCRIPTION
ISO7420x
ISO7421x
INA
2
7
I
Input, channel A
INB
3
3
I
Input, channel B
GND1
4
4
–
Ground connection for VCC1
GND2
5
5
–
Ground connection for VCC2
OUTA
7
2
O
Output, channel A
OUTB
6
6
O
Output, channel B
VCC1
1
1
–
Power supply, VCC1
VCC2
8
8
–
Power supply, VCC2
4
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SLLSE45F – DECEMBER 2010 – REVISED JULY 2015
6 Specifications
6.1 Absolute Maximum Ratings (1)
MIN
MAX
UNIT
VCC
Supply voltage (2), VCC1, VCC2
–0.5
6
V
VI
Voltage at IN, OUT
–0.5
VCC + 0.5 (3)
V
IO
Output current
±15
mA
VSRG
Maximum surge immunity - Supports IEC 61000-4-5
4000
VPK
TJ(Max)
Maximum junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal and are peak voltage values.
Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
Machine model (MM) ANSI/ESDS5.2-1996
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VCC1, VCC2
Supply voltage
3.0
IOH
High-level output current
–4
IOL
Low-level output current
VIH
High-level input voltage
2
5.5
V
VIL
Low-level input voltage
0
0.8
V
tui
Input pulse duration
1 / tui
Signaling rate
TJ (2)
TA
(1)
(2)
5.5
V
mA
4
mA
20
ns
0
50 (1)
Mbps
Junction temperature
–40
136
°C
Ambient Temperature
-40
125
°C
25
Under typical conditions, these devices are capable of signaling rate > 150 Mbps.
To maintain the recommended operating conditions for TJ, see the Thermal Information table.
6.4 Thermal Information
ISO742x
THERMAL METRIC (1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal
resistance
Low-K board
212
High-K board
116.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
71.6
°C/W
RθJB
Junction-to-board thermal resistance
57.3
°C/W
ψJT
Junction-to-top characterization parameter
28.3
°C/W
ψJB
Junction-to-board characterization parameter
56.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SLLSE45F – DECEMBER 2010 – REVISED JULY 2015
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6.5 Electrical Characteristics: VCC1 and VCC2 = 5 V ± 10%
TA = –40°C to 125°C
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CMTI
Common-mode transient immunity
MIN
TYP
IOH = –4 mA; see Figure 16.
VCCO (1)– 0.8
4.6
IOH = –20 μA; see Figure 16.
VCCO– 0.1
5
MAX
V
IOL = 4 mA; see Figure 16.
0.2
0.4
IOL = 20 μA; see Figure 16.
0
0.1
400
25
μA
μA
–10
VI = VCCI or 0 V; see Figure 18.
V
mV
10
INx at 0 V or VCCI (1)
UNIT
50
kV/μs
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC I CC MEASUREMENT)
ISO7420x
ICC1
DC to 1 Mbps
ICC2
ICC1
ICC2
ICC1
DC Input: VI = VCCI or 0 V,
AC Input: CL = 15 pF
10 Mbps
Supply current for VCC1 and VCC2
25 Mbps
ICC2
ICC1
CL = 15 pF
50 Mbps
ICC2
0.4
0.8
3.4
5
0.6
1
4.5
6
1
1.5
6.2
8
1.7
2.5
9
12
2.3
3.6
2.3
3.6
2.9
4.5
2.9
4.5
4.3
6
mA
ISO7421x
ICC1
DC to 1 Mbps
ICC2
ICC1
ICC2
ICC1
10 Mbps
Supply current for VCC1 and VCC2
25 Mbps
ICC2
ICC1
6
CL = 15 pF
50 Mbps
ICC2
(1)
DC Input: VI = VCCI or 0 V,
AC Input: CL = 15 pF
4.3
6
6
8.5
6
8.5
mA
VCCI = Input-side VCC; VCCO = Output-side VCC
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SLLSE45F – DECEMBER 2010 – REVISED JULY 2015
6.6 Electrical Characteristics: VCC1 = 5 V ± 10%, VCC2 = 3.3 V ± 10%
TA = –40°C to 125°C
PARAMETER
VOH
TEST CONDITIONS
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CMTI
Common-mode transient immunity
MIN
TYP
VCC1 – 0.8
4.6
ISO7420x/7421x (3.3-V side)
VCC2 - 0.4
3
ISO7421x (5-V side)
VCC1 – 0.1
5
ISO7420x/7421x (3.3-V side)
VCC2 – 0.1
3.3
IOH = –4 mA;
see Figure 16.
ISO7421x (5-V side)
IOH = –20 μA;
see Figure 16,
MAX
V
IOL = 4 mA; see Figure 16.
0.2
0.4
IOL = 20 μA; see Figure 16.
0
0.1
400
25
μA
μA
–10
VI = VCCI or 0 V; see Figure 18.
V
mV
10
INx at 0 V or VCCI
UNIT
50
kV/μs
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC I CC MEASUREMENT)
ISO7420x
ICC1
DC to 1 Mbps
ICC2
ICC1
ICC2
ICC1
DC Input: VI = VCCI or 0 V,
AC Input: CL = 15 pF
10 Mbps
Supply current for VCC1 and VCC2
25 Mbps
ICC2
ICC1
CL = 15 pF
50 Mbps
ICC2
0.4
0.8
2.6
3.7
0.6
1
3.3
4.3
1
1.5
4.4
5.6
1.7
2.5
6.2
7.5
2.3
3.6
1.8
2.8
2.9
4.5
2.2
3.2
4.3
6
2.8
4.1
6
8.5
3.8
5.5
mA
ISO7421x
ICC1
DC to 1 Mbps
ICC2
ICC1
ICC2
ICC1
DC Input: VI = VCCI or 0 V,
AC Input: CL = 15 pF
10 Mbps
Supply current for VCC1 and VCC2
25 Mbps
ICC2
ICC1
CL = 15 pF
50 Mbps
ICC2
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mA
7
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6.7 Electrical Characteristics: VCC1 = 3.3 V ± 10%, VCC2 = 5 V ± 10%
TA = –40°C to 125°C
PARAMETER
VOH
TEST CONDITIONS
MIN
TYP
IOH = –4 mA; see
Figure 16.
ISO7421x (3.3-V side)
VCC1 – 0.4
3
ISO7420x/7421x (5-V side)
VCC2 – 0.8
4.6
IOH = –20 μA;
see Figure 16
ISO7421x (3.3-V side)
VCC1 – 0.1
3.3
ISO7420x/7421x (5-V side)
VCC2 – 0.1
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CMTI
Common-mode transient immunity
MAX
V
5
IOL = 4 mA; see Figure 16.
0.2
0.4
IOL = 20 μA; see Figure 16.
0
0.1
400
25
μA
μA
–10
VI = VCCI or 0 V; see Figure 18.
V
mV
10
INx at 0 V or VCCI
UNIT
50
kV/μs
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC I CC MEASUREMENT)
ISO7420x
ICC1
DC to 1 Mbps
ICC2
ICC1
ICC2
ICC1
DC Input: VI = VCCI or 0 V,
AC Input: CL = 15 pF
10 Mbps
Supply current for VCC1 and VCC2
25 Mbps
ICC2
ICC1
CL = 15 pF
50 Mbps
ICC2
0.2
0.4
3.4
5
0.4
0.6
4.5
6
0.6
0.9
6.2
8
1
1.3
9
12
1.8
2.8
2.3
3.6
2.2
3.2
2.9
4.5
2.8
4.1
mA
ISO7421x
ICC1
DC to 1 Mbps
ICC2
ICC1
ICC2
ICC1
10 Mbps
Supply current for VCC2 and VCC2
25 Mbps
ICC2
ICC1
CL = 15 pF
50 Mbps
ICC2
8
DC Input: VI = VCCI or 0 V,
AC Input: CL = 15 pF
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4.3
6
3.8
5.5
6
8.5
mA
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SLLSE45F – DECEMBER 2010 – REVISED JULY 2015
6.8 Electrical Characteristics: VCC1 and VCC2 = 3.3 V ± 10%
TA = –40°C to 125°C
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CMTI
Common-mode transient immunity
MIN
TYP
IOH = –4 mA; see Figure 16.
VCCO (1) – 0.4
3
IOH = –20 μA; see Figure 16.
VCCO – 0.1
3.3
MAX
UNIT
V
IOL = 4 mA; see Figure 16.
0.2
0.4
IOL = 20 μA; see Figure 16.
0
0.1
V
400
mV
μA
10
INx at 0 V or VCCI (1)
μA
–10
VI = VCCI or 0 V; see Figure 18.
25
50
kV/μs
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC I CC MEASUREMENT)
ISO7420x
ICC1
DC to 1 Mbps
ICC2
ICC1
ICC2
ICC1
DC Input: VI = VCCI or 0 V,
AC Input: CL = 15 pF
10 Mbps
Supply current for VCC1 and VCC2
25 Mbps
ICC2
ICC1
CL = 15 pF
50 Mbps
ICC2
0.2
0.4
2.6
3.7
0.4
0.6
3.3
4.3
0.6
0.9
4.4
5.6
1
1.3
6.2
7.5
1.8
2.8
1.8
2.8
2.2
3.2
2.2
3.2
2.8
4.1
2.8
4.1
3.8
5.5
3.8
5.5
mA
ISO7421x
ICC1
DC to 1 Mbps
ICC2
ICC1
ICC2
ICC1
10 Mbps
Supply current for VCC2 and VCC2
25 Mbps
ICC2
ICC1
CL = 15 pF
50 Mbps
ICC2
(1)
DC Input: VI = VCCI or 0 V,
AC Input: CL = 15 pF
mA
VCCI = Input-side VCC; VCCO = Output-side VCC
6.9 Power Dissipation Characteristics
ISO742x
THERMAL METRIC
D (SOIC)
UNIT
8 PINS
PD
Device power dissipation
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 100-Mbps 50% duty-cycle square wave
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6.10 Switching Characteristics: VCC1 and VCC2 = 5 V ± 10%
TA = –40°C to 125°C
PARAMETER
tPLH, tPHL
PWD (1)
Pulse width distortion |tPHL – tPLH|
tsk(o) (2)
Channel-to-channel output skew time
tsk(pp) (3)
Part-to-part skew time
tr
Output signal rise time
tf
Output signal fall time
tfs
Fail-safe output delay time from input power loss
(1)
(2)
(3)
TEST CONDITIONS
MIN
TYP
MAX
7
11
0.2
3
ISO7421x
0.3
3.7
ISO7420x
0.3
1
ISO7421x
0.3
2
Propagation delay time
ISO7420x
See Figure 16.
ISO7420x
3.7
ISO7421x
4.9
See Figure 16.
See Figure 17.
UNIT
ns
ns
ns
ns
1.8
ns
1.7
ns
6
μs
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.11 Switching Characteristics: VCC1 = 5 V ± 10%, VCC2 = 3.3 V ± 10%
TA = –40°C to 125°C
PARAMETER
tPLH, tPHL
PWD
(1)
Pulse width distortion |tPHL – tPLH|
tsk(o) (2)
Channel-to-channel output skew time
tsk(pp) (3)
Part-to-part skew time
tr
Output signal rise time
tf
Output signal fall time
tfs
Fail-safe output delay time from input power loss
(1)
(2)
(3)
10
TEST CONDITIONS
Propagation delay time
ISO7420x
See Figure 16.
ISO7421x
MIN
TYP
MAX
UNIT
8
13.5
ns
0.3
3
0.5
5.6
ISO7420x
1.5
ISO7421x
0.5
3
ISO7420x
5.4
ISO7421x
6.3
See Figure 16.
See Figure 17.
ns
ns
ns
2
ns
2
ns
6
μs
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.12 Switching Characteristics: VCC1 = 3.3 V ± 10%, VCC2 = 5 V ± 10%
TA = –40°C to 125°C
PARAMETER
tPLH, tPHL
Propagation delay time
ISO7421x
PWD (1)
Pulse width distortion |tPHL – tPLH|
tsk(o) (2)
Channel-to-channel output skew time
tsk(pp) (3)
Part-to-part skew time
tr
Output signal rise time
tf
Output signal fall time
tfs
Fail-safe output delay time from input power loss
(1)
(2)
(3)
TEST CONDITIONS
MIN
ISO7420x
ISO7420x
See Figure 16.
TYP
MAX
7.5
12
7.5
14
0.7
3
ISO7421x
0.7
3.6
ISO7420x
0.5
1.5
ISO7421x
0.5
3
ISO7420x
4.6
ISO7421x
8.5
See Figure 16.
See Figure 17.
UNIT
ns
ns
ns
ns
1.7
ns
1.6
ns
6
μs
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.13 Switching Characteristics: VCC1 and VCC2 = 3.3 V ± 10%
TA = –40°C to 125°C
PARAMETER
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse width distortion |tPHL – tPLH|
tsk(o) (2)
Channel-to-channel output skew time
tsk(pp) (3)
Part-to-part skew time
tr
Output signal rise time
tf
Output signal fall time
tfs
Fail-safe output delay time from input power loss
(1)
(2)
(3)
TEST CONDITIONS
TYP
MAX
8.5
14
ns
0.5
2
ns
ISO7420x
0.4
2
ISO7421x
0.4
3
ISO7420x and ISO7421x
See Figure 16
MIN
ISO7420x
6.2
ISO7421x
6.8
See Figure 16
See Figure 17
UNIT
ns
ns
2
ns
1.8
ns
6
μs
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.14 Typical Characteristics
12
6
TA = 25oC
No Load
o
TA = 25 C
No Load
ICC2 at 5 V
10
Supply Current - mA
Supply Current - mA
5
4
ICC2 at 3.3 V
3
2
ICC1 at 5 V
ICC2 at 5 V
8
ICC2 at 3.3 V
6
4
ICC1 at 5 V
2
1
ICC1 at 3.3 V
ICC1 at 3.3 V
0
0
0
20
40
60
80
100
0
120
20
40
80
8
o
TA = 25 C
CL = 15 pF Load
7
TA = 25 C
CL = 15 pF Load
14
ICC2 at 5 V
ICC2 at 5 V
12
Supply Current - mA
6
ICC2 at 3.3 V
5
4
3
10
ICC2 at 3.3 V
8
6
4
ICC1 at 5 V
2
ICC1 at 5 V
2
1
ICC1 at 3.3 V
ICC1 at 3.3 V
0
0
20
40
60
80
100
0
120
20
40
Figure 3. ISO7420 Supply Current Per Channel vs Data Rate
(15 pF Load)
4
8
o
3.5
100
120
o
TA = 25 C
No Load
7
3
6
ICC1 and ICC2 at 5 V
Supply Current - mA
Supply Current - mA
80
Figure 4. ISO7420 Supply Current Both Channels vs Data
Rate (15 pF Load)
TA = 25 C
No Load
2.5
2
1.5
ICC1 and ICC2 at 3.3 V
ICC1 and ICC2 at 5 V
5
4
3
ICC1 and ICC2 at 3.3 V
1
2
0.5
1
0
60
Data Rate - Mbps
Data Rate - Mbps
0
20
40
60
80
100
120
Data Rate - Mbps
Figure 5. ISO7421 Supply Current Per Channel vs Data Rate
(No Load)
12
120
16
o
0
100
Figure 2. ISO7420 Supply Current Both Channels vs Data
Rate (No Load)
Figure 1. ISO7420 Supply Current Per Channel vs Data Rate
(No Load)
Supply Current - mA
60
Data Rate - Mbps
Data Rate - Mbps
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0
0
20
40
60
80
100
120
Data Rate - Mbps
Figure 6. ISO7421 Supply Current Both Channels vs Data
Rate (No Load)
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Typical Characteristics (continued)
7
10
o
TA = 25 C
CL15 pF
6
o
TA = 25 C
CL15 pF
9
7
Supply Current - mA
Supply Current - mA
8
5
ICC1 and ICC2 at 5 V
4
3
ICC1 and ICC2 at 3.3 V
2
ICC1 and ICC2 at 5 V
6
5
4
ICC1 and ICC2 at 3.3 V
3
2
1
1
0
0
20
40
60
80
100
0
120
0
20
40
Data Rate - Mbps
Figure 7. ISO7421 Supply Current Per Channel vs Data Rate
(15 pF Load)
80
100
120
Figure 8. ISO7421 Supply Current Both Channels vs Data
Rate (15 pF Load)
8
10.5
VCC1 = VCC2 = 5 V,
CL = 15 pF
tpd - Propagation Delay Time - ns
tpd - Propagation Delay Time - ns
60
Data Rate - Mbps
7.5
tPLH
7
tPHL
6.5
6
-50
-25
0
25
50
75
100
TA - Free-Air Temperature - °C
125
150
Figure 9. Propagation Delay Time vs Free-Air Temperature
10
VCC1 = VCC2 = 3.3 V,
CL = 15 pF
tPLH
9.5
9
8.5
tPHL
8
7.5
-50
-25
0
25
50
75
100
TA - Free-Air Temperature - °C
125
150
Figure 10. Propagation Delay Time vs Free-Air Temperature
2.7
6
TA = 25°C
Fail-Safe Voltage Threshold - V
VOH - High-Level Output Voltage - V
FS+
2.65
2.6
2.55
2.5
FS2.45
2.4
-50
-25
0
25
50
75
100
TA - Free-Air Temperature - °C
125
150
Figure 11. Input VCC Fail-Safe Voltage Threshold vs Free-Air
Temperature
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5
4
Output VCC = 5 V
3
2
Output VCC = 3.3 V
1
0
-80
-70
-60
-50
-40
-30
-20
IOH - High-Level Output Current - mA
-10
0
Figure 12. High-Level Output Voltage vs High-Level Output
Current
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Typical Characteristics (continued)
1.4
6
1.2
5
Output Jitter (PK-PK) - ns
VOL - Low-Level Output Voltage - V
TA = 25°C
4
3
Output VCC = 3.3 V
2
OUTA and OUTB, 3.3V-Oper.
0.8
0.6
OUTA and OUTB, 5V-Oper.
0.4
Output VCC = 5 V
o
1
0
1
TA = 25 C
CL15 pF
0.2
0
10
20
30
40
50
60
0
70
0
20
40
60
80
100
120
IOL - Low-Level Output Current - mA
Data Rate - Mbps
Figure 13. Low-Level Output Voltage vs Low-Level Output
Current
Figure 14. ISO7420FE Output Jitter vs Data Rate
1.6
Output Jitter (PK-PK) - ns
1.4
1.2
OUTA and OUTB, 3.3V-Oper.
1
0.8
0.6
OUTA and OUTB, 5V-Oper.
0.4
o
TA = 25 C
CL15 pF
0.2
0
0
20
40
60
80
100
120
Data Rate - Mbps
Figure 15. ISO7421FE Output Jitter vs Data Rate
14
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Isolation Barrier
7 Parameter Measurement Information
IN
Input
Generator
(1)
VI
50 W
VCCI
VI
OUT
1.4 V
1.4 V
0V
VO
CL
tPLH
(2)
tPHL
90%
10%
50%
VO
VOH
50%
VOL
tr
tf
(1)
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate the Input Generator signal. It is not
needed in an actual application.
(2)
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 16. Switching Characteristic Test Circuit and Voltage Waveforms
VI
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
(1)
VCCI
ISOLATION BARRIER
VCCI
IN
2.7 V
VI
OUT
0V
t fs
VO
fs high
VO
(1)
CL
VOH
50%
fs low V
OL
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 17. Fail-Safe Output Delay-Time Test Circuit and Voltage Waveforms
S1
IN
C = 0.1 μ F ±1%
Isolation Barrier
VCCI
GNDI
VCCO
C = 0.1 μ F ±1%
Pass-fail criteria –
output must remain
stable.
OUT
+
(1)
CL
GNDO
VOH or VOL
–
+ VCM –
(1)
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 18. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The isolator in Figure 19 is based on a capacitive isolation barrier technique. The I/O channel of the device
consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to
150 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a
single- ended input signal entering the HF-channel is split into a differential signal via the inverter gate at the
input. The following capacitor-resistor networks differentiate the signal into transients, which then are converted
into differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output
feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations
between signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in
the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high- to the lowfrequency channel.
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these
signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a
sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-pass
filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output
multiplexer.
8.2 Functional Block Diagram
Figure 19. Conceptual Block Diagram of a Digital Capacitive Isolator
16
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8.3 Feature Description
ISO742x are available in multiple channel configurations and default output state options to enable wide variety
of application uses.
PRODUCT
DATA RATE
DEFAULT OUTPUT
ISO7420E
RATED TA
CHANNEL DIRECTION
High
ISO7420FE
Low
50 Mbps
ISO7421E
High
ISO7421FE
Same
–40°C to 125°C
Opposite
Low
8.3.1 Insulation and Safety-Related Specifications for D-8 Package
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
L(I01)
Minimum air gap (clearance)
Shortest terminal-to-terminal distance through air
4
mm
L(I02)
Minimum external tracking
(creepage)
Shortest terminal-to-terminal distance across the
package surface
4
mm
CTI
Tracking resistance (comparative
tracking index)
DIN EN 60112 (VDE 0303-11); IEC 60112
>400
V
Minimum internal gap (internal
clearance)
Distance through the insulation
0.014
mm
RIO
Isolation resistance, input to
output (1)
CIO
Barrier capacitance, input to
output (1)
CI
Input capacitance (2)
(1)
(2)
>1012
Ω
11
Ω
VIO = 0.4 sin (2πft), f = 1 MHz
1
pF
VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V
1
pF
VIO = 500 V, TA = 25°C
VIO = 500 V, 100°C ≤ TA ≤ max
>10
All pins on each side of the barrier tied together creating a two-terminal device.
Measured from input pin to ground.
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance.
Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to
help increase these specifications.
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8.3.2 Insulation Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER (1)
TEST CONDITIONS
SPECIFICATION
UNIT
566
VPEAK
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM
Maximum workingisolation voltage
VPR
Input-to-output test voltage
Method a, After environmental tests subgroup 1,
VPR = VIORM x 1.6, t = 10 s,
Partial Discharge < 5 pC
906
Method b1,
VPR = VIORM x 1.875, t = 1 s (100% Production test)
Partial discharge < 5 pC
1062
After Input/Output safety test subgroup 2/3,
VPR = VIORM x 1.2, t = 10 s,
Partial discharge < 5 pC
680
VPEAK
VIOTM
Maximum transient isolation voltage
VTEST = VIOTM = 4242 VPK
t = 60 sec (qualification)
t= 1 sec (100% production)
4242
VPEAK
RS
Isolation resistance
VIO = 500 V at TS = 150°C
>109
Ω
Pollution degree
2
UL 1577
VISO
(1)
VTEST = VISO = 2500 VRMS, t = 60 sec
(qualification);
VTEST = 1.2 x VISO = 3000 VRMS, t = 1 sec (100%
production)
Maximum withstand isolation voltage
2500
VRMS
Climatic Classification 40/125/21
Table 1. IEC 60664-1 Ratings Table
PARAMETER
TEST CONDITIONS
Basic isolation group
SPECIFICATION
Material group
Installation classification
II
Rated mains voltage ≤ 150 VRMS
I–IV
Rated mains voltage ≤ 300 VRMS
I–III
8.3.3 Regulatory Information
VDE
CSA
Certified according to DIN V
VDE V 0884-10 (VDE V 0884- Approved under CSA Component
10):2006-12 and DIN EN
Acceptance Notice 5A, IEC 60950-1,
61010-1 (VDE 0411-1):2011and IEC 61010-1
07
UL
Recognized under UL 1577
Component Recognition Program
CQC
Certified according to GB
4943.1-2011
Basic Insulation;
Maximum Transient Isolation
Voltage, 4242 VPK;
Maximum Working Isolation
Voltage, 566 VPK
2500 VRMS Isolation Rating;
Basic insulation per CSA 60950-107+A1 and IEC 60950-1 2nd Ed+A1,
384 VRMS maximum working voltage;
CSA 61010-1-04 and IEC 61010-1
2nd Ed, 300 VRMS maximum working
voltage for basic insulation and 150
VRMS for reinforced insulation
Basic Insulation, Altitude ≤
Single Protection Isolation Voltage, 5000 m, Tropical Climate, 250
2500 VRMS (1)
VRMS maximum working
voltage
Certificate number: 40016131
Master contract number: 220991
File number: E181974
(1)
18
Certificate number:
CQC14001109540
Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
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8.3.4 Life Expectancy vs Working Voltage
Life Expectancy – Years
100
VIORM at 566 V
28 Years
10
0
120
250
500
750
880
1000
VIORM – Working Voltage – VPK
G001
Figure 20. Life Expectancy vs Working Voltage
8.3.5 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
IS
Safety input, output, or supply
current
TS
Maximum safety temperature
MIN
TYP
MAX
θJA = 212°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
107
θJA = 212°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
164
150
UNIT
mA
°C
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum
Ratings (1) table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed in the JESD51-3, Low-Effective-Thermal-Conductivity Test
Board for Leaded Surface-Mount Packages and is conservative. The power is the recommended maximum input
voltage times the current. The junction temperature is then the ambient temperature plus the power times the
junction-to-air thermal resistance.
Safety Limiting Current − mA
180
160
VCC1, VCC2 at 3.6 V
140
120
100
VCC1, VCC2 at 5.5 V
80
60
40
20
0
0
50
100
150
200
Case Temperature − °C
Figure 21. θJC Thermal Derating Curve per VDE
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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8.4 Device Functional Modes
Table 2. Functional Table (1)
VCCI
PU
(1)
(2)
(3)
INPUT
INA, INB
VCCO
OUTPUT
OUTA, OUTB
ISO7420E / ISO7421E
ISO7420FE / ISO7421FE
H
H
H
L
L
L
Open
H (2)
L (3)
PU
PD
PU
X
H (2)
L (3)
X
PD
X
Undetermined
Undetermined
VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 3 V); PD = Powered down (VCC ≤ 2.1 V); X = Irrelevant; H =
High level; L = Low level;
In fail-safe condition, output defaults to high level
In fail-safe condition, output defaults to low level
8.4.1 Device I/O Schematic
ISO742xE Input
VCCI
VCCI
VCCI
1 MW
500 W
Output
VCCO
IN
8W
OUT
13 W
ISO742xFx Input
VCCI
VCCI
500 W
IN
1 MW
Figure 22. Device I/O Schematics
20
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Product Folder Links: ISO7420E ISO7420FE ISO7421E ISO7421FE
ISO7420E, ISO7420FE, ISO7421E, ISO7421FE
www.ti.com
SLLSE45F – DECEMBER 2010 – REVISED JULY 2015
9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
ISO742x utilize single-ended TTL-logic switching technology. Its supply voltage range is from 3 V to 5.5 V for
both supplies, VCC1 and VCC2. When designing with digital isolators, it is important to keep in mind that due to the
single-ended design structure, digital isolators do not conform to any specific interface standard and are only
intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the
data controller (i.e. μC or UART), and a data converter or a line transceiver, regardless of the interface type or
standard.
9.2 Typical Application
ISO7421 can be used with Texas Instruments' mixed signal micro-controller, digital-to-analog converter,
transformer driver, and voltage regulator to create an isolated 4-20 mA current loop.
VCC1
VCC2
ISO7421
Figure 23. Isolated 4-20 mA Current Loop
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SLLSE45F – DECEMBER 2010 – REVISED JULY 2015
www.ti.com
Typical Application (continued)
9.2.1 Design Requirements
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO742x only require two external bypass capacitors to operate.
9.2.2 Detailed Design Procedure
9.2.2.1 Maximum Supply Current Equations
(Calculated over recommended operating temperature range and Silicon process variation)
9.2.2.1.1 ISO7420
At VCC1 = VCC2 = 3.3V ± 10%
ICC1(max) = ICC1_Q (max) + 1.791 x 10-2 x f
ICC2(max) = ICC2_Q (max) + 1.687 x 10-2 x f + 3.570 x 10-3 x f x CL
(1)
(2)
At VCC1 = VCC2 = 5V ± 10%
ICC1(max) = ICC1_Q (max) + 3.152 x 10-2 x f
ICC2(max) = ICC2_Q (max) + 2.709 x 10-2 x f + 5.365 x 10-3 x f x CL
(3)
(4)
9.2.2.1.2 ISO7421
At VCC1 = VCC2 = 3.3V ± 10%
ICC1(max) = ICC1_Q (max) + 1.726 x 10-2 x f + 1.785 x 10-3 x f x CL
ICC2(max) = ICC2_Q (max) + 1.726 x 10-2 x f + 1.785 x 10-3 x f x CL
(5)
(6)
At VCC1 = VCC2 = 5V ± 10%
ICC1(max) = ICC1_Q (max) + 2.920 x 10-2 x f + 2.682 x 10-3 x f x CL
ICC2(max) = ICC2_Q (max) + 2.920 x 10-2 x f + 2.682 x 10-3 x f x CL
(7)
(8)
ICC1_Q (max) and ICC2_Q (max) are equivalent to the maximum supply currents measured in mA under DC input
conditions (provided in the specification tables of this data sheet); f is data rate in Mbps of both channels; CL is
the capacitive load in pF of both channels. ICC1(max) and ICC2(max) are measured in mA.
9.2.2.2 Typical Supply Current Equations:
(Calculated over recommended operating temperature range and Silicon process variation)
9.2.2.2.1 ISO7420
At VCC1 = VCC2 = 3.3V
ICC1(typ) = ICC1_Q (typ) + 1.528 x 10-2 x f
ICC2(typ) = ICC2_Q (typ) + 1.637 x 10-2 x f + 3.275 x 10-3 x f x CL
(9)
(10)
At VCC1 = VCC2 = 5V
ICC1(typ) = ICC1_Q (typ) + 2.640 x 10-2 x f
ICC2(typ) = ICC2_Q (typ) + 2.502 x 10-2 x f + 4.919 x 10-3 x f x CL
(11)
(12)
9.2.2.2.2 ISO7421
At VCC1 = VCC2 = 3.3V
ICC1(typ) = ICC1_Q (typ) + 1.567 x 10-2 x f + 1.640 x 10-3 x f x CL
ICC2(typ) = ICC2_Q (typ) + 1.567 x 10-2 x f + 1.640 x 10-3 x f x CL
(13)
(14)
At VCC1 = VCC2 = 5V
ICC1(typ) = ICC1_Q (typ) + 2.550 x 10-2 x f + 2.416 x 10-3 x f x CL
ICC2(typ) = ICC2_Q (typ) + 2.550 x 10-2 x f + 2.461 x 10-3 x f x CL
22
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(15)
(16)
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: ISO7420E ISO7420FE ISO7421E ISO7421FE
ISO7420E, ISO7420FE, ISO7421E, ISO7421FE
www.ti.com
SLLSE45F – DECEMBER 2010 – REVISED JULY 2015
Typical Application (continued)
ICC1_Q (typ) and ICC2_Q (typ) are equivalent to the typical supply currents measured in mA under DC input
conditions (provided in the specification tables of this data sheet); f is data rate in Mbps of each channel; CL is
the capacitive load in pF of each channel. ICC1(typ) and ICC2(typ) are measured in mA.
VCC1
1
8
VCC2
0.1 µF
0.1 µF
INA
2
7
OUTA
INB
3
6
OUTB
GND1
4
5
GND2
Figure 24. Typical ISO7420 Circuit Hookup
VCC1
1
8
VCC2
0.1 µF
0.1 µF
OUTA
2
7
INA
INB
3
6
OUTB
GND1
4
5
GND2
Figure 25. Typical ISO7421 Circuit Hookup
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Product Folder Links: ISO7420E ISO7420FE ISO7421E ISO7421FE
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ISO7420E, ISO7420FE, ISO7421E, ISO7421FE
SLLSE45F – DECEMBER 2010 – REVISED JULY 2015
www.ti.com
Typical Application (continued)
9.2.3 Application Curves
TA = 25°C, VCC1 = VCC2 = 3.3 V, Pattern: PRBS 27-1
Figure 26. ISO7420FE Typical Eye Diagram at 50 MBPS,
3.3 V Operation
TA = 25°C, VCC1 = VCC2 = 3.3 V, Pattern: PRBS 27-1
Figure 27. ISO7420FE Typical Eye Diagram at 100 MBPS,
3.3 V Operation
10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, a 0.1 µF bypass capacitor is recommended at
input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501. For
such applications, detailed power supply design and transformer selection recommendations are available in
SN6501 datasheet (SLLSEA0).
24
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Product Folder Links: ISO7420E ISO7420FE ISO7421E ISO7421FE
ISO7420E, ISO7420FE, ISO7421E, ISO7421FE
www.ti.com
SLLSE45F – DECEMBER 2010 – REVISED JULY 2015
11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 28). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the
stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see Application Note Digital Isolator Design Guide, SLLA284.
11.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the
requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower
dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its selfextinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces , pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 28. Recommended Layer Stack
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ISO7420E, ISO7420FE, ISO7421E, ISO7421FE
SLLSE45F – DECEMBER 2010 – REVISED JULY 2015
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• SN6501 Transformer Driver for Isolated Power Supplies, SLLSEA0
• Isolation Glossary, SLLS353
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ISO7420E
Click here
Click here
Click here
Click here
Click here
ISO7420FE
Click here
Click here
Click here
Click here
Click here
ISO7421E
Click here
Click here
Click here
Click here
Click here
ISO7421FE
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
DeviceNet, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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Product Folder Links: ISO7420E ISO7420FE ISO7421E ISO7421FE
PACKAGE OPTION ADDENDUM
www.ti.com
21-May-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
ISO7420ED
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
SO7420
ISO7420EDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
SO7420
ISO7420FED
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7420F
ISO7420FEDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7420F
ISO7421ED
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
SO7421
ISO7421EDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
SO7421
ISO7421FED
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7421F
ISO7421FEDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
I7421F
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
21-May-2013
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO7421E :
• Automotive: ISO7421E-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ISO7420EDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7420FEDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7421EDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7421FEDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO7420EDR
SOIC
D
8
2500
350.0
350.0
43.0
ISO7420FEDR
SOIC
D
8
2500
350.0
350.0
43.0
ISO7421EDR
SOIC
D
8
2500
350.0
350.0
43.0
ISO7421FEDR
SOIC
D
8
2500
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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