Texas Instruments | Low-Power Dual-Channel Isolators, ISO7420-Q1, ISO7421A-Q1 (Rev. B) | Datasheet | Texas Instruments Low-Power Dual-Channel Isolators, ISO7420-Q1, ISO7421A-Q1 (Rev. B) Datasheet

Texas Instruments Low-Power Dual-Channel Isolators, ISO7420-Q1, ISO7421A-Q1 (Rev. B) Datasheet
ISO7421A-Q1
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SLLSE14B – MARCH 2012 – REVISED SEPTEMBER 2013
LOW-POWER DUAL DIGITAL ISOLATORS
FEATURES
1
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following
Results:
– Device Temperature Grade 1: –40°C to
125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level H3A
– Device CDM ESD Classification Level C5
High Signaling Rate: 50 Mbps
Low Power Consumption
Low Propagation Delay – 9 ns (Typical)
Low Skew – 300 ps (Typical)
4-kVpeak Maximum Isolation, 2.5 kVrms per
UL 1577, IEC/VDE and CSA Approved, IEC
60950-1, IEC 61010-1 End Equipment
Standards Approved. All Approvals Pending.
50 kV/μs Transient Immunity (Typical)
Over 25-Year Isolation Integrity at Rated
Voltage
Operates From 3-V to 5.5-V Supply and Logic
Levels
ISO7421A-Q1
D PACKAGE
(TOP VIEW)
VCC1
1
OUTA
2
INB
3
GND1
4
Isolation
•
•
8
VCC2
7
INA
6
OUTB
5
GND2
DESCRIPTION
The ISO7421A-Q1 provides galvanic isolation up to 2.5 kVrms for 1 minute per UL. This digital isolator has two
isolated channels with bidirectional channel configuration. Each isolation channel has a logic input and output
buffer separated by a silicon dioxide (SiO2) insulation barrier. Used in conjunction with isolated power supplies,
these devices prevent noise currents on a data bus or other circuit from entering the local ground and interfering
with or damaging sensitive circuitry.
The devices have TTL input thresholds and require two supply voltages from 3 V to 5.5 V, or any combination.
All inputs are 5-V tolerant when supplied from a 3-V supply.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 125°C
(1)
(2)
SOIC – D
Reel of 2500
ORDERABLE PART NUMBER
ISO7421AQDRQ1
TOP-SIDE MARKING
7421AQ
For the most-current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
ISO7421A-Q1
SLLSE14B – MARCH 2012 – REVISED SEPTEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PIN FUNCTIONS
PIN
NAME
I/O
NO.
DESCRIPTION
GND1
4
–
Ground connection for VCC1
GND2
5
–
Ground connection for VCC2
INA
7
I
Input, channel A
INB
3
I
Input, channel B
OUTA
2
O
Output, channel A
OUTB
6
O
Output, channel B
VCC1
1
–
Power supply, VCC1
VCC2
8
–
Power supply, VCC2
Table 1. FUNCTION TABLE (1)
INPUT SIDE
VCC
PU
PD
(1)
OUTPUT SIDE
VCC
PU
PU
INPUT
IN
OUTPUT
OUT
H
H
L
L
Open
H
X
H
PU = Powered up (VCC ≥ 3 V), PD = Powered down (VCC ≤ 2.4 V),
X = Irrelevant, H = High level, L = Low level
ABSOLUTE MAXIMUM RATINGS (1)
VCC
Supply voltage (2), VCC1, VCC2
–0.5 V to 6 V
VI
Voltage at IN, OUT
–0.5 V to 6 V
IO
Output current
±15 mA
Human-body model (HBM) AEC-Q100 Classification Level H3A
ESD
Electrostatic
discharge
Charged-device model (CDM) AEC-Q100 Classification Level C5
4 kV
All pins
1.5 kV
Machine model (MM)
200 V
TJ(Max) Maximum junction temperature
(1)
(2)
150°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values.
RECOMMENDED OPERATING CONDITIONS
MIN
TYP MAX
3
5.5
UNIT
VCC1, VCC2
Supply voltage
IOH
High-level output current
IOL
Low-level output current
VIH
High-level input voltage
VIL
Low-level input voltage
0
0.8
V
TA
Operating temperature
–40
125
°C
2
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–4
mA
4
2
V
VCC
mA
V
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ISO7421A-Q1
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ELECTRICAL CHARACTERISTICS
VCC1 = VCC2 = 5 V ±10%, TA = –40°C to 125°C
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
TEST CONDITIONS
MIN
TYP
IOH = –4 mA, see Figure 1
VCC – 0.8
4.6
IOH = –20 μA, see Figure 1
VCC – 0.1
5
MAX
V
IOL = 4 mA, see Figure 1
0.2
0.4
IOL = 20 μA, see Figure 1
0
0.1
VI(HYS) Input threshold voltage hysteresis
400
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, see Figure 3
V
mV
10
IN from 0 V or VCC
UNIT
μA
μA
–10
25
1.2
pF
50
kV/μs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic I CC measurement)
ICC1
DC to 1 Mbps
ICC2
ICC1
DC Input: VI = VCC or 0 V
2.3
3.6
AC Input: CL = 15 pF
2.3
3.6
2.9
4.5
2.9
4.5
4.3
6
10 Mbps
ICC2
Supply current for VCC1 and VCC2
ICC1
25 Mbps
ICC2
ICC1
CL = 15 pF
50 Mbps
ICC2
4.3
6
6
9.1
6
9.1
TYP
MAX
mA
SWITCHING CHARACTERISTICS
VCC1 = VCC2 = 5 V ±10%, TA = –40°C to 125°C
PARAMETER
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse duration distortion |tPHL – tPLH|
tsk(pp)
TEST CONDITIONS
MIN
9
14
ns
0.3
3.7
ns
Part-to-part skew time
4.9
ns
tsk(o)
Channel-to-channel output skew time
3.6
ns
tr
Output signal rise time
tf
Output signal fall time
tfs
Fail-safe output delay time from input power loss
tui
Input pulse duration
7
1 / tui
Signaling rate
0
(1)
See Figure 1
UNIT
See Figure 1
1
See Figure 2
ns
1
ns
6
μs
ns
50
Mbps
Also known as pulse skew
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ELECTRICAL CHARACTERISTICS
VCC1 = 5 V ±10%, VCC2 = 3.3 V ±10%, TA = –40°C to 125°C
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
TEST CONDITIONS
MIN
IOH = –4 mA, see Figure 1, 5-V side
VCC – 0.8
IOH = –20 μA, see Figure 1
VCC – 0.1
TYP
MAX
V
IOL = 4 mA, see Figure 1
0.4
IOL = 20 μA, see Figure 1
0.1
VI(HYS) Input threshold voltage hysteresis
UNIT
V
400
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, see Figure 3
mV
μA
10
IN from 0 V or VCC
μA
–10
25
1.2
pF
40
kV/μs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic I CC measurement)
ICC1
DC to 1 Mbps
ICC2
ICC1
DC Input: VI = VCC or 0 V
2.3
3.6
AC Input: CL = 15 pF
1.8
2.8
2.9
4.5
2.2
3.2
4.3
6
2.8
4.1
6
9.1
3.8
5.8
TYP
MAX
10 Mbps
ICC2
Supply current for VCC1 and VCC2
ICC1
25 Mbps
ICC2
ICC1
CL = 15 pF
50 Mbps
ICC2
mA
SWITCHING CHARACTERISTICS
VCC1 = 5 V ±10%, VCC2 = 3.3 V ±10%, TA = –40°C to 125°C
PARAMETER
TEST CONDITIONS
MIN
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse duration distortion |tPHL – tPLH|
tsk(pp)
Part-to-part skew time
tsk(o)
Channel-to-channel output skew time
tr
Output signal rise time
tf
Output signal fall time
tfs
Fail-safe output delay time from input power loss
tui
Input pulse duration
7
1 / tui
Signaling rate
0
(1)
4
See Figure 1
See Figure 1
10
17
ns
0.5
5.6
ns
6.3
ns
4
ns
2
See Figure 2
UNIT
ns
2
ns
6
μs
ns
50
Mbps
Also known as pulse skew
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ELECTRICAL CHARACTERISTICS
VCC1 = 3.3 V ±10%, VCC2 = 5 V ±10%, TA = –40°C to 125°C
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
TEST CONDITIONS
MIN
IOH = –4 mA, see Figure 1, 3.3-V side
VCC – 0.4
IOH = –20 μA, see Figure 1
VCC – 0.1
TYP
MAX
V
IOL = 4 mA, see Figure 1
0.4
IOL = 20 μA, see Figure 1
0
VI(HYS) Input threshold voltage hysteresis
0.1
400
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, see Figure 3
μA
μA
–10
25
V
mV
10
IN from 0 V or VCC
UNIT
1
pF
40
kV/μs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic I CC measurement)
ICC1
DC to 1 Mbps
ICC2
ICC1
DC Input: VI = VCC or 0 V
1.8
2.8
AC Input: CL = 15 pF
2.3
3.6
2.2
3.2
2.9
4.5
2.8
4.1
10 Mbps
ICC2
Supply current for VCC1 and VCC2
ICC1
25 Mbps
ICC2
ICC1
CL = 15 pF
50 Mbps
ICC2
mA
4.3
6
3.8
5.8
6
9.1
TYP
MAX
10
17
ns
0.5
4
ns
8.5
ns
4
ns
SWITCHING CHARACTERISTICS
VCC1 = 3.3 V ±10%, VCC2 = 5 V ±10%, TA = –40°C to 125°C
PARAMETER
TEST CONDITIONS
MIN
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse duration distortion |tPHL – tPLH|
tsk(pp)
Part-to-part skew time
tsk(o)
Channel-to-channel output skew time
tr
Output signal rise time
tf
Output signal fall time
tfs
Fail-safe output delay time from input power loss
tui
Input pulse duration
7
1 / tui
Signaling rate
0
(1)
See Figure 1
See Figure 1
2
See Figure 2
UNIT
ns
2
ns
6
μs
ns
50
Mbps
Also known as pulse skew
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ELECTRICAL CHARACTERISTICS
VCC1 = VCC2 = 3.3 V ±5%, TA = –40°C to 125°C
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
TEST CONDITIONS
MIN
TYP
IOH = –4 mA, see Figure 1
VCC – 0.4
3
IOH = –20 μA, see Figure 1
VCC – 0.1
3.3
MAX
V
IOL = 4 mA, see Figure 1
0.2
0.4
IOL = 20 μA, see Figure 1
0
0.1
VI(HYS) Input threshold voltage hysteresis
400
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, see Figure 3.
μA
μA
–10
25
V
mV
10
IN from 0 V or VCC
UNIT
1
pF
40
kV/μs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic I CC measurement)
ICC1
DC to 1 Mbps
ICC2
ICC1
DC Input: VI = VCC or 0 V
1.8
2.8
AC Input: CL = 15 pF
1.8
2.8
2.2
3.2
2.2
3.2
2.8
4.1
2.8
4.1
3.8
5.8
3.8
5.8
TYP
MAX
12
20
ns
1
5
ns
10 Mbps
ICC2
Supply current for VCC1 and VCC2
ICC1
25 Mbps
ICC2
ICC1
CL = 15 pF
50 Mbps
ICC2
mA
SWITCHING CHARACTERISTICS
VCC1 = VCC2 = 3.3 V ± 5%, TA = –40°C to 125°C
PARAMETER
TEST CONDITIONS
MIN
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse duration distortion |tPHL – tPLH|
tsk(pp)
Part-to-part skew time
6.8
ns
tsk(o)
Channel-to-channel output skew time
5.5
ns
tr
Output signal rise time
tf
Output signal fall time
tfs
Fail-safe output delay time from input power loss
tui
Input pulse duration
7
1 / tui
Signaling rate
0
(1)
6
See Figure 1
UNIT
2
See Figure 1
See Figure 2
ns
2
ns
6
μs
ns
50
Mbps
Also known as pulse skew
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Isolation Barrier
PARAMETER MEASUREMENT INFORMATION
IN
Input
Generator
(1)
50 W
VI
VCC1
VI
OUT
1.4 V
1.4 V
0V
VO
CL
tPLH
(2)
tPHL
90%
10%
VCC/2
VO
VCC/2
VOH
VOL
tr
tf
S0412-01
(1)
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
(2)
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
VI
VCC1
VCC1
Isolation Barrier
0 V IN
or
VCC1
VI
2.7 V
0V
OUT
tfs
VO
VOH
CL
50%
VO
(1)
Fail-Safe HIGH
VOL
S0413-01
(1)
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 2. Fail-Safe Output Delay-Time Test Circuit and Voltage Waveforms
S1
IN
C = 0.1 mF ±1%
Isolation Barrier
VCC1
GND1
VCC2
C = 0.1 mF ±1%
Pass-fail criteria –
output must remain
stable.
OUT
+
VOH or VOL
GND2
(1)
–
+ VCM –
S0414-01
(1)
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 3. Common-Mode Transient Immunity Test Circuit
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DEVICE INFORMATION
PACKAGE CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
L(I01)
Minimum air gap (clearance)
Shortest terminal-to-terminal distance through air
4.8
mm
L(I02)
Minimum external tracking
(creepage)
Shortest terminal-to-terminal distance across the
package surface
4.3
mm
CTI
Tracking resistance (comparative
tracking index)
DIN IEC 60112 / VDE 0303 Part 1
>175
V
Minimum internal gap (internal
clearance)
Distance through the insulation
0.008
mm
RIO
Isolation resistance
CIO
Barrier capacitance, input to output
Input to output, VIO = 500 V, all pins on each side of
the barrier tied together creating a two-terminal device,
TA < 100°C
>1012
Input to output
>1011
Ω
1
pF
VI = 0.4 sin (4E6πt)
Ω
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance.
Creepage and clearance on a printed-circuit board become equal according to the
measurement techniques shown in the Isolation Glossary. Techniques such as inserting
grooves and/or ribs on a printed circuit board are used to help increase these
specifications.
INSULATION CHARACTERISTICS (1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIORM
Maximum working insulation voltage
VPR
Input-to-output test voltage
VIOTM
Transient overvoltage
VISO
Isolation voltage per UL
RS
Insulation resistance
t = 1 s (100% production), partial discharge 5 pC
t = 60 s (qualification)
t = 1 s (100% production)
UNIT
560
V
1050
V
4000
V
t = 60 s (qualification)
2500
t = 1 s (100% production)
3000
VIO = 500 V at TS
>109
Pollution degree
(1)
SPECIFICATION
Vrms
Ω
2
Climatic Classification 40/125/21
Table 2. IEC 60664-1 RATINGS TABLE
PARAMETER
Basic isolation group
Installation classification
8
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TEST CONDITIONS
SPECIFICATION
Material group
III-a
Rated mains voltage ≤ 150 Vrms
I–IV
Rated mains voltage ≤ 300 Vrms
I–III
Rated mains voltage ≤ 400 Vrms
I–II
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REGULATORY INFORMATION
VDE
CSA
UL
Certified according to IEC 60747-52
Approved under CSA Component
Acceptance Notice
Recognized under 1577 Component Recognition
Program (1)
File number: pending (40016131)
File number: pending (1698195)
File number: pending (E181974)
(1)
Production tested ≥ 3000 Vrms for 1 second in accordance with UL 1577.
LIFE EXPECTANCY versus WORKING VOLTAGE
Life Expectancy – Years
100
VIORM at 560 V
28 Years
10
0
120
250
500
750
880
1000
VIORM – Working Voltage – V
G001
Figure 4. Life Expectancy versus Working Voltage
IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
IS
Safety input, output, or supply
current
TS
Maximum case temperature
TEST CONDITIONS
MIN
TYP
MAX
θJA = 212°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C
112
θJA = 212°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C
171
150
UNIT
mA
°C
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum
Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Characteristics table is that of a device installed in the JESD51-3, Low-Effective-Thermal-Conductivity
Test Board for Leaded Surface-Mount Packages and is conservative. The power is the recommended maximum
input voltage times the current. The junction temperature is then the ambient temperature plus the power times
the junction-to-air thermal resistance.
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PACKAGE THERMAL CHARACTERISTICS
(over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
Junction-to-air thermal resistance
θJB
Junction-to-board thermal resistance
θJC
Junction-to-case thermal resistance
PD
(1)
212
122
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 150-Mbps 50% duty-cycle square wave
Device power dissipation
TYP
High-K thermal resistance (1)
Low-K thermal resistance
θJA
MIN
(1)
MAX
UNIT
°C/W
37
°C/W
69.1
°C/W
390
mW
Tested in accordance with the low-K or high-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages
200
Safety Limiting Current − mA
180
VCC1, VCC2 at 3.6 V
160
140
VCC1, VCC2 at 5.5 V
120
100
80
60
40
20
0
0
50
100
150
TC − Case Temperature − °C
200
G002
Figure 5. θJC Thermal Derating Curve per IEC 60747-5-2
VCC1
0.1mF
OUTPUT
INPUT
GND1
VCC2
2 mm
2 mm
max.
max.
ISO7421A-Q1
from
from
VCC1
VCC2
1
8
OUTA
INA
2
7
INB
OUTB
3
6
4
5
0.1mF
INPUT
OUTPUT
GND2
S0417-01
Figure 6. Typical ISO7421A-Q1 Application Circuit
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Input
VCC1
VCC1
VCC1
Output
VCC2
1 MW
8W
500 W
IN
OUT
13 W
S0422-01
Figure 7. Device I/O Schematics
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT
versus
SIGNAL RATE (ALL CHANNELS)
PROPAGATION DELAY TIME
versus
FREE-AIR TEMPERATURE
14
CL = 15 pF
TA = 25°C
18
16
tpd − Propagation Delay Time − ns
ICC1, ICC2 − Supply Current − mA
20
14
VCC1, VCC2 at 5 V
12
10
8
6
VCC1, VCC2 at 3.3 V
4
2
0
0
20
40
60
80
VCC1, VCC2 at 5 V
6
4
2
−35
−15
5
25
45
65
85
105
TA − Free-Air Temperature − °C
G003
125
G004
Figure 9.
INPUT VOLTAGE SWITCHING THRESHOLD
versus
FREE-AIR TEMPERATURE
FAIL-SAFE VOLTAGE THRESHOLD
versus
FREE-AIR TEMPERATURE
1.5
VIT+, 5 V
Fail-Safe Voltage Threshold − V
Input Voltage Switching Threshold − V
8
2.62
1.4
VIT+, 3.3 V
1.3
1.2
1.1
VIT−, 5 V
1.0
VIT−, 3.3 V
0.9
0.8
−55
−35
−15
5
25
45
65
85
105
TA − Free-Air Temperature − °C
2.61
FS+
2.60
2.59
2.58
2.57
2.56
2.55
FS−
2.54
2.53
2.52
−55
125
−35
−15
5
25
45
65
85
105
TA − Free-Air Temperature − °C
G005
125
G006
Figure 10.
Figure 11.
HIGH-LEVEL OUTPUT CURRENT
versus
HIGH-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT CURRENT
versus
LOW-LEVEL OUTPUT VOLTAGE
80
IOL − Low-Level Output Current − mA
0
IOH − High-Level Output Current − mA
10
Figure 8.
1.6
TA = 25°C
−10
−20
−30
−40
VCC1, VCC2 at 3.3 V
−50
−60
−70
VCC1, VCC2 at 5 V
−80
−90
TA = 25°C
70
60
VCC1, VCC2 at 5 V
50
40
VCC1, VCC2 at 3.3 V
30
20
10
0
0
1
2
3
4
VOH − High-Level Output Voltage − V
Figure 12.
12
VCC1, VCC2 at 3.3 V
0
−55
100 120 140 160 180 200
Signal Rate − Mbps
12
Submit Documentation Feedback
5
6
G007
0
1
2
3
4
VOL − Low-Level Output Voltage − V
5
6
G008
Figure 13.
Copyright © 2012–2013, Texas Instruments Incorporated
ISO7421A-Q1
www.ti.com
SLLSE14B – MARCH 2012 – REVISED SEPTEMBER 2013
TYPICAL CHARACTERISTICS (continued)
Figure 14. Eye Diagram at 250 MBPS, 5-V VCC, Typical
Copyright © 2012–2013, Texas Instruments Incorporated
Figure 15. Eye Diagram at 200 MBPS, 5-V VCC, 125°C
Submit Documentation Feedback
13
ISO7421A-Q1
SLLSE14B – MARCH 2012 – REVISED SEPTEMBER 2013
www.ti.com
REVISION HISTORY
Changes from Revision A (September 2012) to Revision B
Page
•
Deleted ISO7420-Q1 part number from header of every page ............................................................................................ 1
•
Deleted ISO7420-Q1package from pinout drawing .............................................................................................................. 1
•
Deleted ISO7420-Q1 part number from Description sectoin ................................................................................................ 1
•
Deleted ISO7420-Q1 from Ordering Information table ......................................................................................................... 1
•
Deleted ISO7420-Q1 from Pin Functions table .................................................................................................................... 2
•
Deleted ISO7420-Q1 from Supply Current section of 5-V, 5-V Electrical Characteristics table ........................................... 3
•
Deleted ISO7420-Q1 from Supply Current section of 5-V, 3.3-V Electrical Characteristics table ........................................ 4
•
............................................................................................................................................................................................... 5
•
Deleted ISO7420-Q1 from Supply Current section of 3.3-V, 5-V Electrical Characteristics table ........................................ 5
•
Deleted ISO7420-Q1 from Supply Current section of 3.3-V, 5-V Electrical Characteristics table ........................................ 6
•
Corrected part number in Typical Application Circuit diagram ........................................................................................... 10
Changes from Original (March, 2012) to Revision A
Page
•
Changed High Signaling Rate from 1 to 50 Mbps. ............................................................................................................... 1
•
Replaced Supply Current section with marked up table from commercial datasheet SLLSE45, 8.5 max value
changed to 9.1. ..................................................................................................................................................................... 3
•
Changed Signaling rate max value from 1 to 50. ................................................................................................................. 3
•
Replaced Supply Current section with marked up table from commercial datasheet SLLSE45, 8.5 max value
changed to 9.1 and 5.5 changed to 5.8. ............................................................................................................................... 4
•
Changed Signaling rate from 1 to 50 Mbps. ......................................................................................................................... 4
•
Replaced Supply Current section with marked up table from commercial datasheet SLLSE45, 5.5 max value
changed to 5.8 and 8.5 changed to 9.1. ............................................................................................................................... 5
•
Changed Signaling rate from 1 to 50 Mbps. ......................................................................................................................... 5
•
Replaced Supply Current section with marked up table from commercial datasheet SLLSE45, 5.5 max value
changed to 5.8. ..................................................................................................................................................................... 6
•
Changed Signaling rate from 1 to 50 Mbps. ......................................................................................................................... 6
14
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Copyright © 2012–2013, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
12-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
ISO7421AQDRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOIC
D
8
2500
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
CU NIPDAU
Level-3-260C-168 HR
(4/5)
-40 to 125
7421AQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ISO7421AQDRQ1
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO7421AQDRQ1
SOIC
D
8
2500
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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