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Texas Instruments Version B is the current version (Rev. C) Datasheet
Not Recommended for New Designs
ISO7230A
ISO7231A
SLLS906C – MAY 2008 – REVISED JUNE 2011
www.ti.com
One Megabit per Second Triple Digital Isolators
Check for Samples: ISO7230A, ISO7231A
FEATURES
1
•
•
•
•
•
1Mbps Signaling Rate
– Low Channel-to-Channel Output Skew;
2ns Maximum (5V-Operation)
– Low Pulse-Width Distortion (PWD);
10ns Maximum (5V-Operation)
Typical 25-Year Life at Rated Working Voltage
(See Application note SLLA197 and Figure 10)
4000Vpeak Isolation, 560Vpeak VIORM
– UL 1577, IEC 60747-5-2 (VDE 0884, Rev 2),
IE 61010-1 and CSA Approved, IEC 60950-1
4kV ESD Protection
Operate With 3.3V or 5V Supplies
•
•
High Electromagnetic Immunity
(See Application note SLLA181)
–40°C to 125°C Operating Range
APPLICATIONS
•
•
•
•
Industrial Fieldbus
Computer Peripheral Interface
Servo Control Interface
Data Acquisition
DESCRIPTION
See the Product Notification section. The ISO7230A and ISO7231A are triple-channel digital isolators each with
multiple channel configurations and output-enable functions. These devices have logic input and output buffers
separated by TI’s silicon dioxide (SiO2) isolation barrier. Used in conjunction with isolated power supplies, these
devices block high voltage, isolate grounds, and prevent noise currents on a data bus or other circuits from
entering the local ground and interfering with or damaging sensitive circuitry.
The ISO7230 triple-channel device has all three channels in the same direction while the ISO7231 has two
channels in one direction and one channel in opposition. These devices have an active-high output enable that
when driven to a low level, places the output in a high-impedance state.
The ISO7230A and ISO7231A have TTL input thresholds and a noise-filter at the input that prevents transient
pulses of up to 2ns in duration from being passed to the output of the device.
In each device a periodic update pulse is sent across the isolation barrier to ensure the proper dc level of the
output. If this dc-refresh pulse is not received, the input is assumed to be unpowered or not being actively driven,
and the failsafe circuit drives the output to a logic high state. (Contact TI for a logic low failsafe option).
These devices require two supply voltages of 3.3V, 5V, or any combination. All inputs are 5V tolerant when
supplied from a 3.3V supply and all outputs are 4mA CMOS. These devices are characterized for operation over
the ambient temperature range of –40°C to 125°C.
ISO7231
DW PACKAGE
ISO7230
DW PACKAGE
VCC1
GND1
INA
INB
INC
NC
NC
GND1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
GND2
OUTA
OUTB
OUTC
NC
EN
GND2
VCC1
GND1
INA
INB
OUTC
NC
EN1
GND1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
GND2
OUTA
OUTB
INC
NC
EN2
GND2
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2011, Texas Instruments Incorporated
Not Recommended for New Designs
ISO7230A
ISO7231A
SLLS906C – MAY 2008 – REVISED JUNE 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTION DIAGRAM
Galvanic Isolation
Barrier
DC Channel
Filter
OSC
+
PWM
Pulse Width
Demodulation
Vref
Carrier Detect
EN
IN
Input
+
Filter
Data MUX
AC Detect
Vref
OUT
Output Buffer
AC Channel
Table 1. Device Function Table ISO723x
INPUT VCC
PU
(1)
OUTPUT VCC
PU
(1)
INPUT
(IN)
OUTPUT ENABLE
(EN)
OUTPUT
(OUT)
H
H or Open
H
L
H or Open
L
X
L
Z
Open
H or Open
H
PD
PU
X
H or Open
H
PD
PU
X
L
Z
PU = Powered Up; PD = Powered Down ; X = Irrelevant; H = High Level; L = Low Level
AVAILABLE OPTIONS
PRODUCT
SIGNALING
RATE
INPUT
THRESHOLD
CHANNEL
CONFIGURATION
MARKED
AS
ISO7230ADW
1 Mbps
~1.5V (TTL)
(CMOS compatible)
3/0
ISO7230A
1 Mbps
~1.5 V (TTL)
(CMOS compatible)
2/1
ISO7231A
ISO7231ADW
(1)
2
ORDERING
NUMBER (1)
ISO7230ADW (rail)
ISO7230ADWR (reel)
ISO7231ADW (rail)
ISO7231ADWR (reel)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Copyright © 2008–2011, Texas Instruments Incorporated
Not Recommended for New Designs
ISO7230A
ISO7231A
SLLS906C – MAY 2008 – REVISED JUNE 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
UNIT
VCC
Supply voltage (2), VCC1, VCC2
–0.5 to 6
V
VI
Voltage at IN, OUT, EN
–0.5 to 6
V
IO
Output current
±15
mA
ESD
Electrostatic Field-Induced-Charged Device
discharge
Model
TJ
Maximum junction temperature
Human Body Model
Machine Model
(1)
(2)
±4
JEDEC Standard 22, Test Method A114-C.01
JEDEC Standard 22, Test Method C101
All pins
ANSI/ESDS5.2-1996
kV
±1
±200
V
170
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal and are peak voltage values.
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
VCC
Supply voltage (1), VCC1, VCC2
IOH
High-level output current
IOL
Low-level output current
tui
Input pulse width
1
1/tui
Signaling rate
0
VIH
High-level input voltage (IN) (EN on all devices)
2
VCC
VIL
Low-level input voltage (IN) (EN on all devices)
0
0.8
TJ
Junction temperature
H
External magnetic field-strength immunity per IEC 61000-4-8 and IEC 61000-4-9
certification
(1)
(2)
3.15
5.5
–4
UNIT
V
mA
4
mA
1000
kbps
μs
1500 (2)
V
150
°C
1000
A/m
For the 5V operation, VCC1 or VCC2 is specified from 4.5V to 5.5V.
For the 3V operation, VCC1 or VCC2 is specified from 3.15V to 3.6V.
Typical signaling rate under ideal conditions at 25°C.
Copyright © 2008–2011, Texas Instruments Incorporated
3
Not Recommended for New Designs
ISO7230A
ISO7231A
SLLS906C – MAY 2008 – REVISED JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5V (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VI = VCC or 0V, All channels, no load,
EN2 at 3V
1
3
1
3
VI = VCC or 0V, All channels, no load,
EN1 at 3V, EN2 at 3V
6.5
11
6.5
11
VI = VCC or 0V, All channels, no load,
EN2 at 3V
15
22
16
22
VI = VCC or 0V, All channels, no load,
EN1 at 3V, EN2 at 3V
13
20
13
20
UNIT
SUPPLY CURRENT
Quiescent
ISO7230A
1 Mbps
ICC1
Quiescent
ISO7231A
1 Mbps
Quiescent
ISO7230A
1 Mbps
ICC2
Quiescent
ISO7231A
1 Mbps
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at 0V, Single channel
VCC – 0.8
IOH = –20μA, See Figure 1
VCC – 0.1
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0V, See Figure 4
(1)
μA
0
IOH = –4mA, See Figure 1
V
IOL = 4mA, See Figure 1
0.4
IOL = 20μA, See Figure 1
0.1
150
mV
10
IN from 0V to VCC
–10
25
V
μA
2
pF
50
kV/μs
For the 5V operation, VCC1 or VCC2 is specified from 4.5V to 5.5V.
For the 3V operation, VCC1 or VCC2 is specified from 3.15V to 3.6V.
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
40
95
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
(1)
(2)
4
See Figure 1
(2)
10
0
See Figure 1
See Figure 2
See Figure 3
2
2
ns
ns
ns
2
12
UNIT
ns
μs
Also referred to as pulse skew.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2008–2011, Texas Instruments Incorporated
Not Recommended for New Designs
ISO7230A
ISO7231A
SLLS906C – MAY 2008 – REVISED JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 at 5V, VCC2 at 3.3V (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1
3
1
3
6.5
11
6.5
11
UNIT
SUPPLY CURRENT
ISO7230A
ICC1
ISO7231A
ISO7230A
ICC2
ISO7231A
Quiescent
1 Mbps
Quiescent
1 Mbps
Quiescent
1 Mbps
Quiescent
1 Mbps
VI = VCC or 0V, All channels, no load, EN2 at 3V
VI = VCC or 0V, All channels, no load, EN1 at 3V,
EN2 at 3V
VI = VCC or 0V, All channels, no load, EN2 at 3V
VI = VCC or 0V, All channels, no load, EN1 at 3V,
EN2 at 3V
9
15
9.5
15
8
12
8
12
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
VOH
High-level output voltage
EN at 0 V, Single channel
IOH = –4mA, See Figure 1
VCC – 0.4
ISO7231
(5-V side)
VCC – 0.8
IOH = –20μA, See Figure 1
V
VCC – 0.1
IOL = 4mA, See Figure 1
0.4
IOL = 20μA, See Figure 1
0.1
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient
immunity
VI = VCC or 0 V, See Figure 4
(1)
μA
0
ISO7230
150
mV
10
IN from 0V to VCC
V
–10
μA
2
pF
25
50
kV/μs
MIN
TYP MAX
40
100
For the 5-V operation, VCC1 or VCC2 is specified from 4.5V to 5.5V.
For the 3V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
SWITCHING CHARACTERISTICS: VCC1 at 5V, VCC2 at 3.3V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay, low-to-high-level output
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
(1)
(2)
(2)
ISO723xA
See Figure 1
ISO723xA
11
0
See Figure 1
See Figure 2
See Figure 3
2.5
2
ns
ns
ns
2
18
UNIT
ns
μs
Also known as pulse skew
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2008–2011, Texas Instruments Incorporated
5
Not Recommended for New Designs
ISO7230A
ISO7231A
SLLS906C – MAY 2008 – REVISED JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 at 3.3V, VCC2 at 5V (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.5
1
1
2
4.5
7
4.5
7
15
22
16
22
13
20
13
20
UNIT
SUPPLY CURRENT
Quiescent
ISO7230A
VI = VCC or 0V, All channels, no load, EN2 at 3V
1 Mbps
ICC1
Quiescent
ISO7231A
VI = VCC or 0V, All channels, no load, EN1 at 3V,
EN2 at 3V
1 Mbps
Quiescent
ISO7230A
VI = VCC or 0V, All channels, no load, EN2 at 3V
1 Mbps
ICC2
Quiescent
ISO7231A
VI = VCC or 0V, All channels, no load, EN1 at 3V,
EN2 at 3V
1 Mbps
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
VOH
EN at 0V, Single channel
IOH = –4mA, See Figure 1
High-level output voltage
VCC – 0.4
ISO7231
(5-V side)
VCC – 0.8
IOH = –20μA, See Figure 1
V
VCC – 0.1
IOL = 4mA, See Figure 1
0.4
IOL = 20μA, See Figure 1
0.1
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient
immunity
VI = VCC or 0V, See Figure 4
(1)
μA
0
ISO7230
150
mV
10
IN from 0V to VCC
–10
25
V
μA
2
pF
50
kV/μs
For 5V operation, VCC1 or VCC2 is specified from 4.5V to 5.5V.
For 3V operation, VCC1 or VCC2 is specified from 3.15V to 3.6V.
SWITCHING CHARACTERISTICS: VCC1 at 3.3V and VCC2 at 5V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
(1)
(2)
6
(2)
ISO723xA
See Figure 1
ISO723xA
40
MAX
tPLH, tPHL
100
11
0
See Figure 1
See Figure 2
See Figure 3
2.5
2
ns
ns
ns
2
12
UNIT
ns
μs
Also known as pulse skew
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2008–2011, Texas Instruments Incorporated
Not Recommended for New Designs
ISO7230A
ISO7231A
SLLS906C – MAY 2008 – REVISED JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3V (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VI = VCC or 0 V, all channels, no load,
EN2 at 3V
0.5
1
1
2
VI = VCC or 0V, all channels, no load,
EN1 at 3V, EN2 at 3V
4.5
7
4.5
7
UNIT
SUPPLY CURRENT
Quiescent
ISO7230A
1 Mbps
ICC1
Quiescent
ISO7231A
1 Mbps
Quiescent
ISO7230A
1 Mbps
ICC2
Quiescent
ISO7231A
1 Mbps
VI = VCC or 0V, all channels, no load,
EN2 at 3V
9
15
9.5
15
8
12
8
12
VI = VCC or 0V, all channels, no load,
EN1 at 3V, EN2 at 3V
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at 0V, single channel
VCC – 0.4
IOH = –20μA, See Figure 1
VCC – 0.1
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0V, See Figure 4
(1)
μA
0
IOH = –4mA, See Figure 1
V
IOL = 4mA, See Figure 1
0.4
IOL = 20μA, See Figure 1
0.1
150
mV
10
IN from 0V or VCC
–10
25
V
μA
2
pF
50
kV/μs
For 5V operation, VCC1 or VCC2 is specified from 4.5V to 5.5V.
For 3V operation, VCC1 or VCC2 is specified from 3.15V to 3.6V.
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
(1)
(2)
(2)
ISO723xA
See Figure 1
ISO723xA
45
MAX
tPLH, tPHL
110
12
0
See Figure 1
See Figure 2
See Figure 3
3
2
ns
ns
ns
2
18
UNIT
ns
μs
Also referred to as pulse skew.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2008–2011, Texas Instruments Incorporated
7
Not Recommended for New Designs
ISO7230A
ISO7231A
SLLS906C – MAY 2008 – REVISED JUNE 2011
www.ti.com
ISOLATION BARRIER
PARAMETER MEASUREMENT INFORMATION
IN
Input
Generator
VI
50 W
NOTE A
VCC
VI
VCC/2
VCC/2
OUT
0V
tPHL
tPLH
CL
NOTE B
VO
VO
VOH
90%
50%
50%
10%
tr
VOL
tf
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50kHz, 50% duty cycle, tr ≤
3ns, tf ≤ 3ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
Vcc
Vcc
ISOLATION BARRIER
RL = 1 kW ±1%
IN
0V
Input
Generator
VI
OUT
EN
Vcc/2
VI
t PZL
VO
VO
CL
Vcc/2
0V
t PLZ
Vcc
0.5 V
50%
NOTE
B
50 W
VOL
NOTE A
ISOLATION BARRIER
3V
Vcc
IN
Input
Generator
VI
OUT
VO
Vcc/2
VI
Vcc/2
0V
t PZH
EN
50 W
CL
NOTE
B
RL = 1 kW ±1%
VO
VOH
50%
0.5 V
t PHZ
0V
NOTE A
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50kHz, 50% duty cycle, tr ≤
3ns, tf ≤ 3ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 2. Enable/Disable Propagation Delay Time Test Circuit and Waveform
8
Copyright © 2008–2011, Texas Instruments Incorporated
Not Recommended for New Designs
ISO7230A
ISO7231A
SLLS906C – MAY 2008 – REVISED JUNE 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
VCC
0V
or
VCC
IN
ISOLATION BARRIER
VI
VCC
OUT
VI
2.7 V
VO
0V
VOH
tfs
CL
NOTE B
VO
50%
VOL
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50kHz, 50% duty cycle, tr ≤
3ns, tf ≤ 3ns, ZO = 50Ω.
B.
CL = 15pF and includes instrumentation and fixture capacitance within ±20%.
Figure 3. Failsafe Delay Time Test Circuit and Voltage Waveforms
VCC2
VCC1
S1
IN
ISOLATION BARRIER
C = 0.1 mF± 1%
GND1
C = 0.1 mF± 1%
OUT
NOTE B
Pass-fail criteria:
Output must
remain stable
VOH or VOL
GND2
VCM
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50kHz, 50% duty cycle, tr ≤
3ns, tf ≤ 3ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 4. Common-Mode Transient Immunity Test Circuit and Voltage Waveform
Copyright © 2008–2011, Texas Instruments Incorporated
9
Not Recommended for New Designs
ISO7230A
ISO7231A
SLLS906C – MAY 2008 – REVISED JUNE 2011
www.ti.com
DEVICE INFORMATION
PACKAGE CHARACTERISTICS
PARAMETER
L(I01)
L(I02)
RIO
TEST CONDITIONS
MIN
TYP MAX
UNIT
Minimum air gap (Clearance)
Shortest terminal-to-terminal distance through air
8.34
mm
Minimum external tracking (Creepage)
Shortest terminal-to-terminal distance across the
package surface
8.1
mm
Minimum Internal Gap (Internal
Clearance)
Distance through the insulation
0.008
mm
Isolation resistance
Input to output, VIO = 500V, all pins on each side of the
barrier tied together creating a two-terminal device,
TA < 100°C
>1012
Input to output, VIO = 500V, 100°C ≤ TA ≤ TA max
>1011
Ω
Ω
CIO
Barrier capacitance Input to output
VI = 0.4 sin (4E6πt)
2
pF
CI
Input capacitance to ground
VI = 0.4 sin (4E6πt)
2
pF
REGULATORY INFORMATION
VDE
CSA
UL
Certified according to IEC
60747-5-2
Approved under CSA Component
Acceptance Notice
Recognized under 1577
Component Recognition
Program (1)
File Number: 40016131
File Number: 220991
File Number: E181974
(1)
Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
DEVICE I/O SCHEMATICS
Enable
VCC2
VCC2
VCC1
VCC2
1 MW
VCC1
VCC1
VCC2
1 MW
500 W
EN
Output
Input
IN
500 W
8W
OUT
13 W
10
Copyright © 2008–2011, Texas Instruments Incorporated
Not Recommended for New Designs
ISO7230A
ISO7231A
SLLS906C – MAY 2008 – REVISED JUNE 2011
www.ti.com
THERMAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Low-K Thermal Resistance
θJA
Junction-to-air
θJB
Junction-to-Board Thermal Resistance
θJC
Junction-to-Case Thermal Resistance
PD
(1)
MIN
TYP MAX
(1)
168
High-K Thermal Resistance
°C/W
96.1
61
°C/W
48
°C/W
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 50% duty cycle square wave
Device Power Dissipation
UNIT
220
mW
Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.
TYPICAL CHARACTERISTIC CURVES
INPUT THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
VCC1 FAILSAFE THRESHOLD
vs
FREE-AIR TEMPERATURE
1.4
3
5 V Vth+
2.9
VCC1 - Failsafe Threshold - V
Input Voltage Threshold - V
1.35
1.3
3.3 V Vth+
1.25
1.2
Air Flow at 7 cf/m,
Low-K Board
1.15
5 V Vth1.1
2.8
VCC at 5 V or 3.3 V,
Load = 15 pF,
Air Flow at 7/cf/m,
Low-K Board
2.7
Vfs+
2.6
2.5
Vfs-
2.4
2.3
2.2
1.05
3.3 V Vth1
-40
-25
-10
2.1
5
20
35
50
65
80
TA - Free-Air Temperature - °C
95
110
2
-40
125
-10
5
20
35
50
65
80
95
110
125
TA - Free-Air Temperature - °C
Figure 5.
Figure 6.
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50
50
VCC = 5 V
Load = 15 pF,
TA = 25°C
Load = 15 pF,
TA = 25°C
45
40
IO - Output Current - mA
40
IO - Output Current - mA
-25
VCC = 3.3 V
30
20
35
VCC = 3.3 V
30
25
VCC = 5 V
20
15
10
10
5
0
0
0
2
4
VO - Output Voltage - V
Figure 7.
Copyright © 2008–2011, Texas Instruments Incorporated
6
0
1
2
3
VO - Output Voltage - V
4
5
Figure 8.
11
Not Recommended for New Designs
ISO7230A
ISO7231A
SLLS906C – MAY 2008 – REVISED JUNE 2011
www.ti.com
APPLICATION INFORMATION
2 mm
max. from
VCC1
VCC1
2 mm
max. from
VCC2
VCC2
0.1 mF
0.1 mF
1
16
2
15
IN A
3
14
OUT A
IN B
4
13
OUT B
IN C
5
12
OUT C
NC
6
11
NC
7
10
8
9
GND2
GND1
NC
EN
GND2
GND1
ISO7230
Figure 9. Typical ISO7230 Application Circuit
LIFE EXPECTANCY vs WORKING VOLTAGE
WORKING LIFE -- YEARS
100
VIORM at 560-V
28 Years
10
0
120
250
500
750
880
1000
WORKING VOLTAGE (VIORM) -- V
Figure 10. Time Dependant Dielectric Breakdown Testing Results
12
Copyright © 2008–2011, Texas Instruments Incorporated
Not Recommended for New Designs
ISO7230A
ISO7231A
SLLS906C – MAY 2008 – REVISED JUNE 2011
www.ti.com
PRODUCT NOTIFICATION
An ISO723xA anomaly occurs when a negative-going pulse below the specified 1μs minimum bit width is input to
the device. The output locks in a logic-low condition until the next rising edge occurs after a 1μs period.
Positive noise edges in pulses of less than the minimum specified 1μs have no effect on the device, and are
properly filtered.
To prevent noise from interfering with ISO723xA performance, it is recommended that an appropriately sized
capacitor be placed on each input of the device
Figure 11. ISO723xA Anomaly
Copyright © 2008–2011, Texas Instruments Incorporated
13
Not Recommended for New Designs
ISO7230A
ISO7231A
SLLS906C – MAY 2008 – REVISED JUNE 2011
www.ti.com
REVISION HISTORY
Changes from Original (May 2008) to Revision A
Page
•
Added Product Notification section link. ............................................................................................................................... 1
•
Deleted text from paragraph 2 of the Description: "and turns off internal bias circuitry to conserve power" ....................... 1
•
Deleted Product Preview note .............................................................................................................................................. 2
•
Changed From: 3 To: 3.15 .................................................................................................................................................... 3
•
Changed VCC From: 3.6 To: 3.45 .......................................................................................................................................... 3
•
Changed ICC1 and ICC2 values From: TBD ............................................................................................................................. 4
•
Changed VCC – 0.4 To: VCC – 0.8 ......................................................................................................................................... 4
•
Changed Typical value from 1 To: 2 ..................................................................................................................................... 4
•
Changed Propagation delay max From: 80 To: 95 .............................................................................................................. 4
•
Changed ICC1 and ICC2 values From: TBD ............................................................................................................................. 5
•
Changed Typical value from 1 To: 2 ..................................................................................................................................... 5
•
Changed Propagation delay max From: 80 To: 100 ............................................................................................................ 5
•
Changed ICC1 and ICC2 values From: TBD ............................................................................................................................. 6
•
Changed Typical value from 1 To: 2 ..................................................................................................................................... 6
•
Changed Propagation delay max From: 80 To: 100 ............................................................................................................ 6
•
Changed ICC1 and ICC2 values From: TBD ............................................................................................................................. 7
•
Changed ............................................................................................................................................................................... 7
•
Changed Typical value from 1 To: 2 ..................................................................................................................................... 7
•
Changed Propagation delay max From: 85 To: 110 ............................................................................................................ 7
•
Changed L(101) Minimum air gap (Clearance) - minimum value from: 7.7mm to: 8.34mm .............................................. 10
•
Changed Typical value from 1 To: 2 ................................................................................................................................... 10
•
Changed Typical value from 1 To: 2 ................................................................................................................................... 10
•
Changed the REGULATORY INFORMATION Table ......................................................................................................... 10
•
Changed Figure 11 ............................................................................................................................................................. 13
Changes from Revision A (June 2008) to Revision B
•
Page
Changed VCC From: 3.45 To: 3.6 .......................................................................................................................................... 3
Changes from Revision B (July 2008) to Revision C
Page
•
Changed "1ns" to "2ns", added "(5v-Operation)" .................................................................................................................. 1
•
Changed "2ns" to "10ns", added "(5v-Operation)" ................................................................................................................ 1
•
Deleted "Low Jitter Content; 1 ns Typ at 150 Mbps" ............................................................................................................ 1
•
Deleted Min = 4.5 V and max = 5.5 V for Supply Voltage of the ROC Table. ..................................................................... 3
•
Changed VCC From: 3.6 To: 5.5 ............................................................................................................................................ 3
•
Corrected Figure 1 ................................................................................................................................................................ 8
•
Changed File number "1698195" to "220991" .................................................................................................................... 10
•
Corrected DEVICE I/O SCHEMATICS ............................................................................................................................... 10
•
Corrected Figure 9 .............................................................................................................................................................. 12
14
Copyright © 2008–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO7230ADW
NRND
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7230A
ISO7230ADWG4
NRND
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7230A
ISO7230ADWR
NRND
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7230A
ISO7231ADW
NRND
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7231A
ISO7231ADWR
NRND
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7231A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ISO7230ADWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7231ADWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO7230ADWR
SOIC
DW
16
2000
350.0
350.0
43.0
ISO7231ADWR
SOIC
DW
16
2000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DW 16
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
B
7.6
7.4
NOTE 4
2.65 MAX
B
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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