Texas Instruments | 3.3-V / 5-V High-Speed Digital Isolators | Datasheet | Texas Instruments 3.3-V / 5-V High-Speed Digital Isolators Datasheet

Texas Instruments 3.3-V / 5-V High-Speed Digital Isolators Datasheet
ISO721M-EP
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3.3-V/5-V HIGH-SPEED DIGITAL ISOLATORS
FEATURES
1
• Controlled Baseline
– One Assembly Site
– One Test Site
– One Fabrication Site
• Extended Temperature Performance of
–55°C to 125°C
• Enhanced Diminishing Manufacturing Sources
(DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree (1)
• 4000-V(peak) Isolation
– UL 1577, IEC 60747-5-2 (VDE 0884, Rev. 2)
IEC 61010-1
– 50-kV/µs Transient Immunity Typical
•
23
(1)
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
•
•
•
•
•
Signaling Rate 0 Mbps to 150 Mbps
– Low Propagation Delay
– Low Pulse Skew (Pulse-Width Distortion)
Low-Power Sleep Mode
High Electromagnetic Immunity
Low Input Current Requirement
Failsafe Output
Drop-In Replacement for Most Opto and
Magnetic Isolators
APPLICATIONS
•
•
•
•
Industrial Fieldbus
– Modbus
– Profibus
– DeviceNet™ Data Buses
– Smart Distributed Systems (SDS™)
Computer Peripheral Interface
Servo Control Interface
Data Acquisition
DESCRIPTION/ORDER INFORMATION
The ISO721, ISO721M, ISO722, and ISO722M are digital isolators with a logic input and output buffer separated
by a silicon oxide (SiO2) insulation barrier. This barrier provides galvanic isolation of up to 4000 V. Used in
conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits
from entering the local ground, and interfering with or damaging sensitive circuitry.
A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation
barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or
resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure
the proper dc level of the output. If this dc-refresh pulse is not received for more than 4 µs, the input is assumed
to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SDS is a trademark of Honeywell.
DeviceNet is a trademark of Open Devicenet Vendors Association, Inc.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
ISO721M-EP
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTION DIAGRAM
DC Channel
Isolation Barrier
+
_
OSC
+
PWM
Vref
_
+
POR
BIAS
Filter
Pulse Width
Demodulation
Carrier Detect
POR
ISO722
Only
IN
Input
+
Filter
+
_
Vref
_
Data MUX
AC Detect
3-State
Output Buffer
EN
OUT
+
AC Channel
The symmetry of the dielectric and capacitor within the integrated circuitry provides for close capacitive matching,
and allows fast transient voltage changes between the input and output grounds without corrupting the output.
The small capacitance and resulting time constant provide for fast operation with signaling rates (2) from 0 Mbps
(dc) to 100 Mbps for the ISO721/ISO722, and 0 Mbps to 150 Mbps with the ISO721M/ISO722M.
These devices require two supply voltages of 3.3 V, 5 V, or any combination. All inputs are 5-V tolerant when
supplied from a 3.3-V supply and all outputs are 4-mA CMOS.
The ISO721 has TTL input thresholds and a noise-filter at the input that prevents transient pulses of up to 2 ns in
duration from being passed to the output of the device.
The ISO721M has CMOS VCC/2 input thresholds, but do not have the noise filter and the additional propagation
delay. These features of the ISO721M also provide for reduced jitter operation.
The ISO721M is characterized for operation over the ambient temperature range of –55°C to 125°C.
(2)
2
The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
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IN 2
VCC1 3
8 VCC2
Isolation
VCC1 1
D PACKAGE
ISO722, ISO722M
(TOP VIEW)
VCC1 1
7 GND2
IN 2
VCC1 3
6 OUT
GND1 4
5 GND2
GND1 4
Isolation
D PACKAGE
ISO721, ISO721M
(TOP VIEW)
8 VCC2
7 EN
6 OUT
5 GND2
AVAILABLE OPTIONS (1)
PRODUCT (2)
OUTPUT
ENABLED
INPUT
THRESHOLDS
NOISE
FILTER
PACKAGE
ISO721 (3)
ISO721M
NO
TTL
YES
SOIC-8
-
-
NO
CMOS
NO
SOIC-8
721MEP
ISO721MMDREP (reel)
ISO722 (3)
YES
TTL
YES
SOIC-8
-
-
ISO722M (3)
YES
CMOS
NO
SOIC-8
-
-
(1)
(2)
(3)
TOP-SIDE
MARKING
ORDERING NUMBER
GREEN
Pb Free
Sb/Br Free
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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REGULATORY INFORMATION
VDE
CSA
UL
Certified according to IEC 60747-5-2
Approved under CSA Component
Acceptance Notice: CA-5A
Recognized under 1577
Component Recognition Program (1)
File Number: 40014131
File Number: 1698195
File Number: E181974
(1)
Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
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ABSOLUTE MAXIMUM RATINGS (1)
UNIT
(2)
VCC
Supply voltage
VI
Voltage at IN, OUT, or EN terminal
IO
Output Current
ESD
Electrostatic
discharge
TJ
Maximum junction temperature
(1)
(2)
, VCC1, VCC2
–0.5 V to 6 V
–0.5 V to 6 V
±15 mA
Human-Body Model
JEDEC Standard 22, Test Method A114-C.01
Charged-Device Model
JEDEC Standard 22, Test Method C101
±2 kV
All pins
±1 kV
170°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values. Vrms
values are not listed in this publication.
RECOMMENDED OPERATING CONDITIONS
MIN
VCC
Supply voltage, VCC1, VCC2
IOH
High-level output current
IOL
Low-level output current
tui
Input pulse width
VIH
High-level input voltage (IN, EN)
VIL
Low-level input voltage (IN, EN)
VIH
High-level input voltage (IN, EN)
VIL
Low-level input voltage (IN, EN)
TJ
Junction temperature
H
External magnetic field intensity per IEC 61000-4-8 and IEC 61000-4-9
certification
TYP
MAX
4.5
5.5
3
3.6
4
UNIT
V
mA
-4
ISO72x
10
ISO72xM
ns
6.67
ISO72x
IOS72xM
2
VCC
0
0.8
0.7 VCC
VCC
0
0.3 VCC
See the Thermal Characteristics table
V
V
150
°C
1000
A/m
SPECIFICATIONS
UNIT
560
V
After Input/Output Safety Test Subgroup 2/3
VPR = VIORM × 1.2, t = 10 s,
Partial discharge < 5 pC
672
V
Method a, VPR = VIORM × 1.6,
Type and sample test with t = 10 s,
Partial discharge < 5 pC
896
V
Method b1, VPR = VIORM × 1.875,
100 % Production test with t = 1 s,
Partial discharge < 5 pC
1050
V
IEC 60747-5-2 INSULATION CHARACTERISTICS (1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
VIORM
VPR
TEST CONDITIONS
Maximum working insulation voltage
Input to output test voltage
VIOTM
Transient overvoltage
t = 60 s
4000
V
RS
Insulation resistance
VIO = 500 V at TS
>109
Ω
Pollution degree
(1)
4
2
Climatic Classification 40/125/21
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ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 5 V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Quiescent
ICC1
VCC1 supply current
ICC2
VCC2 supply current
VOH
High-level output voltage
VOL
Low-level output voltage
MIN
VI = VCC or 0 V, No load
25 Mbps
TYP
MAX
0.5
1
2
4
Quiescent
VI = VCC or 0 V, No load
8
12
25 Mbps
VI = VCC or 0 V, No load
10
14
IOH = -4 mA, See Figure 1
VCC – 0.8
4.6
IOH = –20 µA, See Figure 1
VCC – 0.1
5
mA
mA
V
IOL = 4 mA, See Figure 1
0.2
0.4
IOL = 20 µA, See Figure 1
0
0.1
VI(HYS) Input voltage hysteresis
UNIT
V
150
IIH
High-level input current
IN at 2 V
IIL
Low-level input current
IN at 0.8 V
IOZ
High-impedance output
current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
ISO722, ISO722M
mV
10
µA
–10
EN, IN at VCC
µA
1
25
1
pF
50
kV/µs
SWITCHING CHARACTERISTICS: VCC1 and VCC2 5 V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay , high-to-low-level output
tsk(p)
Pulse skew |tPHL – tPLH|
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay, high-to-low-level output
tsk(p)
Pulse skew |tPHL – tPLH|
tsk(pp) (1)
Part-to-part skew
tr
Output signal rise time
tf
Output signal fall time
tpHZ
Sleep-mode propagation delay,
high-level-to-high-mpedance output
tpZH
Sleep-mode propagation delay,
high-impedance-to-high-level output
tpLZ
Sleep-mode propagation delay,
low-level-to-high-impedance output
UNIT
ISO72x
17
ns
0.5
EN at 0 V,
See Figure 1
2
ISO721M
2
10
16
10
16
0.5
1
1
1
ns
ns
8
ns
4
µs
8
ns
5
µs
3
µs
See Figure 2
ISO722
ISO722M
See Figure 3
tfs
Failsafe output delay time from input power loss
ISO72x
See Figure 4
100 Mbps NRZ data input, See Figure 6
2
100 Mbps unrestricted bit run length data
input, See Figure 6
3
150 Mbps NRZ data input, See Figure 6
1
ISO72xM 150 Mbps unrestricted bit run length data
input, See Figure 6
(1)
MAX
17
EN at 0 V,
See Figure 1
Sleep-mode propagation delay,
high-impedance-to-low-level output
Peak-to-peak eye-pattern jitter
TYP
3
tpZL
tjit(PP)
MIN
ns
2
tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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ELECTRICAL CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Quiescent
ICC1
VCC1 supply current
ICC2
VCC2 supply current
VOH
High-level output voltage
VOL
Low-level output voltage
MIN
VI = VCC or 0 V, No load
25 Mbps
TYP
MAX
0.5
1
2
4
Quiescent
VI = VCC or 0 V, No load
4
6.5
25 Mbps
VI = VCC or 0 V, No load
5
7.5
IOH = –4 mA, See Figure 1
VCC – 0.4
3
IOH = –20 µA, See Figure 1
VCC – 0.1
3.3
mA
mA
V
IOL = 4 mA, See Figure 1
0.2
0.4
IOL = 20 µA, See Figure 1
0
0.1
VI(HYS) Input voltage hysteresis
UNIT
V
150
IIH
High-level input current
IN at 2 V
IIL
Low-level input current
IN at 0.8 V
IOZ
High-impedance output
current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
ISO722, ISO722M
mV
10
µA
–10
EN, IN at VCC
µA
1
1
pF
25
40
kV/µs
MIN
TYP
SWITCHING CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay , high-to-low-level output
tsk(p)
Pulse skew |tPHL – tPLH|
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay, high-to-low-level output
tsk(p)
Pulse skew |tPHL – tPLH|
tsk(pp) (1)
Part-to-part skew
tr
Output signal rise time
tf
Output signal fall time
tpHZ
Sleep-mode propagation delay,
high-level-to-high-mpedance output
tpZH
Sleep-mode propagation delay,
high-impedance-to-high-level output
tpLZ
Sleep-mode propagation delay,
low-level-to-high-impedance output
19
EN at 0 V,
See Figure 1
3
ISO721M
3
12
20
12
20
0.5
1
2
2
ISO722
ISO722M
ns
ns
11
ns
6
µs
13
ns
6
µs
3
µs
See Figure 3
Failsafe output delay time from input power loss
ISO72x
See Figure 4
100 Mbps NRZ data input, See Figure 6
2
100 Mbps unrestricted bit run length data
input, See Figure 6
3
150 Mbps NRZ data input, See Figure 6
1
ISO72xM 150 Mbps unrestricted bit run length data
input, See Figure 6
6
ns
See Figure 2
tfs
(1)
UNIT
0.5
EN at 0 V,
See Figure 1
Sleep-mode propagation delay,
high-impedance-to-low-level output
Peak-to-peak eye-pattern jitter
ISO72x
5
tpZL
tjit(PP)
MAX
19
ns
2
tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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ELECTRICAL CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Quiescent
ICC1
VCC1 supply current
ICC2
VCC2 supply current
VOH
High-level output voltage
VOL
Low-level output voltage
MIN
VI = VCC or 0 V, No load
25 Mbps
TYP
MAX
0.3
0.5
1
2
Quiescent
VI = VCC or 0 V, No load
8
12
25 Mbps
VI = VCC or 0 V, No load
10
14
IOH = –4 mA, See Figure 1
VCC – 0.8
4.6
IOH = –20 µA, See Figure 1
VCC – 0.1
5
mA
mA
V
IOL = 4 mA, See Figure 1
0.2
0.4
IOL = 20 µA, See Figure 1
0
0.1
VI(HYS) Input voltage hysteresis
UNIT
V
150
IIH
High-level input current
IN at 2 V
IIL
Low-level input current
IN at 0.8 V
IOZ
High-impedance output
current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
ISO722, ISO722M
mV
10
µA
–10
EN, IN at VCC
µA
1
25
1
pF
40
kV/µs
SWITCHING CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay , high-to-low-level output
tsk(p)
Pulse skew |tPHL – tPLH|
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay, high-to-low-level output
tsk(p)
Pulse skew |tPHL – tPLH|
tsk(pp) (1)
Part-to-part skew
tr
Output signal rise time
tf
Output signal fall time
tpHZ
Sleep-mode propagation delay,
high-level-to-high-mpedance output
tpZH
Sleep-mode propagation delay,
high-impedance-to-high-level output
tpLZ
Sleep-mode propagation delay,
low-level-to-high-impedance output
ISO72x
UNIT
17
ns
0.5
EN at 0 V,
See Figure 1
3
ISO721M
3
12
21
12
21
0.5
1
0
5
1
1
ISO722
ISO722M
ns
ns
9
ns
5
µs
9
ns
5
µs
3
µs
See Figure 3
tfs
Failsafe output delay time from input power loss
ISO72x
See Figure 4
100 Mbps NRZ data input, See Figure 6
2
100 Mbps unrestricted bit run length data
input, See Figure 6
3
150 Mbps NRZ data input, See Figure 6
1
ISO72xM 150 Mbps unrestricted bit run length data
input, See Figure 6
(1)
MAX
See Figure 2
Sleep-mode propagation delay,
high-impedance-to-low-level output
Peak-to-peak eye-pattern jitter
TYP
17
EN at 0 V,
See Figure 1
tpZL
tjit(PP)
MIN
ns
2
tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Quiescent
ICC1
VCC1 supply current
ICC2
VCC2 supply current
VOH
High-level output voltage
VOL
Low-level output voltage
MIN
VI = VCC or 0 V, No load
25 Mbps
TYP
MAX
0.3
0.5
1
2
Quiescent
VI = VCC or 0 V, No load
4
6.5
25 Mbps
VI = VCC or 0 V, No load
5
7.5
IOH = –4 mA, See Figure 1
VCC – 0.4
3
IOH = –20 µA, See Figure 1
VCC – 0.1
3.3
mA
mA
V
IOL = 4 mA, See Figure 1
0.2
0.4
IOL = 20 µA, See Figure 1
0
0.1
VI(HYS) Input voltage hysteresis
UNIT
V
150
IIH
High-level input current
IN at 2 V
IIL
Low-level input current
IN at 0.8 V
IOZ
High-impedance output
ISO722, ISO722M
current
EN, IN at VCC
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
mV
10
µA
–10
µA
1
25
1
pF
40
kV/µs
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 3.3 V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay , high-to-low-level output
tsk(p)
Pulse skew |tPHL – tPLH|
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay, high-to-low-level output
tsk(p)
Pulse skew |tPHL – tPLH|
tsk(pp) (1)
Part-to-part skew
tr
Output signal rise time
tf
Output signal fall time
tpHZ
Sleep-mode propagation delay,
high-level-to-high-mpedance output
tpZH
Sleep-mode propagation delay,
high-impedance-to-high-level output
tpLZ
Sleep-mode propagation delay,
low-level-to-high-impedance output
ISO72x
20
ns
0.5
EN at 0 V,
See Figure 1
3
ISO721M
3
12
25
12
25
0.5
1
2
2
ISO722
ISO722M
ns
ns
13
ns
6
µs
13
ns
6
µs
3
µs
See Figure 3
Failsafe output delay time from input power loss
ISO72x
See Figure 4
100 Mbps NRZ data input, See Figure 6
2
100 Mbps unrestricted bit run length data
input, See Figure 6
3
150 Mbps NRZ data input, See Figure 6
1
ISO72xM 150 Mbps unrestricted bit run length data
input, See Figure 6
8
UNIT
See Figure 2
tfs
(1)
MAX
20
EN at 0 V,
See Figure 1
Sleep-mode propagation delay,
high-impedance-to-low-level output
Peak-to-peak eye-pattern jitter
TYP
5
tpZL
tjit(PP)
MIN
ns
2
tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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ISOLATION BARRIER
PARAMETER MEASUREMENT INFORMATION
IN
Input
Generator
NOTE A
+
VI
50 W
-
VCC1
IO
OUT
VCC1/2
VI
0V
EN
tPHL
VOH
tPLH
+
ISO722
and
ISO722M
VCC1/2
CL
Note B
VO
-
90%
50%
VO
50%
10%
VOL
tf
tr
ISOLATION BARRIER
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
IN
3V
Input
Generator
NOTE A
VO
OUT
VCC2
VI
VCC2/2
0V
EN
RL = 1 kW ±1 %
CL
NOTE B
+
tPZH
VOH
50%
VO
VI
VCC2/2
50 W
0.5 V
0V
tPHZ
-
Figure 2. ISO722 Sleep-Mode High-Level Output Test Circuit and Voltage Waveforms
ISOLATION BARRIER
VCC2
IN
0V
Input
Generator
NOTE A
RL = 1 kW ±1%
OUT
EN
CL
NOTE B
+
VI
VCC2
VI
VO
VCC2/2
0V
tPZL
VO
VCC2/2
tPLZ
50%
VCC2
0.5 V
VOL
50 W
-
A.
The input pulse is supplied by a generator having the following characteristics:
PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 3. ISO722 Sleep-Mode Low-Level Output Test Circuit and Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
VCC1
0V
IN
ISOLATION BARRIER
VI
VCC1
VI
OUT
VO
ISO722
and
ISO722M
0V
tfs
VOH
50%
VO
CL
15 pF
±20%
EN
2.7 V
VOL
NOTE: VI transition time is 100 ns
VCC1
IN
VCC
or
0V
CI = 0.1 mF,
GND1
ISOLATION BARRIER
Figure 4. Failsafe Delay Time Test Circuit and Voltage Waveforms
VCC2
OUT
GND2
±1%
CL
15 pF
±20%
VO
VCM
NOTE: Pass/Fail criteria is no change in VO.
Figure 5. Common-Mode Transient Immunity Test Circuit and Voltage Waveform
10
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PARAMETER MEASUREMENT INFORMATION (continued)
Tektronix
HFS9009
Tektronix
784D
PATTERN
GENERATOR
VCC1
In p u t
0V
O u tp u t
VCC2/2
J itte r
NOTE: Bit pattern run length is 216 – 1. Transition Time is 800 ps. NRZ data input has no more than five consecutive
ones or zeros.
Figure 6. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
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DEVICE INFORMATION
PACKAGE CHARACTERISTICS
PARAMETER
TEST CONDITIONS
L(101) Minimum air gap (Clearance)
(1)
L(102) Minimum external tracking (Creepage)
CTI
RIO
MIN
TYP
MAX
UNIT
Shortest terminal to terminal distance through air
4.8
mm
Shortest terminal to terminal distance across the
package surface
4.3
mm
Tracking resistance (comparative tracking
index)
DIN IEC 60112/VDE 0303 Part 1
≥ 175
V
Minimum internal gap (internal clearance)
Distance through insulation
0.008
mm
>1012
Ω
Isolation resistance
Input to output, VIO = 500 V, all pins on each side
of the barrier tied together creating a two-terminal
device, TA < 100 °C
Input to output, VIO = 500 V,
100°C ≤ TA< TA max.
>1011
Ω
CIO
Barrier capacitance
Input-to-output
VI = 0.4 sin (4E6πt)
1
pF
CI
Input capacitance to ground
VI = 0.4 sin (4E6πt)
1
pF
(1)
Creepage and clearance requirements are applied according to the specific equipment isolation standards of an application. Care should
be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the
printed circuit board do not reduce this distance.
Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation
Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
IEC 60664-1 RATINGS TABLE
PARAMETER
TEST CONDITIONS
Basic isolation group
Installation classification
SPECIFICATION
Material group
IIIa
Rated mains voltage ≤150 VRMS
I-IV
Rated mains voltage ≤300 VRMS
I-III
DEVICE I/O SCHEMATIC
Equivalent Input and Output Schematic Diagrams
Input
Enable
Output
VCC2
VCC2
VCC1
VCC2
VCC1
1 MW
8W
OUT
500 W
500 W
EN
IN
13 W
1 MW
12
VCC1
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IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the IO can allow low resistance to ground or the supply, and without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system
failures.
PARAMETER
TEST CONDITIONS
IS
Safety input, output, or supply current
TS
Maximum case temperature
MIN
TYP
MAX
θJA = 263°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C
100
θJA = 263°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C
153
150
UNIT
mA
°C
The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum
ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The junction-to-air thermal resistance in the Thermal
Characteristics table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board
for Leaded Surface Mount Packages and is conservative. The power is the recommended maximum input
voltage times the current. The junction temperature is then the ambient temperature plus the power times the
junction-to-air thermal resistance.
THERMAL CHARACTERISTICS
(over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Low-K Thermal Resistance (1)
263
°C/W
High-K Thermal Resistance (1)
θJA
Junction-to-Air
125
°C/W
θJB
Junction-to-Board Thermal
Resistance
44
°C/W
θJC
Junction-to-Case Thermal
Resistance
75
°C/W
VCC1 = VCC2 = 5.5 V, TJ = 150°C,
CL = 15 pF, Input a 100 Mbps 50% duty
cycle square wave
159
VCC1 = VCC2 = 5.5 V, TJ = 150°C,
ISO72xM CL = 15 pF, Input a 150 Mbps 50% duty
cycle square wave
195
ISO72x
PD
(1)
Device Power Dissipation
mW
Tested in accordance with the Low-K or High-K thermal metric definition of EIA/JESD51-3 for leaded surface mount packages.
200
Safety Limiting Current − mA
175
VCC1, VCC2 = 3.6 V
150
125
100
75
VCC1, VCC2 = 5.5 V
50
25
0
0
50
100
150
200
o
Case Temperature − C
Figure 7. θJC THERMAL DERATING CURVE per IEC 60747-5-2
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FUNCTION TABLE
ISO721 (1)
(1)
VCC1
VCC2
PU
PU
PD
PU
INPUT
(IN)
OUTPUT
(OUT)
H
H
L
L
Open
H
X
H
PU = powered up (VCC ≥ 3 V); PD = powered down (VCC ≤ 2.5 V), X = irrelevant, H = high Level; L =
low level
ISO722 (1)
VCC1
(1)
14
VCC2
INPUT
(IN)
ISO722/ISO722M
OUTPUT ENABLE (EN)
OUTPUT
(OUT)
H
L or Open
H
L
L or Open
L
X
H
Z
PU
PU
Open
L or Open
H
PD
PU
X
L or Open
H
PD
PU
X
H
Z
PU = powered up (VCC ≥ 3 V); PD = powered down (VCC ≤ 2.5 V), X = irrelevant, H = high Level; L = low level
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TYPICAL CHARACTERISTICS
RMS SUPPLY CURRENT vs SIGNALING RATE
RMS SUPPLY CURRENT vs SIGNALING RATE
15
10
VCC1 = 3.3 V,
VCC2 = 3.3 V,
o
TA = 25 C,
CL = 15 pF
8
VCC1 = 5 V,
VCC2 = 5 V,
o
TA = 25 C,
CL = 15 pF
14
13
ICC − Supply Current − (mARMS)
ICC − Supply Current − (mARMS)
9
7
6
ICC2
5
4
3
ICC1
2
12
11
10
ICC2
9
8
7
ICC1
6
5
4
3
2
1
1
0
0
0
25
50
75
100
0
25
Signaling Rate (Mbps)
100
Figure 9.
PROPAGATION DELAY vs FREE-AIR TEMPERATURE
PROPAGATION DELAY vs FREE-AIR TEMPERATURE
20
25
16
tPLH
15
tPHL
ISO72xM
10
VCC1 = 3.3 V,
VCC2 = 3.3 V,
CL = 15 pF,
Air Flow at 7 cf/m
5
-10
5
20
35
50
65
80
95
Propagation Delay − ns
20
-25
ISO72x
tPHL
tPHL
ISO72x
0
-40
tPLH
18
tPLH
Propagation Delay − ns
75
Figure 8.
30
14
tPLH
12
tPHL
10
8
ISO72xM
6
VCC1 = 5 V,
VCC2 = 5 V,
CL = 15 pF,
Air Flow at 7 cf/m
4
2
0
-40
110 125
-25
-10
TA − Free-Air Temperature − oC
20
35
50
65
80
95
110 125
Figure 10.
Figure 11.
ISO72x INPUT THRESHOLD VOLTAGE vs
FREE-AIR TEMPERATURE
ISO72xM INPUT THRESHOLD VOLTAGE vs
FREE-AIR TEMPERATURE
2.5
5-V (VIT+)
2.4
1.3
3.3-V (VIT+)
1.25
1.2
Air Flow at 7 cf/m
1.15
5-V (VIT- )
1.1
VIT − Input Voltage Threshold − V
1.35
5-V (VIT+)
2.3
2.2
5-V (VIT-)
2.1
2
Air Flow at 7 cf/m
1.9
1.8
3.3-V (VIT+)
1.7
1.6
1.05
3.3-V (VIT- )
1
-40
5
TA − Free-Air Temperature − oC
1.4
VIT − Input Voltage Threshold − V
50
Signaling Rate (Mbps)
-25
-10
5
20
35
50
3.3-V (VIT-)
1.5
65
80
95
110 125
1.4
-40
-25
TA − Free-Air Temperature − oC
-10
5
20
35
50
65
80
95
110 125
TA − Free-Air Temperature − oC
Figure 12.
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT
VOLTAGE
2.92
-80
2.9
-70
IOH − High-Level Output Current − mA
VCC1 Failsafe Voltage − V
VCC1 FAILSAFE THRESHOLD VOLTAGE vs
FREE-AIR TEMPERATURE
Vfs+
2.88
VCC = 5 V or 3.3 V,
CL = 15 pF,
Air Flow at 7 cf/m
2.86
2.84
2.82
Vfs-
2.8
2.78
-40
o
TA = 25 C
VCC = 5 V
-60
-50
-40
VCC = 3.3 V
-30
-20
-10
0
-25
-10
5
20
35
50
80
65
95
0
110 125
1
2
3
4
5
6
VOH − High-Level Output Voltage − V
TA − Free-Air Temperature − oC
Figure 14.
Figure 15.
LOW-LEVEL OUTPUT CURRENT vs
LOW-LEVEL OUTPUT VOLTAGE
70
o
IOL − Low-Level Output Current − mA
TA = 25 C
60
VCC = 5 V
50
40
30
VCC = 3.3 V
20
10
0
0
1
2
3
4
5
VOL − Low-Level Output Voltage − V
Figure 16.
16
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APPLICATION INFORMATION
MANUFACTURER CROSS-REFERENCE DATA
The ISO72xx isolators have the same functional pinout as most other vendors, and they are often pin-for-pin
drop-in replacements. The notable differences in the products are propagation delay, signaling rate, power
consumption, and transient protection rating. Table 1 is used as a guide for replacing other isolators with the
ISO72x family of single channel isolators.
GND1 4
IN 2
VCC1 3
6 OUT
5 GND2
8 VCC2
7 GND2
6 OUT
5 GND2
GND1 4
VI 2
VDD1 3
GND1 4
VDD1 1
VI 2
*
3
GND1 4
IL710
8 VDD2
7 NC
VDD1 1
VI 2
6 VO
5 GND2
NC 3
GND1 4
8 VDD2
7 VOE
Isolation
VCC1 1
7 EN
8 VDD2
7 GND2
6 VO
5 GND2
Isolation
8 VCC2
HCPL-xxxx
ADuM1100
VDD1 1
Isolation
IN 2
VCC1 3
ISO721
or
ISO721M
Isolation
VCC1 1
Isolation
ISO722
or
ISO722M
6 VO
5 GND2
Figure 17. Pin Cross Reference
Table 1. CROSS REFERENCE
PIN 7
ISOLATOR
PIN 1
PIN 2
PIN 3
PIN 4
PIN 5
PIN 6
ISO721
OR
ISO721M
ISO721 (1) (2)
VCC1
IN
VCC1
GND1
GND2
OUT
GND2
ADuM1100 (1) (2)
VDD1
VI
VDD1
GND1
GND2
VO
GND2
VDD2
HCPL-xxxx
VDD1
VI
*Leave
Open (3)
GND1
GND2
VO
NC (4)
VDD2
IL710
VDD1
VI
NC (5)
GND1
GND2
VO
VOE
VDD2
(1)
(2)
(3)
(4)
(5)
ISO722
OR
ISO722M
PIN 8
EN
VCC2
The ISO72xx pin 1 and pin 3 are internally connected together. Either or both may be used as VCC1.
The ISO721 and ISO721M pin 5 and pin 7 are internally connected together. Either or both may be used as GND2.
Pin 3 of the HCPL devices must be left open. This is not a problem when substituting an ISO72xx device since the extra VCC1 on pin 3
may be left an open circuit as well.
An HCPL device PIN 7 must be left floating (open) or grounded when an ISO722 or ISO722M device is to be used as a drop-in
replacement. If pin 7 of the ISO722 or ISO722M device is placed in a high logic state, the output of the device is disabled
Pin 3 of the IL710 must not be tied to ground on the circuit board since this shorts the ISO72xx's VCC1 to ground. The IL710 pin 3 may
only be tied to VCC or left open to drop in an ISO72xx.
VCC1
VCC2
0.1mF
INPUT
20 mm
max .
from
Vcc1
ISO721
or ISO721M
1
8
20 mm
max.
from
Vcc2
2 IN
7
6
3
OUT
4
5
GND1
0.1mF
OUTPUT
GND2
Figure 18. Basic Application Circuit
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ISOLATION GLOSSARY
Creepage Distance — The shortest path between two conductive input-to-output leads measured along the
surface of the insulation. The shortest distance path is found around the end of the package body.
Clearance — The shortest distance between two conductive input-to-output leads measured through air (line of
sight).
Input-to-Output Barrier Capacitance -- The total capacitance between all input terminals connected together,
and all output terminals connected together.
Input-to-Output Barrier Resistance -- The total resistance between all input terminals connected together, and
all output terminals connected together.
Primary Circuit -- An internal circuit directly connected to an external supply mains or other equivalent source
that supplies the primary circuit electric power.
Secondary Circuit -- A circuit with no direct connection to primary power, and derives its power from a separate
isolated source.
Comparative Tracking Index (CTI) -- CTI is an index used for electrical insulating materials. It is defined as the
numerical value of the voltage that causes failure by tracking during standard testing. Tracking is the process that
produces a partially conducting path of localized deterioration on or through the surface of an insulating material
as a result of the action of electric discharges on or close to an insulation surface -- the higher CTI value of the
insulating material, the smaller the minimum creepage distance.
Generally, insulation breakdown occurs either through the material, over its surface, or both. Surface failure may
arise from flashover or from the progressive degradation of the insulation surface by small localized sparks. Such
sparks are the result of the breaking of a surface film of conducting contaminant on the insulation. The resulting
break in the leakage current produces an overvoltage at the site of the discontinuity, and an electric spark is
generated. These sparks often cause carbonization on insulation material and lead to a carbon track between
points of different potential. This process is known as tracking.
18
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Insulation:
Operational insulation -- Insulation needed for the correct operation of the equipment.
Basic insulation -- Insulation to provide basic protection against electric shock.
Supplementary insulation -- Independent insulation applied in addition to basic insulation in order to ensure
protection against electric shock in the event of a failure of the basic insulation.
Double insulation -- Insulation comprising both basic and supplementary insulation.
Reinforced insulation -- A single insulation system which provides a degree of protection against electric shock
equivalent to double insulation.
Pollution Degree:
Pollution Degree 1 -- No pollution, or only dry, nonconductive pollution occurs. The pollution has no influence.
Pollution Degree 2 -- Normally, only nonconductive pollution occurs. However, a temporary conductivity caused
by condensation must be expected.
Pollution Degree 3 -- Conductive pollution occurs or dry nonconductive pollution occurs, which becomes
conductive due to condensation that is to be expected.
Pollution Degree 4 – Continuous conductivity occurs due to conductive dust, rain, or other wet conditions.
Installation Category:
Overvoltage Category -- This section is directed at insulation co-ordination by identifying the transient
overvoltages that may occur, and by assigning four different levels as indicated in IEC 60664.
1. Signal Level -- Special equipment or parts of equipment.
2. Local Level -- Portable equipment etc.
3. Distribution Level -- Fixed installation
4. Primary Supply Level -- Overhead lines, cable systems
Each category should be subject to smaller transients than the category above.
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PACKAGE OPTION ADDENDUM
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11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
ISO721MMDREP
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
721MEP
ISO721MMDREPG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
721MEP
V62/08627-01XE
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
721MEP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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11-Apr-2013
OTHER QUALIFIED VERSIONS OF ISO721M-EP :
• Catalog: ISO721M
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ISO721MMDREP
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO721MMDREP
SOIC
D
8
2500
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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