Texas Instruments | Designing an Isolated I2C Bus interface by using digital isolators (Rev. A) | Application notes | Texas Instruments Designing an Isolated I2C Bus interface by using digital isolators (Rev. A) Application notes

Texas Instruments Designing an Isolated I2C Bus interface by using digital isolators (Rev. A) Application notes
Analog Design Journal
Signal Chain
Designing a reinforced isolated I2C-Bus®
interface by using digital isolators
By Thomas Kugelstadt
Senior Applications Engineer
I2C Bus operation
The continuing changes in legislation concerning both the
design and use of machinery and equipment require the
isolation of almost any type of industrial system or interface. The inter-integrated circuit bus (I2C Bus®) is a singleended, multi-master, two-wire bus; and, while designed
only for short-distance I2C communication, it is no exception to isolation requirements.
The particular challenge in designing an isolated I2C
interface by using standard digital isolators lies in the
different operation modes between the two. The I2C Bus
operates in bidirectional, half-duplex mode, while standard
digital isolators are unidirectional devices. To make efficient use of one technology supporting the other, external
circuitry is required that separates the bidirectional bus
into two unidirectional signal paths without introducing
significant propagation delay.
This article provides a short introduction to I2C Bus
operation and then describes how to design an isolated I2C
interface by adding only a few external components to a
digital capacitive isolator.
The I2C uses open-drain technology, thus requiring the
serial data line (SDA) and serial clock line (SCL) to be
connected to VDD by resistors (see Figure 1). Pulling the
line to ground is considered a logic “0,” and letting the line
float is a logic “1.” This logic configuration is used as a
channel-access method. Transitions of logic states must
occur while SCL is low, because transitions while SCL is
high indicate START and STOP conditions. Typical supply
voltages are 3.3 V and 5 V, although systems with higher
or lower voltages are permitted.
I2C communication uses a 7-bit address space with 16
reserved addresses, so a theoretical maximum of 112
nodes can communicate on the same bus. In praxis,
however, the number of nodes is limited by the specified
total bus capacitance of 400 pF, which restricts communication distances to a few meters. The specified signaling
rates are 100 kbps (standard mode), 400 kbps (fast
mode), 1 Mbps (fast mode plus), and 3.4 Mbps (highspeed mode).
Figure 1. The I2C Bus®
VDD
RPU
RPU
RPU
RPU
RPU
RPU
RPU
RPU
SDA
SCL
SDA
SCL
GND
µC
Master
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SDA
SCL
SDA
GND
SCL
GND
ADC
Slave
DAC
Slave
1
SDA
SCL
GND
µC
Slave
ADJ 2Q 2018
Analog Design Journal
Signal Chain
Figure 2. Timing diagram of a complete data transfer
7-Bit
ADDRESS
SDA
SCL
1–7
R/W
ACK
8
9
8-Bit
DATA
ACK
8-Bit
DATA
ACK/
NACK
1–8
9
1–8
9
S
P
START
Condition
STOP
Condition
If the master writes to a slave, it repeatedly sends a
byte to the slave, which sends an ACK bit for each byte
received. In this case, the master is in master-transmit
mode and the slave is in slave-receive mode.
If the master reads from a slave, it repeatedly receives a
byte from the slave while sending an ACK bit to acknowledge the receipt of every byte but the last one (see Figure
3). In this situation the master is in master-receive mode
and the slave is in slave-transmit mode.
The master ends the transmission with a STOP bit or
may send another START bit to maintain bus control for
further transfers.
When writing to a slave, a master mainly operates in
transmit mode and changes to receive mode only when
receiving acknowledgment from the slave.
When reading from a slave, the master starts in transmit
mode and then changes to receive mode after sending a
READ request (R/W bit = 1) to the slave. The slave
continues in the complementary mode until the end of a
transaction.
Note that the master ends a reading sequence by not
acknowledging the last byte received—i.e., by sending a
NACK bit. This procedure resets the slave state machine
and allows the master to send the STOP command.
The bus has two roles for nodes: master and slave. A
master issues the clock and slave addresses and also initiates and ends data transactions. A slave receives the clock
and addresses and responds to requests from the master.
Figure 2 shows a typical data transfer between master
and slave.
The master initiates a transaction by creating a START
condition, then transmits the 7-bit address of the slave it
wishes to communicate with. This is followed by a single
READ/WRITE (R/W) bit, representing whether the master
wishes to write to “0” or to read from “1,” the slave. The
master then releases the SDA line to allow the slave to
acknowledge the receipt of data.
The slave responds with an acknowledge (ACK) bit by
pulling SDA low during the entire high time of the ninth
clock pulse on SCL. Then the master continues in either
transmit or receive mode (according to the R/W bit sent),
while the slave continues in the complementary mode
(receive or transmit, respectively).
The address and 8-bit data bytes are sent with the most
significant bit (MSB) first. The START bit is indicated by a
high-to-low transition of SDA while SCL is high. The STOP
condition is created by a low-to-high transition of SDA
while SCL is high.
Figure 3. Changes in transmit/receive modes during a data transfer
From Master to Slave
From Slave to Master
S Slave Address W A
DATA
DATA
A
A P
Master Transmitter Writing to Slave Receiver
S Slave Address R A
DATA
DATA
A
Master Receiver Reading from Slave Transmitter
Texas Instruments
2
A P
A = Acknowledged
(ACK)
A = Not acknowledged
(NACK)
S = Start
P = Stop
R = Read
W = Write
ADJ 2Q 2018
Analog Design Journal
Signal Chain
Figure 4. Isolating an I2C line by using a digital isolator
VCC2
VCC1
Transmit
R4
R3
R PU1
R PU2
Q1
SDA
SDA 1
R1
Isolator
D1
SDA 2
R2
SDA
Receive
To Other
SDA Inputs
D3
Isolator design
SDA1 that is just enough to block Q1 but well below
VIHmin, thus presenting a valid low for an I2C input. At the
same time, R4 provides a logic high to the isolator input in
transmit direction, preventing diode D2 from conducting.
Once SDA2 is released and returns to the level of VCC2,
SDA1 follows after one propagation delay through the
isolator. When the isolator is driven from the bus side
(SDA2), the added signal delays for both the falling and
the rising edges mainly consist of only one propagation
delay through the isolator.
In the opposite direction, when SDA1 is pulled low, its
maximum low-level output, VOLmax, is significantly lower
than VE and causes Q1 to conduct. The low-state signal
passing through the isolator in transmit direction forward
biases D2, and SDA2 goes low. However, when SDA1 is
released, its voltage cannot return to the level of VCC1
immediately due to the remaining low-level signal at
SDA2. Instead, SDA1 rises to the necessary VE potential
that blocks Q1, and it will stay at this level until a highimpedance Q1 allows R4 to provide a logic high to the
isolator input, thus releasing SDA2 and D1. Only then will
SDA1 be able to return to the level of VCC1.
When the isolator is driven from the device side
(SDA1), the added signal delays for both edges increase
due to the involvement of the comparator function.
2
Isolating an I C signal path by using standard digital isolators requires splitting the half-duplex line into separate
transmit and receive paths and converting the isolator’s
push-pull outputs into open-collector outputs via Schottky
diodes (Figure 4). To prevent a transmitted signal from
feeding back to its source, a comparator function is implemented that detects the direction of the signal flow and
switches the signal paths accordingly.
Transistor Q1 and its surrounding resistor network
provide the comparator function. Since the dominant
switching level in I2C is logic low, the base of Q1 is so
biased that a low level applied to SDA1 turns the transistor on, and a low level sent from SDA2 keeps Q1 at high
impedance. While the R3/R2 voltage divider primarily
determines the biasing, diode D3 provides temperature
compensation. To prevent SDA2 from turning Q1 on, the
low-level output at D1 is raised by a voltage drop across
R1, which raises Q1’s emitter potential, VE, and decreases
the base-emitter voltage below the minimum turn-on level.
However, care must be taken to maintain VE below the
minimum input high-level threshold of SDA1, which the
I2C specification lists as VIHmin = 0.3 × VCC.
So, when the I2C Bus at SDA2 is pulled low, the low state
passing in receive direction causes a voltage increase at
Texas Instruments
D2
3
ADJ 2Q 2018
Analog Design Journal
Signal Chain
Figure 5. Final isolator circuit
3.3 V
3.3 V
0.1 µF
1
VCC1
2 kΩ
16
0.1 µF
VCC2
ISO7731
3
SCL1
1 nF *
2.49 kΩ
14
7
3.12 kΩ
10
EN1
EN2
1.1 kΩ
13
4
1.45 kΩ
SCL2
10 pF *
D2
MMBT3904
12
5
SDA1
SDA2
612 Ω
84.5 Ω
BAS40
GND1
2, 8
BAS40
GND1
* Optional components
GND2
9, 15
GND2
Figure 5 shows the final isolator circuit for the majority
of I2C applications where the master is isolated from a
slave bus. In this case, only the SDA line is bidirectional,
while the SCL is unidirectional. For a multi-master system
in which both lines must be bidirectional, the SDA circuit
design can also be applied to the SCL when an ISO7742
isolator is used.
Related Web sites
Product information:
www.ti.com/isolation
ISO7731
ISO7742
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ADJ 2Q 2018
Analog Design Journal
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