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Texas Instruments ISO5852SDW Driving and Protecting SiC and IGBT Power Modules User guides
User's Guide
SLLU298 – May 2018
ISO5852SDW Driving and Protecting SiC and IGBT Power
Modules
This user's guide describes the characteristics, operation, and use of the ISO5852SDWEVM-017
Evaluation Module (EVM). This TI EVM provides driving and protection for popular Silicon Carbide (SiC)
MOSFET and Si IGBT Power Modulues. A complete schematic diagram, printed-circuit board layouts, and
bill of materials are included in this document.
1
2
3
4
Contents
Overview ...................................................................................................................... 3
1.1
Features .............................................................................................................. 3
1.2
Applications .......................................................................................................... 3
1.3
Description ........................................................................................................... 4
Test Setup and Results ..................................................................................................... 9
2.1
Before You Begin .................................................................................................. 9
2.2
Equipment ......................................................................................................... 10
Board Layout ................................................................................................................ 18
Schematic and Bill of Materials ........................................................................................... 25
4.1
Schematic .......................................................................................................... 25
4.2
Bill of Materials .................................................................................................... 31
List of Figures
1
ISO5852SDWEVM-017 EVM Block Diagram ............................................................................ 6
2
ISO5852SDWEVM-017 Top View ......................................................................................... 8
3
ISO5852SDWEVM-017 Mounted on Top of Power Module ........................................................... 9
4
Power Up and Bias Supply Voltages VU and VL Test Setup ........................................................ 11
5
Test Setup for Input and Output Switching Waveforms ............................................................... 12
6
Major Input and Output Waveforms Using Output Overlapping Prevention Feature .............................. 14
7
Thermistor Amplifier Test Setup.......................................................................................... 15
8
Input Bus Voltage Sense Amplifier Test Setup......................................................................... 16
9
Safety Isolated Regions between High and Low Voltage Board Areas ............................................. 17
10
Top View of the Board ..................................................................................................... 18
11
Bottom View Of The Board
12
Component Placement .................................................................................................... 20
13
Top Layer
14
Signal Layer 1 .............................................................................................................. 22
15
Signal Layer 2 .............................................................................................................. 23
16
Bottom Layer................................................................................................................ 24
17
Electrical Schematic of ISO5852SDWEVM-017
18
19
20
21
...............................................................................................
...................................................................................................................
.......................................................................
Electrical Schematic with Functional Blocks Outlined .................................................................
Waveforms with Overlapping Enabled ..................................................................................
Rise Time and Propagation Delay Waveforms with 10 nF Load ....................................................
Fall Time and Propagation Delay Waveforms with 10 nF Load ......................................................
19
21
26
27
28
29
30
List of Tables
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1
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1
Electrical Specifications ..................................................................................................... 4
2
Voltages and Current During Power Up Test........................................................................... 12
3
Function Generator Settings .............................................................................................. 13
4
Oscilloscope Settings ...................................................................................................... 13
5
Themistor Amplifier Output Signals ...................................................................................... 15
6
Input Bus Voltage Sense Amplifier Outputs ............................................................................ 16
7
Bill of Materials
.............................................................................................................
31
Trademarks
All trademarks are the property of their respective owners.
2
ISO5852SDW Driving and Protecting SiC and IGBT Power Modules
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Overview
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1
Overview
The ISO5852SDWEVM-017 is a compact, dual channel isolated gate driver board providing drive, bias
voltages, protection and diagnostic needed for half-bridge SiC MOSFET and Si IGBT Power Modules
housed in 150-mm × 62-mm × 17-mm packages.
This TI EVM is based on 5.7-kVrms reinforced isolation driver IC ISO5852SDW in SOIC-16DW package
with 8.0 mm creepage and clearance. The EVM includes SN6505B based isolated DC-DC transformer
bias supplies.
Isolated temperature and input rail monitoring is provided by 5-kVrms isolated amplifiers AMC1301.
Compact form factor 100-mm × 62-mm × 6.6-mm, excluding connector height, allows direct connection to
standard 62-mm half-bridge modules.
1.1
Features
This EVM supports the following features:
• 20-A peak split sink and source drive current to optimize turn on and turn off switching time
• Two, 2-W output bias supplies with undervoltage lockout (UVLO) and overvoltage lockout (OVLO)
protection
• Turn ON and turn OFF drive voltages can be programmed independently from 12 V to 21 V and from
–3.3 V to –7 V respectively by using two input supplies from 3.3 V to 5.3 V
• Robust noise-immune solution with CMTI >100 V/ns
• Supports 5-kVrms Reinforced Isolation for input rail up to 1700-V
• Programmable Short-circuit sensing and Soft Turn-OFF protection by de-saturation circuit
• 2-A Active Miller Clamp
• Output Short Circuit Clamp
• Fault feedback with reset
• Temperature and input rail monitoring
1.2
Applications
This EVM is used in the following applications:
• Solar inverters
• Motor drives
• HEV and EV chargers
• Wind turbines
• Transportation
• UPS
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Overview
1.3
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Description
Compact driver board ISO5852SDWEVM-017 supports SiC power modules by reducing parasitics,
minimizing switching loss and EMI and providing full required protection and diagnostics features.
1.3.1
Specification
Electrical parameters of the board are shown in Table 1.
Table 1. Electrical Specifications
PARAMETER
TEST CONDITION
MIN
NOM
MAX
4.5
5.0
5.5
UNIT
SUPPLY VOLTAGES AND CURRENTS
VCC
Primary supply voltage
IVCCQ
Primary quiescent current
IN+, IN- low
IVCCS
Primary supply current
FSW = 10kHz,
CLOAD = 10nF
VCCUR
Vcc rising UVLO threshold
VCCUF
Vcc falling UVLO threshold
VCCUH
Vcc UVLO hysteresis
0.2
VCCOR
Vcc rising OVLO threshold
5.7
VCCOF
Vcc falling OVLO threshold
VCCOH
Vcc UVLO hysteresis
VCC2U,
VCC2L
VCC2U,
VCC2L
mA
210
mA
4.5
4.2
5.4
V
30
4.6
4.3
V
V
V
5.8
V
5.5
V
0.2
V
Turn ON drive voltages
Transformer
750342879
15
17
19
V
Turn OFF drive voltages
Transformer
750313734
–5.9
–5
–4.7
V
DRIVE CURRENT AND POWER
IOH
Peak source current
CLOAD = 10nF
15
20
IOL
Peak sink current
CLOAD = 10nF
15
20
PDRV
Drive power per channel
At 25⁰C
A
A
2.0
W
0.7 ×
VCC
V
INPUT/OUTPUT SIGNALS
VINR, VRSTR INL+, INU+, RST rising threshold
VINF, VRSTF
0.3 ×
VCC
INL+, INU+, RST falling threshold
0.15 ×
VCC
VINH, VRSTH INL+, INU+, RST hysteresis
VFLU, VFLL
V
FL, FU Fault voltage
IFLT = 5 mA
VFLU, VFLL
FL, FU Fault current
Internal pullup
current
VFLTH
F high level
At VCC = 4.5 V
VFLTL
F low level
At VCC = 4.5 V
ATEMP
Thermistor monitor gain
8.2
ARAIL
Input rail monitor gain
8.2
V
0.2
100
4.4
V
µA
4.5
V
0.1
V
TIMING PARAMETERS
4
TRISE
Drive output rise time
CLOAD = 10nF
30
TFALL
Drive output fall time
CLOAD = 10nF
34
TPROP
Propagation delay
CLOAD = 100nF
130
TSKEW
Pulse skew
TGLITCH
Input glitch filter
TUVLO
UVLO recovery delay
50
µs
TOVOL
OVLO recovery delay
50
µs
20
ISO5852SDW Driving and Protecting SiC and IGBT Power Modules
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30
ns
ns
150
ns
20
ns
40
ns
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Table 1. Electrical Specifications (continued)
PARAMETER
TEST CONDITION
MIN
NOM
MAX
UNIT
Can be
programmed by
resistors down to 4
V
8.3
9.0
9.5
V
310
400
480
ns
SHORT CIRCUIT PROTECTION
VDESAT
Nominal desaturation threshold
TDESATBLN
K
Blanking time
TDS90
Response time to 90% VOUTHL
CLOAD = 10nF
553
760
ns
TDS10
Response time to 10% VOUTHL
CLOAD = 10nF
2
3.5
µs
ICHARGE
Capacitor charge current
0.42
0.5
0.58
mA
9
14
1.6
2.1
IDISCHARGE Capacitor discharge current
VCLAMP
Miller clamp threshold
ICLAMP
Miller clamp current
mA
2.5
V
4
A
ISOLATION
CMTI
VISO
Withstand isolation voltage
CI
Barrier capacitance
TA
Operating Ambient Temperature
CMTI
100
Reinforced, 60s
5.0
-40
V/ns
kVrms
25
20
pF
125
oC
SIZE
Board size
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Without connector
100 x 62 x 6.6
ISO5852SDW Driving and Protecting SiC and IGBT Power Modules
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mm
5
Overview
1.3.2
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Block Diagram
The ISO5852SDWEVM-017 board block diagram is shown in Figure 1.
Reinforced Isolation
AMC1301
BUS_P
Rx
Tx
DU
BUS_N
DC-DC
+15 V
Vdrp1
S1
Vdrn1
Vdrp1
±5 V
VCC2
VCC
VCC_5V
VCC
Inv
Rec
VCC
VCC1
5V
GND
VCC1
UVLO1
UVLO2
500 µA
DESAT
IN±
DU
Mute
INU+
9V
IN+
S1
GND2
VCC2
FU
SU
VCC1
RDY
Gate Drive
Ready
OUTH
STO
VCC1
FLT
Q
S
Q
R
GU
10
Encoder
Logic
VCC1
10
and
OUTL
Decoder
2V
Fault
CLAMP
RST
GND1
VCC
VEE2
Logic Block
VCC1
Vdrp2
Vdrn1
VCC1
VCC2
UVLO1
UVLO2
500 µA
DESAT
IN±
DL
Mute
RST
9V
S2
IN+
GND2
VCC2
SL
VCC1
INL+
RDY
Gate Drive
Ready
OUTH
and
10
Encoder
Logic
FL
STO
VCC1
FLT
Q
S
Q
R
VCC1
F
10
GL
OUTL
Decoder
2V
Fault
CLAMP
RST
GND1
VEE2
Vdrn2
DC-DC
VCC
Inv
Rec
+15 V
Vdrp1
S2
Vdrn1
±5V
TRO_P
TR_P
Rx
Tx
TRO_N
TR_N
Figure 1. ISO5852SDWEVM-017 EVM Block Diagram
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Overview
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It includes two isolated channels with the following key functional blocks:
• 20A source/sink 5.7 kVrms Isolated driver using ISO5852SDW driver IC
• Split rail bias supply using two 424 kHz transformer drivers SN6505B to generate separately +17 V rail
for turn ON and -5 V rail for turn OFF
• Input logic block with shoot-through prevention
• Output protection and diagnostic block
• Analog amplifiers AMC1301 to monitor temperature inside the module and input voltage rail with 5.0
kVrms isolation
1.3.3
Isolated Gate Driver ISO5852S
ISO5852SDW, isolated driver in SOIC-16DW package with 8.0mm creepage and clearance providing
5.7kVrms reinforced isolation, includes all main short circuit protection features. ISO5852SDW driver IC
employs TI proprietary high voltage, low propagation delay, CMTI immune capacitive isolation technology.
The list of isolation safety certifications from agencies like VDE, CSA, UL and CQC is provided in related
datasheet. Short, 76 ns propagation delay with only 20 ns skew allows accurate control of power devices.
Figure 1 includes block diagram of ISO5852SDW driver.
Primary side voltage Vcc1 is controlled by internal UVLO1 circuit with 2.25Vmax rising threshold and
1.7Vmin falling threshold. Inverting and non-inverting input signals IN- and IN+ have CMOS thresholds
derived from Vcc1 voltage: 0.7 x Vcc1 max rising and 0.3 x Vcc1 min falling accordingly. Secondary side
voltage Vcc2 can go up to 35V abs. max. Turn ON drive voltage between Vcc2 and GND2 pins is
controlled by internal UVLO2 circuit with 13Vmax rising threshold and 9.5V min falling threshold. The split
sink/source output allows setting optimal turn ON and turn OFF time by selecting separate gate resistors
between driver output and gate of power device. This driver has all necessary short circuit protection
features including desaturation current sensing, soft short circuit turn OFF, Miller gate clamp, fault, power
ready and reset signals.
1.3.4
Split-Rail Bias Supply using SN6505B
Split rail bias supply generates 17V turn ON, and -5V turn OFF voltages using two push-pull transformer
drivers SN6505B operating at 424kHz and housed in 6-pin small SOT-23 package.
The SN6505B is supplied through Vcc terminal from external source in the range from 2.25 to 5.5V. Input
voltage is controlled by UVLO circuit having rising threshold 2.25Vmax and falling threshold 1.7V min.
Internal oscillator operates at 424kHz typical frequency within range from 363 kHz min. to 517 kHz max..
The SN6505 employs spread spectrum clocking technique to minimize EMI. The output stage includes 1A
push-pull switches rated up to 16 V abs. max. The switches are protected by current limit circuit tripped at
1.7 A typ. level. The device also protected by thermal shutdown circuit triggered at 168 ºC typical
threshold and returning back to normal operation at 150 ºC typical. Additional features include soft start
and Enable signal. Because there is no closed feedback loop in this inexpensive bias supply solution, it
operates like DC-DC transformer and requires low tolerance primary voltage to maintain output voltages
within ±10% range.
1.3.5
Input Logic
Input logic block fulfills the following functions:
• Provides additional UVLO and OVLO protection of secondary side drive voltages using sensing on
primary side Vcc based on window comparator TPS3700
• Generates separate fault signals for each channel when the short circuit occurs along with general
system fault signal using AND logic CMOS IC SN74AHC1G08QDBVRQ1
• Generates combined Reset signal output for both isolated channels
• Provides isolated differential output signals from temperature and input rail monitoring circuits using
isolated amplifiers AMC1301
• Can be set for driver outputs overlapping prevention mode by having shunt resistors R48 and R52 in
place. To allow outputs overlapping simply remove shunt resistors R48 and R52.
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Output Protection and Diagnostic
The output boost and protection blocks fulfill the following functions:
• Boost sink and source currents up to 20 A typical
• Determine short circuit conditions using Vds sensing
• Provide analog isolated input rail sensing signal using AMC1301 amplifier
• Provide analog isolated temperature monitoring using thermistor inside the module and AMC1301
amplifier
1.3.7
Isolated Differential Amplifier AMC1301
The AMC1301 is a precision, isolated amplifier with an output separated from the input circuitry by an
isolation barrier providing protection from electromagnetic and electrical noise in the system.
The input of the AMC1301 device is optimized for sensing signals in ±250 mV range with high immunity to
common mode noise. The amplifier is housed in wide body SOIC-8DWV package with 9 mm creepage
and clearance.
1.3.8
Board Views
Top view of the driver board ISO5852SDWEVM-017 is shown in Figure 2. Figure 3 shows the driver EVM
soldered on top of power module.
Figure 2. ISO5852SDWEVM-017 Top View
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Figure 3. ISO5852SDWEVM-017 Mounted on Top of Power Module
2
Test Setup and Results
Test setup and related waveforms presented in User's Guide are for ISO5852SDWEVM-017 EVM
EXCLUDING any user provided power modules attached to backside of the EVM. Capacitive load
presented by power module is emulated by 10 nF capacitors C16 and C36. When EVM is attached to and
evaluated with power module, capacitors C16 and C36 should be removed.
2.1
Before You Begin
When starting to evaluate and test the ISO5852SDWEVM-017 EVM, it will typically be in a stand-alone
configuration, separate from power module. This EVM does not internally generate high voltages or high
temperatures.
In the start-up configuration, there will be no high voltage or high temperature capable of presenting the
user with an electrical shock hazard or burn resulting from elevated temperature risks provided the EVM is
used within its electrical load rating limits established in Table 1.
WARNING
To minimize risk of electric shock hazard always follow safety
practices normally followed in a development laboratory. Refer to
TI’s EVM High Voltage guideline accompanying this EVM.
However, to evaluate isolated input rail amplifier voltages in accordance with the described below test
procedure 2.2.4, which requires the addition of an external power source with maximum rating of 300
VDC, high voltage may be accessible between board test points DU and SL.
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Test Setup and Results
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To minimize risk of electrical shock hazard, always follow all high voltage safety rules and regulations
while operating electrical equipment!
When evaluating ISO5852SDWEVM-017 with EVM attached to its intended vendor provided power
module as part of the system level measurements and assessments, the power module will have
accessibility of high voltage and high temperatures that impact the EVM’s operating conditions as well.
High voltages with transients up to 1500Vpk can appear between isolated areas of the EVM, bounded as
illustrated in Figure 9. The externally provided power module also radiates heat that indirectly provides air
flow and convection that can elevate the temperature of EVM board.
WARNING
To minimize risk of fire hazard, it is critical to assure that the
external power module’s electrical and thermal ratings are never
exceeded as published by the external power module’s
manufacturer’s datasheet, and the maximum temperature of any
external power module should never exceed 130 oC.
The EVM provides isolated thermal dissipation diagnostic signals available at connector J1 shown in
Figure 9, which measure high voltage input rail and thermistor temperatures inside the external power
module. Both BUS_P (pin 17) to BUS_N (pin 18) and TRO_P (pin 20) to TRO_N (pin 19) diagnostic
signals must be strictly monitored to assure both high voltage and thermal protective features are being
utilized.
The user is required to provide necessary interface controller hardware to shut down and deenergize the
system immediately if BUS_P to BUS_N signal exceeds 1.85 VDC, or signal TRO_P to TRO_N drops
below 0.135 VDC.
2.2
Equipment
•
•
•
•
•
Power Supplies
– At least up to 6-V and 1-A power supply for powering EVM, for example: BK Precision, series 1715
– At least up to 300-V and 10-mA power source for testing bus isolated sense amplifier within EVM
Function Generator and accessories
– One 2-channel function generator, for example: Tektronix AFG3102
– Two standard 50-Ω BNC coaxial cables
– Two 50-Ω BNC male to female feed-thru terminators, for example: Tektronix 011-0049-02
Oscilloscope and accessories
– Oscilloscope 500-MHz or higher with at least 4 channels, for example: Tektronix DPO7104
– Four at least 500-MHz bandwidth passive voltage probes, for example: P6139A
Six Digital Multi-Meters (DMM), for example Fluke 187
Other
– 20-wire flat cable with receptacle 71600-120LF from FCI with opposite end wired to PCB with
related test points
– Wires 7 to 10 inch long with clips on both ends to make jumpers on some test points
– Resistance decade box, for example 72-7270 from Tenma
Test procedure includes four main tests with different test setups
1. Power up and bias supply voltages test
2. Input and output pulse switching waveforms test
3. Thermistor isolated amplifier input and output signal test
4. Bus voltage sense isolated amplifier input and output signal test
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All test setups shown in the following figures assume the flat test cable with receptacle and test points is
attached to the connector J1 of the EVM.
2.2.1
Power UP Test
Test setup for power up test is shown in Figure 4. For these tests digital multi-metersfor DC voltage
measurements are set auto-range. MM1 is set for DC current measurements with expected range up to
500 mA. Here and in all test setups below, red arrows indicate positive terminals and black arrows indicate
return terminal.
Figure 4. Power Up and Bias Supply Voltages VU and VL Test Setup
WARNING
Before start testing make sure to follow all electrical safety and
ESD protection requirements implemented at your company!
1. Enable power supply PS1
2. Gradually increase the voltage at PS1 and monitor voltage using MM4 and current using MM1
3. Verify measured voltage and current in accordance to Table 2. If current or voltage is outside the
specified range, stop increasing the voltage at PS1 and return to initial stage
4. Gradually reduce the voltage at PS1 to 0 V and disable it
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Measured voltages and current should be within range shown in Table 2.
Table 2. Voltages and Current During Power Up Test
MM4 (Vcc)
2.2.2
MM1 (Icc)
MM2 (+VU)
MM3 (-VU)
MM5 (+VL)
MM6 (-VL)
2.95 V – 3.05 V
< 30 mA
< ±0.1 V
< ±0.1 V
< ±0.1 V
< ±0.1 V
4.65 V – 4.75 V
130 mA – 145 mA
15.5 V – 16.5 V
4.5 V – 5.2 V
15.4 V – 16.4 V
4.5 V – 5.2 V
4.95 V – 5.05 V
135 mA – 150 mA
16.8 V – 17.5 V
5.0 V – 5.5 V
16.6 V – 17.4 V
5.0 V – 5.5 V
5.4 V – 5.45 V
140 mA – 155 mA
17.5 V – 19.0 V
5.5 V – 6.2 V
17.3 V – 18.8 V
5.5 V – 6.2 V
5.7 V < MM4 < 6 V
< 30 mA
< ±0.1 V
< ±0.1 V
< ±0.1 V
< ±0.1 V
Input and Output Switching Waveforms Test
Test setup for switching waveforms is shown in Figure 5.
Figure 5. Test Setup for Input and Output Switching Waveforms
12
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Function generator settings are shown in Table 3.
Table 3. Function Generator Settings
CHANNEL
MODE
FREQ.
WIDTH
DELAY
AMPL.
OFFSET
LOAD
IMPED.
FREQUENC
Y SET
A (Ch.1)
Pulse
10 kHz
80 µs
0
4 Vpp
2.0 V
50 Ω
B (Ch.2)
Pulse
10 kHz
80 µs
50 µs
4 Vpp
2.0 V
50 Ω
Ch1 = Ch2,
ON
SYNC
TRIGGER
RESOLUTION
Oscilloscope settings are shown in Table 4.
Table 4. Oscilloscope Settings
CHANNEL
VERTICAL
SCALE
Ch. 1(red)
10 V/div
Ch. 2(blue)
3 V/div
Ch. 3(pink)
3 V/div
Ch. 4(green)
10 V/div
HORIZONTAL
SCALE
BANDWIDTH
COUPLING
TERMINATIO
N
50 µs/div
500 MHz or
above
DC
1 MΩ
Ch. 2
High
1. Enable power supply PS1
2. Gradually increase the voltage at PS1 into 4.95 V to 5.05 V range and monitor current using MM1 that
should not exceed 150 mA
3. Enable channel A (ch.1) and channel B (ch.2) of function generator
4. Monitor current increase at MM1 but does not exceed 250 mA
5. Compare waveforms with typical screen shot showed in Figure 6
6. Disable function generator channels
7. Gradually reduce voltage at PS1 down to 0 and disable it (Make sure function generator outputs are
disabled before this action!)
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Figure 6. Major Input and Output Waveforms Using Output Overlapping Prevention Feature
•
•
•
•
•
14
INU (pink) is high side input: 3.0V/div
OU (green) is high side output: 10V/div
INL (blue) is low side input: 3.0V/div
OL (red) is low side output: 10V/div
Time scale is 50µs/div
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2.2.3
Thermistor Amplifier Test
Test setup for thermistor amplifier test is shown in Figure 7.
Figure 7. Thermistor Amplifier Test Setup
1. Enable power supply PS1
2. Gradually increase the voltage at PS1 into 4.95 V to 5.05 V range and monitor current using MM1 that
should not exceed 150 mA
3. Set resistances using Resistance Decade Box in accordance to Table 5 and monitor voltages at MM5
and MM6
4. Gradually reduce the voltage of power supply PS1 down to 0 V and disable it
Table 5. Themistor Amplifier Output Signals
RESISTANCE
5.0 kΩ
2.0 kΩ
800 Ω
280 Ω
MM5 (differential output)
1.85 V - 1.91 V
0.85 V - 0.91 V
0.36 V - 0.39 V
0.125 V - 0.145 V
MM6 (common output)
0.4 V - 0.6 V
0.8 V - 1.2 V
1.0 V - 1.4 V
1.2 V - 1.5 V
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15
Test Setup and Results
2.2.4
www.ti.com
7 Sense Amplifier Test
Test setup for input bus voltage sense amplifier test is shown in Figure 8.
Figure 8. Input Bus Voltage Sense Amplifier Test Setup
1. Enable power supply PS1
2. Gradually increase the voltage at PS1 into 4.95 V to 5.05 V range and monitor current using MM1 that
should not exceed 145 mA
3. Enable power supply PS2
4. Gradually increase the voltage of power supply PS2 from 0 V up to 300 V and monitor voltages in
accordance to Table 6
5. Gradually decrease the voltage of power supply PS2 down to 0 and disable it
6. Gradually reduce the voltage of power supply PS1 down to 0 V and disable it
Table 6. Input Bus Voltage Sense Amplifier Outputs
16
PS2
0V
49 V - 51 V
99 V - 101 V
149 V - 151 V
299 V - 301 V
MM5 (differential output)
0.28 V - 0.32 V
0.34 V - 0.38 V
0.39 V - 0.43 V
0.42 V - 0.48 V
0.58 V - 0.64 V
MM6 (common output)
1.15 V - 1.45 V
1.1 V - 1.4 V
1.05 V - 1.35 V
1.0 V - 1.3 V
0.95 V - 1.25 V
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Test Setup and Results
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Figure 9. Safety Isolated Regions between High and Low Voltage Board Areas
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17
Board Layout
3
www.ti.com
Board Layout
General top and bottom view, component placement and all four layers are shown in Figure 10 through
Figure 16 respectively.
Figure 10. Top View of the Board
18
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Board Layout
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Figure 11. Bottom View Of The Board
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Board Layout
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Figure 12. Component Placement
20
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Board Layout
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Figure 13. Top Layer
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Board Layout
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Figure 14. Signal Layer 1
22
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Board Layout
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Figure 15. Signal Layer 2
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Board Layout
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Figure 16. Bottom Layer
24
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Schematic and Bill of Materials
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4
Schematic and Bill of Materials
4.1
Schematic
The schematic of ISO5852SDWEVM-017 board is shown in Figure 17. Functional blocks of the schematic
are shown in Figure 18 and below are listed the functions that related blocks perform.
• B1 - high side +17.5V/-5V bias supply
• B2 - low side +17.5V/-5V bias supply
• B3 - connectors, UVLO/OVLO protection, fault and reset logic, overlapping option setting
• B4 - high side driver with booster and desaturation protection
• B5 - low side driver with booster and desaturation protection
• B6 - input bus voltage sensing isolated amplifier
• B7 - thermistor based temperature sense isolated amplifier
The ISO5852SDWEVM-017 EVM allows following adjustments depending on applications.
• By default the board set into output overlapping protection mode. Removing resistor shunts R48 and
R52 allows output overlapping
• When attaching EVM to power module, it is recommended to remove output load capacitors C16 and
C36
• To set turn ON and OFF output driver voltages beoynd the default, UVLO/OVLO protection can be
disabled by removing resistor R53
• By removing resistive shunt R65 and using separate input supplies applied to connectors J1 and J2,
turn ON and turn OFF drive voltages can be independently adjusted. The EVM maintains functionality
if the VCC input supply voltages are within range from 3V to 5.5V. This allows set drive voltages
approximately from +12 V to +21 V for turn ON drive voltage and from -3.5 V to -7 V for turn OFF drive
voltage
• Change of C15 and C35 values allows soft shutdown adjustment during short circuit protection
respectively for high side and low side drivers
• By default resistors R1 and R17 are not included. Adding these resistors provide additional current
source for desaturation protection circuit
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Schematic and Bill of Materials
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Figure 17. Electrical Schematic of ISO5852SDWEVM-017
26
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Figure 18. Electrical Schematic with Functional Blocks Outlined
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Schematic and Bill of Materials
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Additional waveforms are shown below to illustrate described above adjustments and EVM drive current
capabilites. Operation waveforms with overlapping enabled is shown in Figure 19.
Figure 19. Waveforms with Overlapping Enabled
•
•
•
•
•
28
INU (pink) is high side input: 3.0V/div
OU (green) is high side output: 10V/div
INL (blue) is low side input: 3.0V/div
OL (red) is low side output: 10V/div
Time scale is 50µs/div
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Current capability during turn ON is illustrated in Figure 20 by rise time while charging 10 nF load
capacitors
Figure 20. Rise Time and Propagation Delay Waveforms with 10 nF Load
•
•
•
•
•
•
•
INU (pink) is high side input: 3.0V/div
OU (green) is high side output: 10V/div
INL (blue) is low side input: 3.0V/div
OL (red) is low side output: 10V/div
Time scale is 50ns/div
Rise time is about 30 ns
Propagation delay is 133.5 ns
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Schematic and Bill of Materials
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Current capability during turn OFF with 10 nF load capacitors is illustrated in Figure 21.
Figure 21. Fall Time and Propagation Delay Waveforms with 10 nF Load
•
•
•
•
•
•
•
30
INU (pink) is high side input: 3.0V/div
OU (green) is high side output: 10V/div
INL (blue) is low side input: 3.0V/div
OL (red) is low side output: 10V/div
Time scale is 50ns/div
Fall time is about 34 ns
Propagation delay is 98.5 ns
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Schematic and Bill of Materials
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4.2
Bill of Materials
Table 7. Bill of Materials
DESIGNATOR
QTY
VALUE
PART NUMBER
MANUFACTURER
DESCRIPTION
PACKAGE
REFERENCE
C1, C21
2
220pF
GRM188R71H221KA01D
MuRata
CAP, CERM, 220 pF, 50 V,
+/- 10%, X7R, 0603
0603
C2, C9, C22, C29
4
10uF
C3216X7R1V106M160AC
TDK
CAP, CERM, 10 uF, 35 V,
+/- 20%, X7R, 1206_190
1206_190
C3, C5, C10, C11,
C18, C23, C25, C30,
C31, C38, C45, C53
12
0.1uF
C1005X7R1H104K050BB
TDK
CAP, CERM, 0.1 uF, 50 V,
+/- 10%, X7R, 0402
0402
C4, C24
2
10uF
GRM21BR6YA106KE43L
MuRata
CAP, CERM, 10 uF, 35 V,
+/- 10%, X5R, 0805
0805
C6, C19, C27, C39
4
10uF
C1608X5R1E106M080AC
TDK
CAP, CERM, 10 uF, 25 V,
+/- 20%, X5R, 0603
0603
C7, C26, C43, C51
4
0.1uF
CGA5L2X7R2A104K160AA
TDK
CAP, CERM, 0.1 uF, 100
V, +/- 10%, X7R, AECQ200 Grade 1, 1206
1206
C8, C20, C28, C40,
C48
5
0.1uF
GRM155R61A104KA01D
MuRata
CAP, CERM, 0.1 uF, 10 V,
+/- 10%, X5R, 0402
0402
0402
C12, C13, C32, C33
4
100pF
CC0402JRNPO9BN101
Yageo America
CAP, CERM, 100 pF, 50 V,
+/- 5%, C0G/NP0, 0402
C14, C17, C34, C37,
C44, C52
6
10uF
C2012X5R1E106K125AB
TDK
CAP, CERM, 10 uF, 25 V,
+/- 10%, X5R, 0805
0805
C15, C35
2
0.015uF
CGA3E2X7R2A153K080AA
TDK
CAP, CERM, 0.015 uF,
100 V, +/- 10%, X7R, AECQ200 Grade 1, 0603
0603
C16, C36
2
0.01uF
GCM188R71H103KA37D
MuRata
CAP, CERM, 0.01 uF, 50
V, +/- 10%, X7R, AECQ200 Grade 1, 0603
0603
C41, C49
2
0.1uF
12061C104JAT2A
AVX
CAP, CERM, 0.1 uF, 100
V, +/- 5%, X7R, 1206
1206
C42
1
0.01uF
C0402C103J5RACTU
Kemet
CAP, CERM, 0.01 uF, 50
V, +/- 5%, X7R, 0402
0402
0402
C46, C47, C57, C58
4
10pF
04025U100CAT2A
AVX
CAP, CERM, 10 pF, 50
V,+/- 2.5%, C0G/NP0,
AEC-Q200 Grade 1, 0402
C50
1
0.01uF
C0603H103J3GACTU
Kemet
CAP, CERM, 0.01 uF, 25
V, +/- 5%, C0G/NP0, 0603
0603
C54, C56
2
2.2uF
C1206C225K4RACTU
Kemet
CAP, CERM, 2.2 uF, 16 V,
+/- 10%, X7R, 1206
1206
C55
1
1uF
UMK107AB7105KA-T
Taiyo Yuden
CAP, CERM, 1 uF, 50 V,
+/- 10%, X7R, 0603
0603
SOD-323
D1, D6, D8, D10,
D14, D16, D18, D20
8
40V
B0540WS-7
Diodes Inc.
Diode, Schottky, 40 V, 0.5
A, SOD-323
D2, D5, D11, D15
4
1200V
STTH112A
STMicroelectronics
Diode, Ultrafast, 1200 V, 1
A, SMA
SMA
Diodes Inc.
Diode, Zener, 12 V, 200
mW, SOD-323
SOD-323
Diodes Inc.
Diode, Schottky, 30 V, 0.2
A, SOD-323
SOD-323
Diodes Inc.
Diode, Schottky, 40 V, 2 A,
SMA
SMA
Littelfuse
Diode, TVS, Bi, 22 V, SMA
SMA
N/A
Fiducial mark. There is
nothing to buy or mount.
N/A
FCI
Header(shrouded),
2.54mm, 10x2, Gold with
Tin tail, TH
Header(shroude
d), 2.54mm,
10x2, TH
On-Shore Technology
Terminal Block, 2.54mm,
2x1, Brass, TH
Terminal Block,
2.54mm, 2-pole,
Brass, TH
TDK
Coupled inductor, 2.8 A,
0.055 ohm, SMD
4.7x4.5mm
Diodes Inc.
Transistor, NPN, 60 V, 5 A,
AEC-Q101, SOT-89
SOT-89
Diodes Inc.
Transistor, PNP, 60 V, 4.3
A, AEC-Q101, SOT-89
SOT-89
Panasonic
RES, 1.00 k, 1%, 0.25 W,
0805
0805
D3, D12
2
12V
MMSZ5242BS-7-F
D4, D13
2
30V
BAT54WS-7-F
D7, D17
2
40V
B240A-13-F
D9, D19
2
22V
SMAJ22CA
FID1, FID2, FID3
3
N/A
J1
1
71918-220LF
J2
1
OSTVN02A150
L1
1
ACM4520-421-2P-T000
Q1, Q3
2
60 V
ZXTN2010ZTA
Q2, Q4
2
60 V
ZXTP2012ZTA
R1, R17
2
1.00k
ERJ-P06F1001V
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Schematic and Bill of Materials
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Table 7. Bill of Materials (continued)
DESIGNATOR
VALUE
PART NUMBER
R2, R18
2
10.0k
CRCW080510K0FKEA
R3, R19
2
1.00Me
g
CRCW08051M00FKEA
R4, R5, R20, R21
4
100
CRCW0402100RFKED
R6, R22, R61
3
10
CRCW080510R0JNEA
R7, R9, R11, R23,
R25, R27
6
12
CRCW080512R0JNEA
R8, R10, R12, R14,
R15, R16, R24, R26,
R28, R30, R31, R34
12
1.20
CRCW12061R20FKEA
R13, R29, R63, R64
4
10.0k
RC0603FR-0710KL
R32, R67
2
10.0k
R33, R48, R52
3
R35, R65
2
MANUFACTURER
DESCRIPTION
PACKAGE
REFERENCE
Vishay-Dale
RES, 10.0 k, 1%, 0.125 W,
0805
0805
Vishay-Dale
RES, 1.00 M, 1%, 0.125
W, 0805
0805
Vishay-Dale
RES, 100, 1%, 0.063 W,
0402
0402
Vishay-Dale
RES, 10, 5%, 0.125 W,
0805
0805
Vishay-Dale
RES, 12, 5%, 0.125 W,
0805
0805
Vishay-Dale
RES, 1.20, 1%, 0.25 W,
AEC-Q200 Grade 0, 1206
1206
Yageo America
RES, 10.0 k, 1%, 0.1 W,
0603
0603
RMCF0402FT10K0
Stackpole Electronics
Inc
RES, 10.0 k, 1%, 0.063 W,
AEC-Q200 Grade 0, 0402
0402
0
ERJ-3GEY0R00V
Panasonic
RES, 0, 5%, 0.1 W, 0603
0603
0
MCR18EZHJ000
Rohm
RES, 0, 5%, 0.25 W, 1206
1206
Vishay-Dale
RES, 1.00 M, 1%, 0.25 W,
1206
1206
R36, R37, R38, R39,
R40, R41, R42, R43,
R44
9
1.00Me
g
CRCW12061M00FKEA
R45
1
49.9k
CRCW040249K9FKED
R46
1
1.21k
CRCW04021K21FKED
R47
1
523k
CRCW0402523KFKED
R49, R50, R51, R54,
R58, R59, R62, R66
8
10.0
CRCW040210R0FKED
R53
1
10.5k
CRCW040210K5FKED
R55, R60
2
0
CRCW04020000Z0ED
Vishay-Dale
RES, 49.9 k, 1%, 0.063 W,
0402
0402
Vishay-Dale
RES, 1.21 k, 1%, 0.063 W,
AEC-Q200 Grade 0, 0402
0402
Vishay-Dale
RES, 523 k, 1%, 0.063 W,
AEC-Q200 Grade 0, 0402
0402
Vishay-Dale
RES, 10.0, 1%, 0.063 W,
0402
0402
Vishay-Dale
RES, 10.5 k, 1%, 0.063 W,
AEC-Q200 Grade 0, 0402
0402
Vishay-Dale
RES, 0, 5%, 0.063 W,
AEC-Q200 Grade 0, 0402
0402
0402
R56
1
40.2k
CRCW040240K2FKED
Vishay-Dale
RES, 40.2 k, 1%, 0.063 W,
AEC-Q200 Grade 0, 0402
R57
1
100k
RMCF0402FT100K
Stackpole Electronics
Inc
RES, 100 k, 1%, 0.063 W,
AEC-Q200 Grade 0, 0402
0402
T1, T3
2
50uH
750342879
Wurth Elektronik
Transformer, 50 uH, SMT
9.14x8mm
T2, T4
2
340uH
750313734
Wurth Elektronik
Transformer, 340 uH, TH
8x9.14mm
TP1, TP2, TP3, TP4,
TP5, TP6, TP7, TP8,
TP9, TP10, TP11,
TP12, TP13, TP14
14
0508-0-00-15-00-00-03-0
Mill-Max
PCB Pin, 20mil Dia, Gold,
TH
PCB Pin, 20mil
Dia, TH
U1, U4
2
ISO5852SDWR
Texas Instruments
5.7 kVrms Split O/P,
Reinforced Isolated IGBT
Gate Driver, DW0016B
(SOIC-16)
DW0016B
U2, U3, U5, U6
4
SN6505BDBVR
Texas Instruments
Low-Noise 1 A, 420 kHz
Transformer Driver,
DBV0006A (SOT-23-6)
DBV0006A
U7, U10
2
SN74AHC1G08QDBVRQ1
Texas Instruments
Automotive Catalog Single
2-Input Positive-AND Gate,
DBV0005A, LARGE T&R
DBV0005A
U8, U11
2
AMC1301DWVR
Texas Instruments
Precision +/-250-mV Input,
3-us Delay, Reinforced
Isolated Amplifier,
DWV0008A (SOIC-8)
DWV0008A
U9
1
TPS3700QDDCRQ1
Texas Instruments
Automotive, High-Voltage
(18V) Window Comparator
with Over- and
Undervoltage Detection,
DDC0006A (SOT-23-T-6)
DDC0006A
Texas Instruments
150-mA, 30-V, Ultra-Low
IQ, Wide Input LowDropout Regulator with
Reverse Current
Protection, DBV0005A
(SOT-23-5)
DBV0005A
U12
32
QTY
1
TPS70950DBVR
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STANDARD TERMS FOR EVALUATION MODULES
1.
Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance
with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2
Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have
been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications
or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control
techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.
User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)
business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit
User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty
period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or
replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be
warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
3
Regulatory Notices:
3.1 United States
3.1.1
Notice applicable to EVMs not FCC-Approved:
FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software
associated with the kit to determine whether to incorporate such items in a finished product and software developers to write
software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or
otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition
that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.
Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must
operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1
For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1
Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2
Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow the
instructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs
(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿6丁目24番1号
西新宿三井ビル
3.3.3
Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http:/
/www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
3.4 European Union
3.4.1
For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):
This is a class A product intended for use in environments other than domestic environments that are connected to a
low-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment this
product may cause radio interference in which case the user may be required to take adequate measures.
4
EVM Use Restrictions and Warnings:
4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1
User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2
EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5.
Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
6.
Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT
LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL
FAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT
NOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS
FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE
SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BE
CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL OR
INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THE
EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY OR
IMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED.
7.
USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLY
WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL
THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
8.
Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR
REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING,
OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF
USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI
MORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS
OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDED
HEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR IN
CONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAR
EVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE
CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9.
Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES
Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to,
reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are
developing applications that incorporate TI products; by downloading, accessing or using any particular TI Resource in any way, you
(individually or, if you are acting on behalf of a company, your company) agree to use it solely for this purpose and subject to the terms of
this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources.
You understand and agree that you remain responsible for using your independent analysis, evaluation and judgment in designing your
applications and that you have full and exclusive responsibility to assure the safety of your applications and compliance of your applications
(and of all TI products used in or for your applications) with all applicable regulations, laws and other applicable requirements. You
represent that, with respect to your applications, you have all the necessary expertise to create and implement safeguards that (1)
anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that
might cause harm and take appropriate actions. You agree that prior to using or distributing any applications that include TI products, you
will thoroughly test such applications and the functionality of such TI products as used in such applications. TI has not conducted any
testing other than that specifically described in the published documentation for a particular TI Resource.
You are authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include
the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO
ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING TI RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS.
TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY YOU AGAINST ANY CLAIM, INCLUDING BUT NOT
LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF
DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL,
COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR
ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
You agree to fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of your noncompliance with the terms and provisions of this Notice.
This Notice applies to TI Resources. Additional terms apply to the use and purchase of certain types of materials, TI products and services.
These include; without limitation, TI’s standard terms for semiconductor products http://www.ti.com/sc/docs/stdterms.htm), evaluation
modules, and samples (http://www.ti.com/sc/docs/sampterms.htm).
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
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