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Texas Instruments ISO72XEVM User guides
User's Guide
SLLU091 – January 2006
ISO721EVM
1
2
Contents
Introduction ................................................................................................................... 1
EVM Setup and Operation .................................................................................................. 3
List of Figures
1
2
3
4
5
6
The ISO721 and ISO721M Pinout .........................................................................................
The ISO721 and ISO721M EVM Schematic .............................................................................
ISO721 and ISO721M EVM, Top .........................................................................................
ISO721 and ISO721M EVM, Bottom .....................................................................................
Basic EVM Operation .......................................................................................................
Typical Input and Output Waveforms .....................................................................................
2
2
3
3
4
4
List of Tables
1
1
EVM Connections ............................................................................................................ 2
Introduction
This user's guide details the evaluation module (EVM) operation of the ISO721 and ISO721M digital
isolators. The same EVM board is used for each device. Configuration requirements are presented as well
as user optional I/O loads. This document is intended to aid designers with isolator parameter
performance evaluation within a particular system.
1.1
Overview
The ISO721 and ISO721M digital isolators have a logic input and output buffer separated by a silicon
oxide (SiO2) insulation barrier. Used with isolated power supplies, these devices prevent noise currents on
a data bus or other circuits from entering the local ground and interfering with or damaging sensitive
circuitry.
A binary input signal is conditioned, translated to a balanced signal, and then differentiated by the
capacitive isolation barrier. Across the isolation barrier, a differential comparator receives the logic
transition information, then sets or resets a flip-flop and the output circuit accordingly. A periodic update
pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not
received for more than 4 μs, the input is assumed to be unpowered or not functional, and the fail-safe
circuit drives the output to a logic-high state.
CAUTION
Note that although these devices provide galvanic isolation of up to 4000 V, this
EVM cannot be used for isolation voltage testing. It is designed for the
examination of device operating parameters only and will be damaged if high
voltage (> 5.5 V) is applied anywhere in the circuit.
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Introduction
1.2
Functional Configuration of the ISO721 and ISO721M
The EVM is configured for the pinout displayed in Figure 1. The additional I/Os on the EVM are provided
for future development.
ISO721
ISO721M
8 VCC2
ISOLATION
VCC1 1
IN 2
VCC1 3
GND1 4
7 GND2
6 OUT
5 GND2
Figure 1. The ISO721 and ISO721M Pinout
The ISO721 has TTL input thresholds and a input noise filter that prevents transient pulses of up to 2 ns in
duration from being passed to the output of the device.
The ISO721M has a CMOS VCC/2 input threshold and does not have the noise filter and the additional
propagation delay. These features of the ISO721M also provide for a 0-Mbps to 150-Mbps signaling rate
rather than the ISO721’s 0-Mbps to 100-Mbps signaling rate.
1.3
EVM Signal Paths of the ISO721 and ISO721M Isolators
This multifunctional EVM is designed with signal paths shown in Figure 2 for the analysis of the ISO721
and ISO721M, as well as future isolator configurations.
V CC1 (Banana Jack P 1)
C2
INPUT
J3
C3
C4
C5
V CC2 (Banana Jack P 2)
C6
C11
C10
C9
C8
ISO 721
or
ISO 721M
0W
SMA
1
50 W
8
0W
2 IN
7
6
3
OUT
4
5
GND 1 (Banana Jack P 3)
C7
OUTPUT
J2
SMA
GND 2 (Banana Jack P 4)
Figure 2. The ISO721 and ISO721M EVM Schematic
Table 1. EVM Connections
Connection
Label
J1
SMA connector (unused)
J2
SMA connector to the output pin 6
J3
SMA connector to the input pin 2
J4
2
Description
SMA connector (unused)
P1
VCC1
Input power supply banana jack
P2
VCC2
Output power supply banana jack
P3
GND1
Input power ground connection banana jack
P4
GND2
Output power ground connection banana jack
ISO721EVM
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EVM Setup and Operation
Table 1. EVM Connections (continued)
Connection
1.4
Label
Description
JMP1
3-pin jumper (unused)
JMP2
3-pin jumper (unused)
JMP3
3-pin jumper – VCC1, input, GND1
JMP4
3-pin jumper (unused)
The EVM Configuration
The ISO721EVM configuration has an SMA connector J3 set up as the input to pin 2, the IN pin of the
ISO721 in Figure 1 and Figure 2. A 0-Ω input series resistor, R8, is located next to the J3 input connector,
and a 50-Ω R5 from the input to ground is located on the bottom of the board.
R8
IN
OUT
R4
Figure 3. ISO721 and ISO721M EVM, Top
The output channel configuration of the ISO721EVM has the OUT pin (pin 6) of Figure 1 and Figure 2
connected to SMA connector J2 through a 0- Ω series resistor R4.
R5
IN
OUT
Figure 4. ISO721 and ISO721M EVM, Bottom
The pads for R3, C12, and C13 are available on the bottom of the EVM for varied loading conditions if
desired by a user.
2
EVM Setup and Operation
This section includes the setup and operation of the EVM for parameter performance evaluation. Typical
waveforms are included.
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EVM Setup and Operation
2.1
Overview
The basic setup in Figure 5 has the two power supplies required to evaluate isolator performance with
3.3-V on one side and 5-V on the other. If both sides are to be evaluated at the same supply voltage, only
one power supply is required and can be used to power both sides of the EVM.
CAUTION
Note that this EVM is for operating parameter performance evaluation only and
not designed for isolation voltage testing. Any voltage applied above the 5.5-V
maximum recommended operating voltage of the ISO721 will damage the
EVM.
Power Supply
Tektronix
HFS9009
Pattern
Generator
P1
Power Supply
P3
P2
Tektronix
784D
Scope
P4
J3
Vcc 1 GND 1
INPUT
Vcc 2 GND 2
J2
OUTPUT
Figure 5. Basic EVM Operation
The input to the EVM is a 20-MHz pulse displayed on channel 1 in Figure 6. The output of the EVM is
channel 2.
Figure 6. Typical Input and Output Waveforms
4
ISO721EVM
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EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES
ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have
electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be complete
in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental
measures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit does
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Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from
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TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or
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Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the product. This
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This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES
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Copyright © 2007, Texas Instruments Incorporated
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 0 V to 5.5 V and the output voltage range of 0 V to 6 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions
concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 85°C. The EVM is designed to operate
properly with certain components above 85°CC as long as the input and output ranges are maintained. These components include but are
not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified
using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation,
please be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
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