Texas Instruments | SN74HCS08 Quadruple 2-Input AND Gates with Schmitt-Trigger Inputs | Datasheet | Texas Instruments SN74HCS08 Quadruple 2-Input AND Gates with Schmitt-Trigger Inputs Datasheet

Texas Instruments SN74HCS08 Quadruple 2-Input AND Gates with Schmitt-Trigger Inputs Datasheet
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SN74HCS08
SCLS778 – DECEMBER 2019
SN74HCS08 Quadruple 2-Input AND Gates with Schmitt-Trigger Inputs
1 Features
2 Applications
•
•
•
•
1
•
•
•
Wide operating voltage range: 2 V to 6 V
Schmitt-trigger inputs allow for slow or noisy input
signals
Low power consumption
– Typical ICC of 100 nA
– Typical input leakage current of ±100 nA
±7.8-mA output drive at 5 V
Extended ambient temperature range: –40°C to
+125°C, TA
Combine power good signals
Combine enable signals
3 Description
This device contains four independent 2-input AND
Gates with Schmitt-trigger inputs. Each gate performs
the Boolean function Y = A ● B in positive logic.
Device Information(1)
PART NUMBER
SN74HCS08PWR
PACKAGE
TSSOP (14)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Benefits of Schmitt-trigger Inputs
Voltage
Output
Current
Voltage
Current
Output
Input Voltage
Voltage
Output
Voltage
Time
Current
Response
Waveforms
Time
Time
Input Voltage
Output
Schmitt-trigger
CMOS Input
Time
Time
Current
Response
Waveforms
Supply Current
Standard
CMOS Input
Supply Current
Input Voltage
Supports Slow Inputs
Input
Voltage
Noise Rejection
Input
Voltage
Input Voltage
Waveforms
Input
Voltage
Low Power
Time
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74HCS08
SCLS778 – DECEMBER 2019
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
3
4
4
4
4
5
5
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
8.3 Feature Description................................................... 7
8.4 Device Functional Modes.......................................... 8
9
Application and Implementation .......................... 9
9.1 Application Information.............................................. 9
9.2 Typical Application .................................................... 9
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 12
11.1 Layout Guidelines ................................................. 12
11.2 Layout Example .................................................... 12
12 Device and Documentation Support ................. 13
12.1
12.2
12.3
12.4
12.5
12.6
Parameter Measurement Information .................. 6
Detailed Description .............................................. 7
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram ......................................... 7
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13
13
13 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
2
DATE
REVISION
NOTES
December 2019
*
Initial release.
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5 Pin Configuration and Functions
PW Package
14-Pin TSSOP
Top View
1A
1
14
VCC
1B
2
13
4B
1Y
3
12
4A
2A
4
11
4Y
2B
5
10
3B
2Y
6
9
3A
GND
7
8
3Y
Pin Functions
PIN
NAME
I/O
NO.
DESCRIPTION
1A
1
Input
Channel 1, Input A
1B
2
Input
Channel 1, Input B
1Y
3
Output
2A
4
Input
Channel 2, Input A
2B
5
Input
Channel 2, Input B
2Y
6
Output
GND
7
—
3Y
8
Output
3A
9
Input
Channel 3, Input A
3B
10
Input
Channel 3, Input B
4Y
11
Output
4A
12
Input
Channel 4, Input A
4B
13
Input
Channel 4, Input B
VCC
14
—
Channel 1, Output Y
Channel 2, Output Y
Ground
Channel 3, Output Y
Channel 4, Output Y
Positive Supply
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
–0.5
7
UNIT
VCC
Supply voltage
V
IIK
Input clamp current (2)
VI < –0.5 or VI > VCC +
0.5
±20
mA
IOK
Output clamp current (2)
VO < –0.5 or VO > VCC +
0.5
±20
mA
IO
Continuous output current
VO = 0 to VCC
±35
mA
Continuous current through VCC or GND
±50
mA
TJ
Junction temperature (3)
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Do not exceed the absolute
maximum voltage supply rating.
Guaranteed by design.
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6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC
specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VCC
Supply voltage
2
6
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
Δt/Δv
Input transition rise and fall rate
TA
Ambient temperature
VCC
Unlimited
–40
V
ns/V
125
°C
6.4 Thermal Information
SN74HCS08
THERMAL METRIC
PW (TSSOP)
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance
151.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
79.4
°C/W
RθJB
Junction-to-board thermal resistance
94.7
°C/W
ΨJT
Junction-to-top characterization parameter
25.2
°C/W
ΨJB
Junction-to-board characterization parameter
94.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
6.5 Electrical Characteristics
over operating free-air temperature range; typical ratings measured at TA = 25°C (unless otherwise noted).
PARAMETER
VT+
VT-
ΔVT
VOH
TEST CONDITIONS
Positive switching threshold
Negative switching threshold
Hysteresis (VT+ - VT-)
High-level output voltage
VI = VIH or VIL
VCC
MIN
TYP
MAX UNIT
2V
0.7
1.5
4.5 V
1.7
3.15
6V
2.1
4.2
2V
0.3
1.0
4.5 V
0.9
2.2
6V
1.2
3.0
2V
0.2
1.0
4.5 V
0.4
1.4
6V
0.6
1.6
IOH = -20 µA
2 V to 6 V
IOH = -6 mA
4.5 V
IOH = -7.8 mA
6V
IOL = 20 µA
2 V to 6 V
IOL = 6 mA
4.5 V
IOL = 7.8 mA
VCC – 0.1
VCC – 0.002
4
4.3
5.4
V
V
V
V
5.75
0.002
0.1
0.18
0.30
VOL
Low-level output voltage
VI = VIH or VIL
6V
0.22
0.33
II
Input leakage current
VI = VCC or 0
6V
±100
±1000
nA
ICC
Supply current
VI = VCC or 0, IO = 0
6V
0.1
2
µA
Ci
Input capacitance
5
pF
4
2 V to 6 V
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Electrical Characteristics (continued)
over operating free-air temperature range; typical ratings measured at TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
Power dissipation capacitance
per gate
Cpd
VCC
No load
MIN
TYP
2 V to 6 V
MAX UNIT
10
pF
6.6 Switching Characteristics
over operating free-air temperature range; typical ratings measured at TA = 25°C (unless otherwise noted). See the
Parameter Measurement Information.
PARAMETER
FROM (INPUT)
TO (OUTPUT)
VCC
TYP
MAX
14
36
4.5 V
7
13
6V
6
12
2V
9
17
4.5 V
5
8
6V
4
7
2V
tpd
Propagation delay
tt
A or B
Y
Transition-time
Y
MIN
UNIT
ns
ns
6.7 Typical Characteristics
TA = 25°C
70
46
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
Output Resistance (:)
42
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
65
Output Resistance (:)
44
40
38
36
34
32
60
55
50
45
40
30
35
28
26
30
0
2.5
5
7.5 10 12.5 15 17.5
Output Sink Current (mA)
20
22.5
25
0
Figure 1. Output driver resistance in Low state
ICC ± Supply Current (mA)
VCC = 2.5 V
0.14
VCC = 3.3 V
ICC ± Supply Current (mA)
VCC = 2 V
0.16
0.12
0.1
0.08
0.06
0.04
0.02
0
0
0.5
1
1.5
2
2.5
VI ± Input Voltage (V)
3
5
7.5 10 12.5 15 17.5
Output Source Current (mA)
20
22.5
25
Figure 2. Output driver resistance in High state
0.2
0.18
2.5
3.5
Figure 3. Typical supply current versus input voltage across
common supply values (2 V to 3.3 V)
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
VCC = 4.5 V
VCC = 5 V
VCC = 6 V
0
0.5
1
1.5
2 2.5 3 3.5 4
VI ± Input Voltage (V)
4.5
5
5.5
6
Figure 4. Typical supply current versus input voltage across
common supply values (4.5 V to 6 V)
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7 Parameter Measurement Information
•
•
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 2.5 ns.
The outputs are measured one at a time, with one input transition per measurement.
Test
Point
90%
VCC
90%
Input
10%
10%
tr(1)
From Output
Under Test
CL(1)
0V
tf(1)
90%
VOH
90%
Output
10%
10%
tr(1)
CL= 50 pF and includes probe and jig capacitance.
Figure 5. Load Circuit
tf(1)
VOL
Figure 6. Voltage Waveforms
Transition Times
VCC
Input
50%
50%
0V
tPHL(1)
tPLH(1)
VOH
Output
50%
50%
VOL
tPLH(1)
tPHL(1)
VOH
Output
50%
50%
VOL
The maximum between tPLH and tPHL is used for tpd.
Figure 7. Voltage Waveforms
Propagation Delays
6
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8 Detailed Description
8.1 Overview
This device contains four independent 2-input AND Gates with Schmitt-trigger inputs. Each gate performs the
Boolean function Y = A ● B in positive logic.
8.2 Functional Block Diagram
One of Four Channels
xA
xY
xB
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device may
create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times.
8.3.2 CMOS Schmitt-Trigger Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics,
which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much slower
than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the inputs slowly
will also increase dynamic current consumption of the device. For additional information regarding Schmitt-trigger
inputs, please see Understanding Schmitt Triggers.
8.3.3 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 8.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
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Feature Description (continued)
Device
VCC
+IIK
+IOK
Logic
Input
-IIK
Output
-IOK
GND
Figure 8. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
Table 1. Function Table
INPUTS
8
A
B
OUTPUT
Y
H
H
H
L
X
L
X
L
L
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
In this application, three 2-input AND gates are combined to produce a 4-input AND gate function as shown in
Figure 9. The fourth gate can be used for another application in the system, or the inputs can be grounded and
the channel left unused.
The SN74HCS08 is used to directly control the RESET pin of a motor controller. The controller requires four
input signals to all be HIGH before being enabled, and should be disabled in the event that any one signal goes
LOW. The 4-input AND gate function combines the four individual reset signals into a single active-low reset
signal.
Many power good signals utilize open-drain outputs which can produce slow input transition rates when they
transition from LOW to Hi-Z mode. This makes the SN74HCS08 ideal for the application because it has Schmitttrigger inputs that do not have input transition rate requirements.
9.2 Typical Application
Over Current
Detection
Power Supply
Motor Controller
OC
PG
RESET
ON/OFF
OT
On/Off Switch
Over
Temp
Detection
Figure 9. Typical application block diagram
9.2.1 Design Requirements
• All signals in the system operate at 5 V
• The motor controller should be disabled if any of these conditions apply:
– Power Supply is not ready (PG)
– Excessive current is detected (OC)
– Excessive temperature is detected (OT)
– The power switch is in the OFF position (ON/OFF)
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the
SN74HCS08 plus the maximum supply current, ICC, listed in the Electrical Characteristics. The logic device can
only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not to
exceed the maximum total current through GND or VCC listed in the Absolute Maximum Ratings.
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Typical Application (continued)
The SN74HCS08 can drive a load with a total capacitance less than or equal to 50 pF connected to a highimpedance CMOS input while still meeting all of the datasheet specifications. Larger capacitive loads can be
applied, however it is not recommended to exceed 70 pF.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings,
is an additional limitation to prevent damage to the device. Do not violate any values
listed in the Absolute Maximum Ratings. These limits are provided to prevent damage
to the device.
9.2.1.2 Input Considerations
Input signals must cross Vt-(min) to be considered a logic LOW, and Vt+(max) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
SN74HCS08, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ resistor
value is often used due to these factors.
The SN74HCS08 has no input signal transition rate requirements because it has Schmitt-trigger inputs.
Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude
can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Electrical
Characteristics. This hysteresis value will provide the peak-to-peak limit.
Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without
causing huge increases in power consumption. The typical additional current caused by holding an input at a
value other than VCC or ground is plotted in the Typical Characteristics.
Refer to the Feature Description for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. Similarly, the
ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the
output voltage as specified by the VOL specification in the Electrical Characteristics.
Unused outputs can be left floating.
Refer to Feature Description for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout.
2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the SN74HCS08
to the receiving device.
3. Ensure the resistive load at the output is larger than (VCC / 25 mA) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
10
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Typical Application (continued)
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation
9.2.3 Application Curves
OC
PG
ON/OFF
OT
RESET
Figure 10. Application timing diagram
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
Figure 11.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example
GND
VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
0.1 F
Avoid 90°
corners for
signal lines
Bypass capacitor
placed close to
the device
1A
1
14
VCC
1B
2
13
4B
4A
1Y
3
12
2A
4
11
4Y
2B
5
10
3B
2Y
6
9
3A
GND
7
8
3Y
Unused inputs
tied to VCC
Unused output
left floating
Figure 11. Example layout for the SN74HCS08
12
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• HCMOS Design Considerations
• CMOS Power Consumption and CPD Calculation
• Designing with Logic
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
12.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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20-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
SN74HCS08PWR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
TSSOP
PW
14
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
HCS08
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
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flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74HCS08 :
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
20-Dec-2019
• Automotive: SN74HCS08-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
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