Texas Instruments | SN74HCS595-Q1 Automotive 8-Bit Shift Register With Schmitt-Trigger Inputs and 3-State Output Registers | Datasheet | Texas Instruments SN74HCS595-Q1 Automotive 8-Bit Shift Register With Schmitt-Trigger Inputs and 3-State Output Registers Datasheet

Texas Instruments SN74HCS595-Q1 Automotive 8-Bit Shift Register With Schmitt-Trigger Inputs and 3-State Output Registers Datasheet
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SN74HCS595-Q1
SCLS785 – DECEMBER 2019
SN74HCS595-Q1 Automotive 8-Bit Shift Register With Schmitt-Trigger Inputs and 3-State
Output Registers
1 Features
3 Description
•
The SN74HCS595-Q1 device contains an 8-bit,
serial-in, parallel-out shift register that feeds an 8-bit
D-type storage register. All inputs include Schmitttriggers, eliminating any erroneous data outputs due
to slow-edged or noisy input signals. The storage
register has parallel 3-state outputs. Separate clocks
are provided for both the shift and storage register.
The shift register has a direct overriding clear
(SRCLR) input, serial (SER) input, and a serial output
(QH') for cascading. When the output-enable (OE)
input is high, the outputs are in a high-impedance
state. Internal register data is not impacted by the
operation of the OE input.
1
•
•
•
•
AEC-Q100 Qualified for automotive applications:
– Device temperature grade 1: –40°C to +125°C,
TA
– Device HBM ESD Classification Level 2
– Device CDM ESD Classifcation Level C6
Wide operating voltage range: 2 V to 6 V
Schmitt-trigger inputs allow for slow or noisy input
signals
Low power consumption
– Typical ICC of 100 nA
– Typical input leakage current of ±100 nA
±7.8-mA output drive at 5 V
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
2 Applications
SN74HCS595QPWRQ1
•
•
•
•
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Output expansion
LED matrix control
7-segment display control
8-bit data storage
TSSOP (14)
5.00 mm x 4.40 mm
Benefits of Schmitt-trigger Inputs
Voltage
Output
Current
Voltage
Current
Output
Input Voltage
Voltage
Output
Voltage
Time
Current
Response
Waveforms
Time
Time
Input Voltage
Output
Schmitt-trigger
CMOS Input
Time
Time
Current
Response
Waveforms
Supply Current
Standard
CMOS Input
Supply Current
Input Voltage
Supports Slow Inputs
Input
Voltage
Noise Rejection
Input
Voltage
Input Voltage
Waveforms
Input
Voltage
Low Power
Time
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74HCS595-Q1
SCLS785 – DECEMBER 2019
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Characteristics...............................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 11
9
Application and Implementation ........................ 12
9.1 Application Information .......................................... 12
9.2 Typical Application ................................................. 12
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 16
12 Device and Documentation Support ................. 17
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
17
17
13 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
2
DATE
REVISION
NOTES
December 2019
*
Initial release.
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5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
QB
1
16
VCC
QC
2
QA
QD
QE
3
15
14
4
13
QF
5
12
RCLK
QG
QH
6
11
SRCLK
7
8
10
SRCLR
QH¶
GND
9
SER
OE
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
QB
1
Output
QB output
QC
2
Output
QC output
QD
3
Output
QD output
QE
4
Output
QE output
QF
5
Output
QF output
QG
6
Output
QG output
QH
7
Output
QH output
GND
8
—
QH'
9
Output
SRCLR
10
Input
Shift register clear, active low
SRCLK
11
Input
Shift register clock, rising edge triggered
RCLK
12
Input
Output register clock, rising edge triggered
OE
13
Input
Output Enable, active low
SER
14
Input
Serial input
QA
15
Output
VCC
16
—
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Ground
Serial output, can be used for cascading
QA output
Positive supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
(2)
MIN
MAX
–0.5
7
UNIT
V
IIK
Input clamp current
VI < –0.5 V or VI > VCC + 0.5 V
±20
mA
IOK
Output clamp current (2)
VI < –0.5 V or VI > VCC + 0.5 V
±20
mA
IO
Continuous output current
VO = 0 to VCC
±35
mA
Continuous current through VCC or GND
±70
mA
TJ
Junction temperature (3)
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Guaranteed by design.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002
HBM ESD Classification Level 2
UNIT
(1)
±4000
V
Charged device model (CDM), per AEC Q100011 CDM ESD Classification Level C6
±1500
AEC Q100-002 indicate that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
5
MAX
UNIT
VCC
Supply voltage
2
6
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
TA
Ambient temperature
–40
125
°C
6.4 Thermal Information
SN74HCS595-Q1
THERMAL METRIC
PW (TSSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
141.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
78.8
°C/W
RθJB
Junction-to-board thermal resistance
85.8
°C/W
ΨJT
Junction-to-top characterization parameter
27.7
°C/W
ΨJB
Junction-to-board characterization parameter
85.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
4
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6.5 Electrical Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
VT+
VT-
ΔVT
VOH
TEST CONDITIONS
Positive switching threshold
Negative switching threshold
Hysteresis (VT+ - VT-)
(1)
High-level output voltage
VI = VIH or VIL
VCC
MIN
TYP
MAX UNIT
2V
0.7
1.5
4.5 V
1.7
3.15
6V
2.1
4.2
2V
0.3
1.0
4.5 V
0.9
2.2
6V
1.2
3.0
2V
0.2
1.0
4.5 V
0.4
1.4
6V
0.6
1.6
IOH = -20 µA
2 V to 6 V
VCC – 0.1
IOH = -6 mA
4.5 V
4.0
4.3
IOH = -7.8 mA
6V
5.4
5.75
IOL = 20 µA
2 V to 6 V
IOL = 6 mA
4.5 V
IOL = 7.8 mA
V
V
V
VCC – 0.002
V
0.002
0.1
0.18
0.30
VOL
Low-level output voltage
VI = VIH or VIL
6V
0.22
0.33
II
Input leakage current
VI = VCC or 0
6V
±100
±1000
nA
ICC
Supply current
VI = VCC or 0, IO = 0
6V
0.1
2
µA
Ci
Input capacitance
5
pF
Cpd
Power dissipation capacitance
per gate
(1)
2 V to 6 V
No load
2 V to 6 V
40
V
pF
Guaranteed by design.
6.6 Timing Characteristics
CL = 50 pF; over operating free-air temperature range (unless otherwise noted). See Parameter Measurement Information.
Operating free-air temperature (TA)
PARAMETER
VCC
25°C
MIN
SRCLK or RCLK
high or low
tw
Pulse duration
SRCLR low
SER before
SRCLK↑
SRCLK↑ before
RCLK↑
tsu
Setup time
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MAX
MIN
2V
7
9
4.5 V
7
7
6V
7
7
2V
8
10
4.5 V
7
7
6V
7
7
2V
8
13
4.5 V
4
5
6V
3
4
2V
11
18
4.5 V
5
7
6V
4
6
2V
8
13
4
6
SRCLR low before
4.5 V
RCLK↑
6V
SRCLR high
(inactive) before
SRCLK↑
–40°C to 125°C
4
5
2V
8
13
4.5 V
4
6
6V
4
5
UNIT
MAX
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ns
5
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Timing Characteristics (continued)
CL = 50 pF; over operating free-air temperature range (unless otherwise noted). See Parameter Measurement Information.
Operating free-air temperature (TA)
PARAMETER
VCC
25°C
MIN
2V
th
SER after SRCLK↑ 4.5 V
Hold time
6V
–40°C to 125°C
MAX
MIN
0
0
0
0
0
0
UNIT
MAX
ns
6.7 Switching Characteristics
CL = 50 pF; over operating free-air temperature range (unless otherwise noted). See Parameter Measurement Information.
Operating free-air temperature (TA)
PARAMETER
FROM
TO
VCC
25°C
MIN
2V
fmax
Max switching frequency
tpd
Propagation delay
RCLK
tPHL
ten
tdis
QH'
Propagation delay
Enable time
Disable time
SRCLR
OE
OE
QA - QH
QH'
QA - QH
QA - QH
Transition-time
35
19
60
6V
130
75
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TYP
UNIT
MAX
MHz
14
19
28
4.5 V
6
8
10
6V
5
7
9
2V
16
21
37
4.5 V
6
9
12
6V
6
8
10
2V
13
19
27
4.5 V
6
8
11
6V
6
8
10
2V
12
18
27
4.5 V
6
9
13
6V
5
8
11
2V
13
16
20
4.5 V
9
11
13
6V
8
10
12
9
16
5
9
4
8
Any output 4.5 V
6V
6
MIN
110
2V
tt
–40°C to 125°C
MAX
4.5 V
2V
SRCLK
TYP
ns
ns
ns
ns
ns
ns
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6.8 Typical Characteristics
TA = 25°C
70
46
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
Output Resistance (:)
42
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
65
Output Resistance (:)
44
40
38
36
34
32
60
55
50
45
40
30
35
28
26
30
0
2.5
5
7.5 10 12.5 15 17.5
Output Sink Current (mA)
20
22.5
25
Figure 1. Output driver resistance in LOW state.
0
ICC ± Supply Current (mA)
VCC = 2.5 V
0.14
VCC = 3.3 V
ICC ± Supply Current (mA)
VCC = 2 V
0.16
0.12
0.1
0.08
0.06
0.04
0.02
0
0
0.5
1
1.5
2
2.5
VI ± Input Voltage (V)
3
3.5
Figure 3. Supply current across input voltage, 2-,
2.5-, and 3.3-V supply
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5
7.5 10 12.5 15 17.5
Output Source Current (mA)
20
22.5
25
Figure 2. Output driver resistance in HIGH state.
0.2
0.18
2.5
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
VCC = 4.5 V
VCC = 5 V
VCC = 6 V
0
0.5
1
1.5
2 2.5 3 3.5 4
VI ± Input Voltage (V)
4.5
5
5.5
6
Figure 4. Supply current across input voltage, 4.5-,
5-, and 6-V supply
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7 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 2.5 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
VCC
RL
From Output
Under Test
tw
VCC
Test
Point
S1
Input
50%
50%
0V
Figure 6. Voltage Waveforms, Pulse Duration
CL(1)
S2
CL includes probe and test-fixture capacitance.
Figure 5. Load Circuit
VCC
VCC
Clock
Input
50%
Input
50%
50%
0V
tsu
0V
tPHL(1)
tPLH(1)
th
VCC
Data
Input
50%
VOH
50%
Output
50%
50%
0V
VOL
Figure 7. Voltage Waveforms, Setup and Hold Times
tPLH(1)
tPHL(1)
VOH
Output
50%
50%
VOL
Voltage Waveforms, Propagation Delay specifications tPLH and tPHL
are the same as tpd.
Figure 8. Voltage Waveforms, Propagation Delays
90%
VCC
90%
Input
10%
10%
tf
tr
90%
0V
90%
VOH
Output
10%
tr
10%
tf
VOL
Figure 9. Voltage Waveforms, Input and Output Transition Times
8
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8 Detailed Description
8.1 Overview
Figure 10 describes the SN74HCS595-Q1, an 8-bit shift register that feeds an 8-bit D-type storage register. Both
the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are
connected together, the shift register always is one clock pulse ahead of the storage register. All inputs include
Schmitt-triggers allowing for slow input transitions and providing more noise margin.
8.2 Functional Block Diagram
OE
RCLK
SRCLR
SRCLK
SER
13
12
10
11
14
D
Q
D
Q
15
QA
R
D
Q
D
Q
1
QB
R
2
QC
3
QD
4
QE
5
QF
6
QG
D
Q
D
Q
7
QH
R
9
QH¶
Figure 10. Logic Diagram (Positive Logic) for SN74HCS595-Q1
8.3 Feature Description
8.3.1 Balanced CMOS 3-State Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device may
create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times.
3-State outputs can be placed into a high-impedance state. In this state, the output will neither source nor sink
current, and leakage current is defined by the IOZ specification in the Electrical Characteristics. A pull-up or pulldown resistor can be used to ensure that the output remains HIGH or LOW, respectively, during the highimpedance state.
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Feature Description (continued)
8.3.2 CMOS Schmitt-Trigger Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics,
which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much slower
than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the inputs slowly
will also increase dynamic current consumption of the device. For additional information regarding Schmitt-trigger
inputs, please see Understanding Schmitt Triggers.
8.3.3 Positive and Negative Clamping Diodes
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 11.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
Device
VCC
+IIK
+IOK
Logic
Input
-IIK
Output
-IOK
GND
Figure 11. Electrical Placement of Clamping Diodes for Each Input and Output
10
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8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74HCS595-Q1.
Table 1. Function Table
INPUTS
SER
SRCLK SRCLR
FUNCTION
RCLK
OE
H
Outputs QA – QH are disabled.
X
X
X
X
X
X
X
X
L
Outputs QA – QH are enabled.
X
X
L
X
X
Shift register is cleared.
L
↑
H
X
X
First stage of the shift register goes low.
Other stages store the data of previous stage,
respectively.
H
↑
H
X
X
First stage of the shift register goes high.
Other stages store the data of previous stage,
respectively.
X
X
H
↑
X
Shift-register data is stored in the storage register.
X
↑
H
↑
X
Data in shift register is stored in the storage register, the
data is then shifted through
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
In this application, the SN74HCS595-Q1 is used to control seven-segment displays. Utilizing the serial output
and combining a few of the input signals, this implementation reduces the number of I/O pins required to control
the displays from sixteen to four. Unlike other I/O expanders, the SN74HCS595-Q1 does not need a
communication interface for control. It can be easily operated with simple GPIO pins.
The OE pin is used to easily disable the outputs when the displays need to be turned off or connected to a PWM
signal to control brightness. However, this pin can be tied low and the outputs of the SN74HCS595-Q1 can be
controlled accordingly to turn off all the outputs reducing the I/O needed to three. There is no practical limitation
to how many SN74HCS595-Q1 devices can be cascaded. To add more, the serial output will need to be
connected to the following serial input and the clocks will need to be connected accordingly. With separate
control for the shift registers and output registers, the desired digit can be displayed while the data for the next
digit is loaded into the shift register.
At power-up, the initial state of the shift registers and output registers are unknown. To give them a defined state,
the shift register needs to be cleared and then clocked into the output register. An RC can be connected to the
SRCLR pin as shown in Figure 12 to initialize the shift register to all zeros. With the OE pin pulled up with a
resistor, this process can be performed while the outputs are in a high impedance state eliminating any
erroneous data causing issues with the displays.
9.2 Typical Application
VCC
VCC
R1
SRCLR
C1
MCU
Seven Segment
QA
g
QB
f
f
QC
a
SER
QD
b
SRCLK
QE
DP
RCLK
OE
GND
a
QF
c
QG
d
QH
e
b
g
e
c
d
DP
QH¶
VCC
VCC
Seven Segment
QA
g
QB
f
QC
a
SER
QD
b
SRCLK
QE
DP
R2
SRCLR
C2
RCLK
OE
GND
a
f
QF
c
QG
d
QH
e
b
g
e
c
d
DP
QH¶
Figure 12. Output Expansion for 7-segment Display control
12
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Typical Application (continued)
9.2.1 Design Requirements
•
•
•
•
All signals in the system operate at 5 V
The RC values for the SRCLR pin should be chosen such that the signal doesn't reach Vt+(min) until the
supply settles
The resistors at the outputs should be chosen such that the total current through the VCC or GND pin doesn't
exceed the maximum value in Absolute Maximum Ratings
Follow timing requirements given in Timing Characteristics
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the
SN74HCS595-Q1 plus the maximum supply current, ICC, listed in the Electrical Characteristics. The logic device
can only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not
to exceed the maximum total current through GND or VCC listed in the Absolute Maximum Ratings.
The SN74HCS595-Q1 can drive a load with a total capacitance less than or equal to 50 pF connected to a highimpedance CMOS input while still meeting all of the datasheet specifications. Larger capacitive loads can be
applied, however it is not recommended to exceed 70 pF.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings,
is an additional limitation to prevent damage to the device. Do not violate any values
listed in the Absolute Maximum Ratings. These limits are provided to prevent damage
to the device.
9.2.1.2 Input Considerations
Input signals must cross Vt-(min) to be considered a logic LOW, and Vt+(max) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
SN74HCS595-Q1, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
The SN74HCS595-Q1 has no input signal transition rate requirements because it has Schmitt-trigger inputs.
Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude
can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Electrical
Characteristics. This hysteresis value will provide the peak-to-peak limit.
Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without
causing huge increases in power consumption. The typical additional current caused by holding an input at a
value other than VCC or ground is plotted in the .
Refer to the Feature Description for additional information regarding the inputs for this device.
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Typical Application (continued)
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. Similarly, the
ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the
output voltage as specified by the VOL specification in the Electrical Characteristics.
Unused outputs can be left floating.
Refer to Feature Description for additional information regarding the outputs for this device.
9.2.1.4 Timing Considerations
The SN74HCS595-Q1 is a clocked device. As such, it requires special timing considerations to ensure normal
operation.
Primary timing factors to consider:
• Maximum clock frequency: the maximum operating clock frequency defined in Timing Characteristics is the
maximum frequency at which the device is guaranteed to function. This value refers specifically to the
triggering waveform, measuring from one trigger level to the next.
• Pulse duration: ensure that the triggering event duration is larger than the minimum pulse duration, as defined
in the Timing Characteristics.
• Setup time: ensure that the data has changed at least one setup time prior to the triggering event, as defined
in the Timing Characteristics.
• Hold time: ensure that the data remains in the desired state at least one hold time after the triggering event,
as defined in the Timing Characteristics.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– Input signals to Schmitt-trigger inputs, like those found on the HCS family of devices, can support
unlimited edge rates.
– Input thresholds are listed in the Electrical Characteristics.
– Inputs include positive clamp diodes. Input voltages can exceed the device's supply so long as the clamp
current ratings are observed from the Absolute Maximum Ratings. Do not exceed the absolute maximum
voltage rating of the device or it could be damaged.
2. Recommended Output Conditions:
– Load currents should not exceed the value listed in the Absolute Maximum Ratings.
– Series resistors on the output may be used if the user desires to slow the output edge signal or limit the
output current.
9.2.3 Application Curve
Figure 13 illustrates the functionality of the SN74HCS595-Q1.
14
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SCLS785 – DECEMBER 2019
Typical Application (continued)
SER
QA
QB
QC
QC
QD
QE
QF
Output Registers
QB
Serial Registers
Output Registers
QA
Serial Registers
SER
QD
QE
QF
QG
QG
QH
QH
QH¶
QH¶
SRCLK rising edge shifts data
in the serial registers only
RCLK rising edge shifts data
to the output registers
Figure 13. Simplified Functionality of the SN74HCS595-Q1 Registers
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Absolute Maximum Ratings table. Each VCC terminal should have a bypass capacitor to prevent power
disturbance. For this device, a 0.1-μF capacitor is recommended. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminals as possible for best results.
11 Layout
11.1 Layout Guidelines
In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only
two inputs of a triple-input AND gate are used, or when only 3 of the 4 channels are used. Such input pins should
not be left completely unconnected because the unknown voltages result in undefined operational states.
Specified in Figure 14 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that must be
applied to any particular unused input depends on the function of the device. Generally they are tied to GND or
VCC, whichever makes more sense or is more convenient. It is recommended to float outputs unless the part is a
transceiver. If the transceiver has an output enable pin, it disables the output section of the part when asserted.
This pin keeps the input section of the I/Os from being disabled and floated.
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11.2 Layout Example
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
Unused inputs tie to GND or VCC
Avoid 90°
corners for
signal lines
GND VCC
0.1 F
Bypass capacitor
placed close to
the device
QB
1
16
VCC
QC
2
15
QA
QD
3
14
SER
QE
4
13
OE
QF
5
12
RCLK
QG
6
11
SRCLK
QH
7
10
GND
8
9
SRCLR
QH¶
Unused output
left floating
Figure 14. Layout Example
16
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Documentation Support
12.1.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
• Texas Instruments, Reduce Noise and Save Power with the New HCS Logic Family application report
• Texas Instruments, Understanding Schmitt Triggers application report
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74HCS595QDRQ1
PREVIEW
SOIC
D
16
2500
TBD
Call TI
Call TI
-40 to 125
SN74HCS595QPWRQ1
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HCS595Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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