Texas Instruments | SN74LVC1G18 1-of-2 Noninverting Demultiplexer With 3-State Deselected Output (Rev. L) | Datasheet | Texas Instruments SN74LVC1G18 1-of-2 Noninverting Demultiplexer With 3-State Deselected Output (Rev. L) Datasheet

Texas Instruments SN74LVC1G18 1-of-2 Noninverting Demultiplexer With 3-State Deselected Output (Rev. L) Datasheet
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SN74LVC1G18
SCES406L – JULY 2002 – REVISED AUGUST 2019
SN74LVC1G18 1-of-2 Noninverting Demultiplexer With 3-State Deselected Output
1 Features
3 Description
•
•
•
•
•
•
•
•
This non-inverting demultiplexer is designed for 1.65V to 5.5-V VCC operation.
1
•
•
•
•
Operating temperature from –40°C to +125°C
Supports 5-V VCC operation
Inputs accept voltages to 5.5 V
Supports down translation to VCC
Max tpd of 3.4 ns at 3.3 V
Low power consumption, 10-µA max ICC
±24-mA Output drive at 3.3 V
Typical VOLP (output ground bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (output VOH undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports live insertion, partial-power-down
mode, and back-drive protection
Latch-up performance exceeds 100 mA
Per JESD 78, Class II
ESD protection exceeds JESD 22
– 2000-V Human-body model (A114-A)
– 200-V machine model (A115-A)
– 1000-V Charged-device model (C101)
2 Applications
•
•
•
•
•
•
•
•
•
•
•
The SN74LVC1G18 device is a 1-of-2 non-inverting
demultiplexer with a 3-state output. This device
buffers the data on input A and passes it to either
output Y0 or Y1, depending on whether the state of
the select (S) input is low or high, respectively.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LVC1G18DBVR
SOT-23 (6)
2.90 mm × 2.80 mm
SN74LVC1G18DCKR
SC70 (6)
2.00 mm × 1.10 mm
SN74LVC1G18DRYR
SON (6)
1.45 mm × 1.00 mm
SN74LVC1G18DSFR
SON (6)
1.00 mm × 1.00 mm
SN74LVC1G18YZPR
DSBGA (6)
1.39 mm × 0.89 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Data center switch
Baseband unit (BBU)
Wi-Fi access point
Notebook PC
Active antenna system (AAS)
Appliances
Industrial monitor
Coffee machine
Wired speaker
Vacuum robot
Professional audio interface
Simplified Schematic
6
S
A
Y0
1
3
4
Y1
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G18
SCES406L – JULY 2002 – REVISED AUGUST 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
5
5
6
6
7
7
7
8
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, –40 to 85°C ....................
Switching Characteristics, –40 to 125°C...................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 12
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application .................................................. 13
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 16
12 Device and Documentation Support ................. 17
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
17
13 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (July 2012) to Revision L
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Updated Ioff in Features. ......................................................................................................................................................... 1
•
Added Applications. ................................................................................................................................................................ 1
•
Added Device Information table. ............................................................................................................................................ 1
•
Added Operating junction temperature................................................................................................................................... 5
•
Added Handling Ratings table. ............................................................................................................................................... 5
•
Added Thermal Information table. .......................................................................................................................................... 6
2
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5 Pin Configuration and Functions
DRY and DSF Package
6-Pin SON
Transparent Top View
S
GND
A
1
6
2
5
3
4
YZP Package
6-Pin DSBGA
Bottom View
Y0
VCC
Y1
A
GND
S
C1
C2
B1
B2
A1
A2
Y1
VCC
Y0
DBV and DCK Package
6-Pin SOT-23 and SC70
Top View
S
1
6
Y0
GND
2
5
VCC
A
3
4
Y1
Not to scale. See the mechanical drawings at the end of the data sheet for package dimensions.
Pin Functions
PIN
NAME
DBV, DCK,
DRY, DSF
YZP
I/O
DESCRIPTION
S
1
A1
Input
GND
2
B1
—
Active output selection (LOW = Y0, HIGH = Y1)
Ground
A
3
C1
Input
Input A
Y1
4
C2
Output
VCC
5
B2
—
Y0
6
A2
Output
Output Y1
Positive supply
Output Y0
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Logic Diagram (Positive Logic)
6
S
A
4
Y0
1
3
4
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Y1
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
UNIT
V
(2)
VI
Input voltage range
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (3)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2) (1)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
150
°C
150
°C
Continuous current through VCC or GND
TJ
Operating junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged device model (CDM), per JEDEC specification JESD22-C101
2000
(2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Operating
Supply voltage
MAX
1.65
5.5
Data retention only
1.7
VCC = 3 V to 3.6 V
0.7 × VCC
VCC = 1.65 V to 1.95 V
Low-level input voltage
V
2
VCC = 4.5 V to 5.5 V
VIL
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
High-level input voltage
UNIT
1.5
VCC = 1.65 V to 1.95 V
VIH
MIN
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VCC = 4.5 V to 5.5 V
V
0.3 × VCC
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
VCC = 1.65 V
–4
VCC = 2.3 V
–8
–16
VCC = 3 V
VCC = 4.5 V
–32
VCC = 1.65 V
4
VCC = 2.3 V
IOL
Low-level output current
8
16
VCC = 3 V
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
mA
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
(1)
mA
–24
ns/V
5
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6.4 Thermal Information
SN74LVC1G18
THERMAL METRIC
(1)
DBV
DCK
DRY
DSF
YZP
6 PINS
6 PINS
6 PINS
6 PINS
6 PINS
236.1
278.7
306.7
300.3
123.8
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
174.0
217.8
207.2
183.5
1.4
°C/W
RθJB
Junction-to-board thermal resistance
111.5
124.6
181.1
170.7
38.9
°C/W
ψJT
Junction-to-top characterization parameter
93.5
105.2
49.9
24.2
0.5
°C/W
ψJB
Junction-to-board characterization parameter
111.2
124.1
180.3
170.2
38.9
°C/W
N/A
N/A
N/A
N/A
N/A
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(bot) Junction-to-case (bottom) thermal resistance
(1)
6
UNIT
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
-40 to 85°C
PARAMETE
R
TEST CONDITIONS
VCC
1.65 V to
5.5 V
IOH = –100 µA
VOH
1.2
1.9
1.9
2.4
2.4
2.3
2.3
3.8
3.8
MAX
4.5 V
IOL = 100 µA
1.65 V to
5.5 V
0.1
0.1
IOL = 4 mA
1.65 V
0.45
0.45
IOL = 8 mA
2.3 V
0.3
0.3
0.4
0.4
0.55
0.55
0.55
0.55
3V
4.5 V
VI = 5.5 V or GND
Ioff
VI or VO = 5.5 V
IOZ
VO = 0 to 5.5 V
UNIT
V
IOH = –32 mA
IOL = 32 mA
(1)
VCC –
0.1
1.2
IOL = 24 mA
ΔICC
VCC –
0.1
2.3 V
3V
TYP (1)
MIN
1.65 V
IOL = 16 mA
ICC
MAX
IOH = –8 mA
IOH = –24 mA
II
TYP (1)
IOH = –4 mA
IOH = –16 mA
VOL
MIN
-40 to 125°C
V
0 to 5.5 V
±5
±5
µA
0
±10
±10
µA
3.6 V
10
10
µA
10
10
µA
500
500
µA
VI = 5.5 V or GND,
IO = 0
1.65 V to
5.5 V
One input at
VCC – 0.6 V,
Other inputs at VCC or
GND
3 V to 5.5
V
CI
VI = VCC or GND
3.3 V
4
4
pF
Co
VO = VCC or GND
3.3 V
6
6
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
6.6 Switching Characteristics, –40 to 85°C
TA = –40 to 85°C, CL = 30 pF or 50 pF (unless otherwise noted) (see Parameter Measurement Information)
PARA
METER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
S
tdis
S
CONDITION
VCC = 1.8 V
± 0.15 V
MIN MAX
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
MIN MAX
MIN MAX
VCC = 5 V
± 0.5 V
UNIT
MIN MAX
CL = 15 pF
2.3
8.4
1.1
4.2
1.1
3.4
0.8
2.7
ns
CL = 30 pF or 50 pF
3.5
9.3
1.7
5
1.5
4.2
0.7
3.2
ns
Y
CL = 30 pF or 50 pF
3.6
10.2
1.7
5.6
1.5
4.6
0.9
3.4
ns
Y
CL = 30 pF or 50 pF
1.9
12.7
1
5.3
1.1
4.9
0.5
3.3
ns
6.7 Switching Characteristics, –40 to 125°C
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Parameter
Measurement Information)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V VCC = 3.3 V
± 0.2 V
± 0.3 V
VCC = 5 V
± 0.5 V
PARA
METER
FROM
(INPUT)
TO
(OUTPUT)
CONDITION
tpd
A
Y
CL = 30 pF or 50 pF
3.5
9.8
1.7
5.5
1.5
4.7
0.7
3.7
ns
ten
S
Y
CL = 30 pF or 50 pF
3.6
11.2
1.7
6.6
1.5
6.1
0.9
4.9
ns
tdis
S
Y
CL = 30 pF or 50 pF
1.9
13.7
1
6.3
1.1
6.4
0.5
4.8
ns
MIN MAX
MIN MAX
MIN MAX
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UNIT
MIN MAX
7
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6.8 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST
CONDITIONS
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
f = 10 MHz
17
17
18
21
UNIT
pF
6.9 Typical Characteristics
0.5
5
0.45
4.5
0.4
0.35
0.3
0.25
0.2
0.15
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
0.1
0.05
0
0
4
8
12
16
20
24
28
32
IOL, Low-level output current (mA)
36
40
Figure 1. Typical low-level output voltage at common supply
values and currents
8
VOH, High-level output voltage (V)
VOL, Low output voltage (V)
TA = 25°C; Simulated data
4
3.5
3
2.5
2
1.5
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
1
0.5
0
0
5
10
15
20
25
30
35
40
IOH, High-level output current (mA)
45
50
Figure 2. Typical high-level output voltage at common
supply values and currents
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
15 pF
15 pF
15 pF
15 pF
1 MW
1 MW
1 MW
1 MW
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
10
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8 Detailed Description
8.1 Overview
This device contains one independent 1-of-2 noninverting demultiplexer with high-impedance outputs when
disabled.
8.2 Functional Block Diagram
6
S
A
Y0
1
3
4
Y1
8.3 Feature Description
8.3.1 Balanced CMOS 3-State Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device may
create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times.
3-State outputs can be placed into a high-impedance state. In this state, the output will neither source nor sink
current, and leakage current is defined by the IOZ specification in the Electrical Characteristics. A pull-up or pulldown resistor can be used to ensure that the output remains HIGH or LOW, respectively, during the highimpedance state.
8.3.2 Partial Power Down (Ioff)
The inputs and outputs for this device enter a high-impedance state when the device is powered down, inhibiting
current backflow into the device. The maximum leakage into or out of any input or output pin on the device is
specified by Ioff in the Electrical Characteristics.
8.3.3 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings , and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in the Recommended Operating
Conditions to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a
device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.
8.3.4 Over-voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Recommended Operating Conditions .
8.3.5 Clamp Diode Structure
The inputs and outputs to this device have negative clamping diodes only as depicted in Figure 5.
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Feature Description (continued)
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
VCC
Device
Logic
Input
Output
-IIK
-IOK
GND
Figure 5. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
Table 1. Function Table
INPUTS
12
OUTPUTS
S
A
Y0
Y1
L
L
L
Z
L
H
H
Z
H
L
Z
L
H
H
Z
H
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC1G18 can be used to select between controlling two analog switches. In this use case, pull-down
resistors are connected to both outputs of the SN74LVC1G18 to ensure that a valid state is available for the
inputs to the switches at all times. This defaults the switches into the "off" state to prevent unwanted data
transmission.
9.2 Typical Application
SN74LVC1G18
VCC
0.1 F
Y0
10 k
S
System
Controller
A
Analog
Switches
Y1
10 k
Figure 6. Typical application block diagram
9.2.1 Design Requirements
• Each analog switch must be controlled by the system controller, but only when the other switch is disabled.
• When the input S is low, the Y0 output is selected and the Y1 output is in the high impedance state
• When the input S is high, the Y1 output is selected and the Y0 output is in the high impedance state
• When the input A is high, the selected analog switch must be closed
• When the input A is low, the selected analog switch must be open
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions . The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the
SN74LVC1G18 plus the maximum supply current, ICC, listed in the Electrical Characteristics. The logic device
can only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not
to exceed the maximum total current through GND or VCC listed in the Absolute Maximum Ratings .
The SN74LVC1G18 can drive a load with a total capacitance less than or equal to 50 pF connected to a highimpedance CMOS input while still meeting all of the datasheet specifications. Larger capacitive loads can be
applied, however it is not recommended to exceed 70 pF.
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Typical Application (continued)
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings ,
is an additional limitation to prevent damage to the device. Do not violate any values
listed in the Absolute Maximum Ratings . These limits are provided to prevent damage
to the device.
9.2.1.2 Input Considerations
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
SN74LVC1G18, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
The SN74LVC1G18 has standard CMOS inputs, so input signal edge rates cannot be slow. Slow input edge
rates can cause oscillations and damaging shoot-through current. The recommended rates are defined in the
Recommended Operating Conditions .
Refer to the Feature Description for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. Similarly, the
ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the
output voltage as specified by the VOL specification in the Electrical Characteristics. The plots in the Typical
Characteristics provide a relationship between output voltage and current for this device.
Unused outputs can be left floating.
Refer to Feature Description for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout.
2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the
SN74LVC1G18 to the receiving device.
3. Ensure the resistive load at the output is larger than (VCC / 25 mA) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation
14
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Typical Application (continued)
9.2.3 Application Curves
Figure 7. Simulated application transient response
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions . Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
Figure 8.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example
VCC
Avoid 90°
corners for
signal lines
A1
A2
GND
S
Unused output
left floating
0.1 F
GND
B1
B2
VCC
A
C1
C2
Y1
Unused
input tied
to GND
Bypass capacitor placed
close to the device
Figure 8. Example layout for the SN74LVC1G18
16
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Implications of Slow or Floating CMOS Inputs
• CMOS Power Consumption and Cpd Calculation
• Understanding and Interpreting Standard-Logic Data Sheets
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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17
PACKAGE OPTION ADDENDUM
www.ti.com
4-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LVC1G18DBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(C185, C18R)
SN74LVC1G18DBVRG4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(C185, C18R)
SN74LVC1G18DCKR
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
(CJ5, CJF, CJJ, CJ
K, CJR)
SN74LVC1G18DCKRE4
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CJ5
SN74LVC1G18DCKRG4
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CJ5
SN74LVC1G18DRYR
ACTIVE
SON
DRY
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CJ
SN74LVC1G18DSFR
ACTIVE
SON
DSF
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CJ
SN74LVC1G18YZPR
ACTIVE
DSBGA
YZP
6
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
CJN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Apr-2019
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
SN74LVC1G18DBVR
SOT-23
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DBV
6
3000
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
SN74LVC1G18DBVR
SOT-23
DBV
6
3000
178.0
9.2
3.3
3.23
1.55
4.0
8.0
Q3
SN74LVC1G18DCKR
SC70
DCK
6
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
SN74LVC1G18DCKR
SC70
DCK
6
3000
180.0
8.4
2.41
2.41
1.2
4.0
8.0
Q3
SN74LVC1G18DCKR
SC70
DCK
6
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
SN74LVC1G18DCKR
SC70
DCK
6
3000
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74LVC1G18DCKRG4
SC70
DCK
6
3000
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74LVC1G18DRYR
SON
DRY
6
5000
180.0
9.5
1.15
1.6
0.75
4.0
8.0
Q1
SN74LVC1G18DSFR
SON
DSF
6
5000
180.0
9.5
1.16
1.16
0.5
4.0
8.0
Q2
SN74LVC1G18YZPR
DSBGA
YZP
6
3000
178.0
9.2
1.02
1.52
0.63
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC1G18DBVR
SOT-23
DBV
6
3000
202.0
201.0
28.0
SN74LVC1G18DBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
SN74LVC1G18DCKR
SC70
DCK
6
3000
180.0
180.0
18.0
SN74LVC1G18DCKR
SC70
DCK
6
3000
202.0
201.0
28.0
SN74LVC1G18DCKR
SC70
DCK
6
3000
180.0
180.0
18.0
SN74LVC1G18DCKR
SC70
DCK
6
3000
180.0
180.0
18.0
SN74LVC1G18DCKRG4
SC70
DCK
6
3000
180.0
180.0
18.0
SN74LVC1G18DRYR
SON
DRY
6
5000
184.0
184.0
19.0
SN74LVC1G18DSFR
SON
DSF
6
5000
184.0
184.0
19.0
SN74LVC1G18YZPR
DSBGA
YZP
6
3000
220.0
220.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRY 6
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4207181/G
PACKAGE OUTLINE
DRY0006A
USON - 0.6 mm max height
SCALE 8.500
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
B
A
PIN 1 INDEX AREA
1.5
1.4
C
0.6 MAX
SEATING PLANE
0.05
0.00
0.08 C
3X 0.6
SYMM
(0.127) TYP
(0.05) TYP
3
4
4X
0.5
SYMM
2X
1
1
6
6X
0.4
0.3
PIN 1 ID
(OPTIONAL)
5X
0.25
0.15
0.1
0.05
0.35
0.25
C A B
C
4222894/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DRY0006A
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
6
1
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
LAND PATTERN EXAMPLE
1:1 RATIO WITH PKG SOLDER PADS
EXPOSED METAL SHOWN
SCALE:40X
0.05 MAX
ALL AROUND
EXPOSED
METAL
0.05 MIN
ALL AROUND
EXPOSED
METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222894/A 01/2018
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DRY0006A
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
1
6
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X
4222894/A 01/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
6
2X 0.95
1.9
1.45 MAX
3.05
2.75
5
2
4
0.50
6X
0.25
0.2
C A B
3
(1.1)
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X (0.95)
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214840/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X(0.95)
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DSF0006A
X2SON - 0.4 mm max height
SCALE 10.000
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
B
A
PIN 1 INDEX AREA
1.05
0.95
0.4 MAX
C
SEATING PLANE
0.05 C
(0.11) TYP
SYMM
0.05
0.00
3
4
SYMM
2X
0.7
4X
0.35
6
1
6X
(0.1)
PIN 1 ID
6X
0.45
0.35
0.22
0.12
0.07
0.05
C B A
C
4220597/A 06/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MO-287, variation X2AAF.
www.ti.com
EXAMPLE BOARD LAYOUT
DSF0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.6)
(R0.05) TYP
1
6X (0.17)
6
SYMM
4X (0.35)
4
3
SYMM
(0.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:40X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220597/A 06/2017
NOTES: (continued)
4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DSF0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.6)
(R0.05) TYP
1
6
6X (0.17)
SYMM
4X (0.35)
4
3
SYMM
(0.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:40X
4220597/A 06/2017
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
YZP0006
DSBGA - 0.5 mm max height
SCALE 9.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.19
0.15
BALL TYP
0.05 C
0.5 TYP
C
SYMM
1
TYP
B
0.5
TYP
D: Max = 1.418 mm, Min =1.357 mm
E: Max = 0.918 mm, Min =0.857 mm
A
6X
0.015
0.25
0.21
C A
B
1
2
SYMM
4219524/A 06/2014
NanoFree Is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
TM
3. NanoFree package configuration.
www.ti.com
EXAMPLE BOARD LAYOUT
YZP0006
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
6X ( 0.225)
1
2
A
(0.5) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
( 0.225)
METAL
0.05 MAX
METAL
UNDER
MASK
0.05 MIN
( 0.225)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4219524/A 06/2014
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017).
www.ti.com
EXAMPLE STENCIL DESIGN
YZP0006
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
6X ( 0.25)
(R0.05) TYP
2
1
A
(0.5)
TYP
SYMM
B
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4219524/A 06/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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