Texas Instruments | SN74LVC1G08-Q1 Single 2-input positive-AND gate (Rev. G) | Datasheet | Texas Instruments SN74LVC1G08-Q1 Single 2-input positive-AND gate (Rev. G) Datasheet

Texas Instruments SN74LVC1G08-Q1 Single 2-input positive-AND gate (Rev. G) Datasheet
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SN74LVC1G08-Q1
SCES556G – MARCH 2004 – REVISED JUNE 2019
SN74LVC1G08-Q1 Single 2-input positive-AND gate
1 Features
3 Description
•
This single 2-input positive-AND gate is designed for
1.65-V to 5.5-V VCC operation.
1
•
•
•
•
•
•
•
•
AEC-Q100 Qualified for Automotive Applications:
– Device Temperature Grade 1: –40°C to
+125°C, TA
Supports 5-V VCC Operation
Over-voltage Tolerant Inputs Accept Voltages to
5.5 V
Provides Down Translation to VCC
Low Power Consumption, 10-μA Max ICC
±24-mA Output Drive at 3.3 V
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back Drive Protection
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
2 Applications
•
•
•
•
Fully qualified for automotive applications
Combine power good signals for multiple power
rails
Prevent a signal from being passed until a
condition is true
Combine active-low error signals
The SN74LVC1G08-Q1 device performs the Boolean
function or Y = A • B or Y = A + B in positive logic.
This device is fully specified for partial-power-down
applications using I off. The I off circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
The CMOS device has high output drive while
maintaining low static power dissipation over a broad
VCC operating range.
The SN74LVC1G08 is available in a variety of
packages, including the small DRY package with a
body size of 1.45 mm × 1.00 mm.
white space
white space
Device Information(1)
DEVICE NAME
SN74LVC1G08Q
PACKAGE
BODY SIZE
SOT-23 (5)
2.90mm × 1.60mm
SC70 (5)
2.00mm × 1.25mm
SON (6)
1.45mm × 1.00mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G08-Q1
SCES556G – MARCH 2004 – REVISED JUNE 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
5
5
6
6
6
6
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, TA = –40°C to 125°C ......
Switching Characteristics, TA = –40°C to 85°C ........
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description ............................................ 10
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
10
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 12
11.1 Layout Guidelines ................................................. 12
11.2 Layout Example .................................................... 12
12 Device and Documentation Support ................. 13
12.1 Trademarks ........................................................... 13
12.2 Electrostatic Discharge Caution ............................ 13
12.3 Glossary ................................................................ 13
13 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (April 2008) to Revision G
Page
•
Changed data sheet to new TI format ................................................................................................................................... 1
•
Added DRY package to Device Information table. ................................................................................................................. 1
•
Added Thermal Information table. ......................................................................................................................................... 5
•
Added Typical Characteristics. .............................................................................................................................................. 7
•
Added Detailed Description section. .................................................................................................................................... 10
•
Added Application and Implementation section. ................................................................................................................. 11
•
Added Power Supply Recommendations section. .............................................................................................................. 12
•
Added Layout section. ......................................................................................................................................................... 12
2
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SCES556G – MARCH 2004 – REVISED JUNE 2019
5 Pin Configuration and Functions
DBV package
5-pin SOT-23
(Top View)
A
B
GND
1
DCK package
5-pin SC-70
(Top View)
VCC
5
A
1
B
2
GND
3
5
VCC
4
Y
2
3
Y
4
DRY package
6-pin SON
(Top View)
A
1
6
VCC
B
2
5
NC
GND
3
4
Y
NC – No internal connection
See mechanical drawings for dimensions.
Pin Functions
PIN
NAME
NO.
DBV,
DCK
NO.
DRY
I/O
A
1
1
Input
Input A
B
2
2
Input
Input B
GND
3
3
—
Ground
Y
4
4
Output
VCC
5
6
—
Positive Supply
5
—
No internal connection
NC
DESCRIPTION
Output Y
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
UNIT
V
(2)
VI
Input voltage range
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
150
°C
150
°C
Continuous current through VCC or GND
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
4
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
HBM ESD Classification Level
UNIT
(1)
±2000
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level
V
±1000
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions (1)
VCC
Operating
Supply voltage
Data retention only
5.5
UNIT
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
High-level input voltage
MAX
1.5
VCC = 1.65 V to 1.95 V
VIH
MIN
1.65
1.7
VCC = 3 V to 3.6 V
V
2
VCC = 4.5 V to 5.5 V
0.7 × VCC
VCC = 1.65 V to 1.95 V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VIL
Low-level input voltage
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
VCC = 4.5 V to 5.5 V
0.3 × VCC
VCC = 1.65 V
–4
VCC = 2.3 V
IOH
High-level output current
–8
–16
VCC = 3 V
Low-level output current
Δt/Δv
–32
VCC = 1.65 V
4
VCC = 2.3 V
8
16
VCC = 3 V
Input transition rise or fall rate
(1)
Operating free-air temperature
mA
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
TA
mA
–24
VCC = 4.5 V
IOL
V
ns/V
5
Q-suffix devices
–40
125
°C
I-suffix devices
–40
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6.4 Thermal Information
SN74LVC1G08-Q1
THERMAL METRIC (1)
DBV
DCK
DRY
5 PINS
5 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
209.4
244.2
264.4
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
132.5
156.1
166.6
°C/W
RθJB
Junction-to-board thermal resistance
118.1
130.8
142.2
°C/W
ψJT
Junction-to-top characterization parameter
48.8
47.2
26.1
°C/W
ψJB
Junction-to-board characterization parameter
117.4
130.0
141.6
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
–
–
–
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
IOH = –100 μA
VOH
1.65 V to 5.5 V
VCC – 0.15
1.2
1.2
IOH = –8 mA
2.3 V
1.9
1.9
2.4
2.4
2.3
2.3
3V
3.8
UNIT
TYP
MAX
V
IOH = –32 mA
4.5 V
IOL = 100 μA
1.65 V to 5.5 V
0.1
0.1
IOL = 4 mA
1.65 V
0.45
0.45
IOL = 8 mA
2.3 V
0.3
0.3
3.8
0.4
0.4
0.55
0.55
0.55
0.55
0 to 5.5 V
±5
±5
μA
3V
IOL = 24 mA
IOL = 32 mA
4.5 V
VI = 5.5 V or GND
Ioff
VI or VO = 5.5 V
ICC
VI = 5.5 V or GND,
ΔICC
One input at VCC – 0.6 V,
Other inputs at VC C or GND
Ci
VI = VCC or GND
(1)
MIN
VCC – 0.1
IOL = 16 mA
II
MAX
1.65 V
IOH = –24 mA
A or B
inputs
TYP (1)
IOH = –4 mA
IOH = –16 mA
VOL
–40°C to 125°C
RECOMMENDED
–40°C to 85°C
VCC
IO = 0
V
0
±10
±10
μA
1.65 V to 5.5 V
10
10
μA
3 V to 5.5 V
500
500
μA
3.3 V
4
4
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
6.6 Switching Characteristics, TA = –40°C to 125°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
–40°C to 125°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1
10
1
7.5
1
6.5
1
6
ns
6.7 Switching Characteristics, TA = –40°C to 85°C
over recommended operating free-air temperature range, (unless otherwise noted) (see Figure 4)
–40°C to 85°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.4
8
1.1
5.5
1
4.5
1
4
ns
6.8 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance
TEST
CONDITIONS
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
f = 10 MHz
21
24
26
31
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UNIT
pF
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6.9 Typical Characteristics
8
6
TPD
7
5
6
TPD - ns
TPD - ns
4
3
5
4
3
2
2
1
1
TPD
0
-100
0
-50
0
50
Temperature - °C
100
150
0
1
D001
Figure 1. Propagation Delay (tpd) Across Temperature at
3.3V VCC
2
3
Vcc - V
4
5
6
D002
Figure 2. Propagation Delay (tpd) Across VCC at 25°C
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
15 pF
15 pF
15 pF
15 pF
1 MW
1 MW
1 MW
1 MW
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
VM
VOL
tPHL
tPLZ
VLOAD/2
VM
tPZH
VM
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VOH
Output
VM
tPZL
tPHL
VM
Output
VI
Output
Control
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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Parameter Measurement Information (continued)
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74LVC1G08Q device contains one 2-input positive AND gate device and performs the Boolean function
Y = A • B or Y = A + B This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down.
8.2 Functional Block Diagram
Figure 5. Positive Logic
8.3 Feature Description
•
•
•
•
Wide operating voltage range.
– Operates from 1.65 V to 5.5 V.
Allows down voltage translation.
Inputs accept voltages to 5.5 V.
Ioff feature allows voltages on the inputs and outputs when VCC is 0 V.
8.4 Device Functional Modes
Table 1. Function Table
INPUTS
10
A
B
OUTPUT
Y
H
H
H
L
X
L
X
L
L
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9 Application and Implementation
9.1 Application Information
The SN74LVC1G08Q is a high-drive CMOS device that can be used for implementing AND logic with a high
output drive, such as an LED application. It can produce 24 mA of drive current at 3.3 V making it Ideal for
driving multiple outputs and good for high speed applications up to 100 MHz. The inputs are 5.5 V tolerant
allowing it to translate down to VCC.
9.2 Typical Application
AND Logic Function
Basic LED Driver
VCC
VCC
A- uC or Logic
A- uC or Logic
Y- uC or Logic
B- uC or Logic
LVC1G08
B- uC or Logic
LVC1G08
Figure 6. Typical Application Example
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed (IO max) per output and should not exceed total current (continuous
current through VCC or GND) for the part. These limits are located in the Absolute Maximum Ratings
table.
– Outputs should not be pulled above VCC.
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Typical Application (continued)
9.2.3 Application Curves
10
8
Icc
Icc
Icc
Icc
1.8V
2.5V
3.3V
5V
Icc - mA
6
4
2
0
-2
-20
0
20
40
Frequency - MHz
60
80
D003
Figure 7. Icc vs Frequency
10 Power Supply Recommendations
The power supply can be any voltage between the min and max supply voltage rating located in the
Recommended Operating Conditions table.
Each Vcc pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF capacitor is recommended and if there are multiple Vcc pins then 0.01-μF or 0.022-μF capacitor
is recommended for each power pin. It is ok to parallel multiple bypass capacitors to reject different frequencies
of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as
close to the power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only
3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages
at the outside connections result in undefined operational states. Specified below are the rules that must be
observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low
bias to prevent them from floating. The logic level that should be applied to any particular unused input depends
on the function of the device. Generally they will be tied to Gnd or Vcc whichever make more sense or is more
convenient.
11.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
Figure 8. Layout Example
12
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Copyright © 2004–2019, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G08-Q1
SN74LVC1G08-Q1
www.ti.com
SCES556G – MARCH 2004 – REVISED JUNE 2019
12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2004–2019, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G08-Q1
13
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LVC1G08IDCKRQ1
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CEO
SN74LVC1G08QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C08O
SN74LVC1G08QDCKRQ1
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CEO
SN74LVC1G08QDRYRQ1
ACTIVE
SON
DRY
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
EM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2019
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1G08-Q1 :
• Catalog: SN74LVC1G08
• Enhanced Product: SN74LVC1G08-EP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74LVC1G08IDCKRQ1
Package Package Pins
Type Drawing
SC70
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DCK
5
3000
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
SN74LVC1G08QDBVRQ1 SOT-23
DBV
5
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
SN74LVC1G08QDCKRQ1
SC70
DCK
5
3000
179.0
8.4
2.2
2.5
1.2
4.0
8.0
Q3
SN74LVC1G08QDRYRQ1
SON
DRY
6
5000
180.0
9.5
1.2
1.65
0.7
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC1G08IDCKRQ1
SC70
DCK
5
3000
203.0
203.0
35.0
SN74LVC1G08QDBVRQ1
SOT-23
DBV
5
3000
203.0
203.0
35.0
SN74LVC1G08QDCKRQ1
SC70
DCK
5
3000
203.0
203.0
35.0
SN74LVC1G08QDRYRQ1
SON
DRY
6
5000
189.0
185.0
36.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRY 6
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4207181/G
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Copyright © 2019, Texas Instruments Incorporated
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