Texas Instruments | Single 2-Input Exclusive-OR Gate (Rev. A) | Datasheet | Texas Instruments Single 2-Input Exclusive-OR Gate (Rev. A) Datasheet

Texas Instruments Single 2-Input Exclusive-OR Gate (Rev. A) Datasheet
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SN74AHC1G86-Q1
SCLS723A – APRIL 2011 – REVISED MAY 2019
Single 2-Input Exclusive-OR Gate
1 Features
2 Applications
•
•
•
•
•
•
•
1
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– ±4000-V Human-Body Model (HBM) ESD
Classification Level 3A
– ±1000-V Charged-Device Model (CDM) ESD
Classification Level C5
Operating Range of 2 V to 5.5 V
Max tpd of 10ns at 5 V
Low Power Consumption, 10-μA Max ICC
±8-mA Output Drive at 5 V
Schmitt-Trigger Action at All Inputs Makes the
Circuit Tolerant for Slower Input Rise and Fall
Time
Wireless Headsets
Motor Drives and Controls
TVs
Set-Top Boxes
Audio
3 Description
The SN74AHC1G86-Q1 is a single 2-input exclusiveOR gate. The device performs the Boolean function Y
= A ⊕ B or Y = AB + AB in positive logic.
A common application is as a true/complement
element. If one of the inputs is low, the other input is
reproduced in true form at the output. If one of the
inputs is high, the signal on the other input is
reproduced inverted at the output.
Device Information(1)
PART NUMBER
SN74AHC1G86QDBVQ1
PACKAGE
SOT-23 (5)
BODY SIZE (NOM)
2.90 mm x 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Functional Block Diagram
EXCLUSIVE OR
=1
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AHC1G86-Q1
SCLS723A – APRIL 2011 – REVISED MAY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Functional Block Diagram ....................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
3
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
3
3
4
4
5
6
6
6
6
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics..........................................
Switching Characteristics ..........................................
Switching Characteristics ..........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
9.1
9.2
9.3
9.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Function Table ..........................................................
8
8
8
9
10 Application and Implementation........................ 10
10.1 Application Information.......................................... 10
10.2 Typical Application ............................................... 10
11 Power Supply Recommendations ..................... 11
12 Layout................................................................... 12
12.1 Layout Guidelines ................................................. 12
12.2 Layout Example .................................................... 12
13 Device and Documentation Support ................. 13
13.1
13.2
13.3
13.4
13.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13
14 Mechanical, Packaging, and Orderable
Information ........................................................... 13
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (April 2011) to Revision A
Page
•
Changed Features section .................................................................................................................................................... 1
•
Added Applications section ................................................................................................................................................... 1
•
Changed Description section.................................................................................................................................................. 1
•
Changed Pin Configuration and Functions section ................................................................................................................ 3
•
Added TJ spec to Absolute Maximum Ratings table .............................................................................................................. 3
•
Changed Tstg to -65° (min) and 150°C (max) from -40°C (min) and 125°C (max) ................................................................. 3
•
Added ESD Ratings table....................................................................................................................................................... 3
•
Added Thermal Information table ........................................................................................................................................... 4
•
Added Typical Characteristics section.................................................................................................................................... 6
•
Added Detailed Description section........................................................................................................................................ 8
•
Added Application and Implementation section .................................................................................................................. 10
•
Added Power Supply Recommendations section ............................................................................................................... 11
•
Added Layout section .......................................................................................................................................................... 12
2
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SCLS723A – APRIL 2011 – REVISED MAY 2019
6 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
A
1
B
2
GND
3
5
VCC
4
Y
Pin Functions (1)
PIN
NO.
I/O
NAME
1
A
DESCRIPTION
I
Input A
2
B
I
Input B
3
GND
—
Ground
4
Y
O
Output Y
5
VCC
—
Positive Supply
(1)
See mechanical drawings for dimensions.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
7
V
VI
Input voltage range (1)
–0.5
7
V
VO
Output voltage range applied in the high- or low-state (1)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0 V
–20
V
IOK
Output clamp current
VO < 0 V or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 V to VCC
±25
mA
±50
mA
150
°C
150
°C
Continuous current through VCC or GND
TJ
Junction temperature
Tstg
Storage temperature range
(1)
–65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
(1)
Charged-device model (CDM), per AEC Q100-011
±4000
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
MIN
MAX
2
5.5
VCC = 3 V
2.1
V
3.85
VCC = 2 V
Low-level input voltage
V
1.5
VCC = 5.5 V
VIL
UNIT
0.5
VCC = 3 V
0.9
VCC = 5.5 V
V
1.65
VI
Input voltage
0
5.5
VO
Output voltage
0
VCC
V
–50
μA
VCC = 2 V
IOH
High-level output current
IOL
Low-level output current
Δt/ΔV
Input transition rise or fall rate
TA
Operating free-air temperature
VCC = 3.3 V ±0.3 V
–4
VCC = 5 V ±0.5 V
–8
VCC = 2 V
50
VCC = 3.3 V ±0.3 V
4
VCC = 5 V ±0.5 V
8
VCC = 3.3 V ±0.3 V
100
VCC = 5 V ±0.5 V
20
–40
125
V
mA
μA
mA
ns/V
°C
7.4 Thermal Information
SN74AHC1G86-Q1
THERMAL METRIC
(1)
DBV
(SOT-23)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
224.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
152.8
°C/W
RθJB
Junction-to-board thermal resistance
131.8
°C/W
ψJT
Junction-to-top characterization parameter
65.7
°C/W
ψJB
Junction-to-board characterization parameter
131.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5
SCLS723A – APRIL 2011 – REVISED MAY 2019
Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
TYP
2V
1.9
2
1.9
3V
2.9
3
2.9
4.5 V
4.4
4.5
4.4
IOH = –4 mA
3V
2.58
IOH = –8 mA
4.5 V
3.94
IOH = –50 μA
VOH
IOL = 50 μA
VOL
IOL = 4 mA
IOL = 8 mA
II
VI = 5.5 V or GND
ICC
VI = VCC or GND,
CI
VI = VCC or GND
IO = 0 A
MAX
MIN MAX
MIN
UNIT
V
2.48
3.8
2V
0.1
0.1
0.1
3V
0.1
4.5 V
0.1
0.1
3V
0.36
0.44
4.5 V
0.36
0.44
0 V to 5.5 V
±0.1
±1
μA
1
10
μA
10
10
pF
5.5 V
5V
4
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5
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7.6 Switching Characteristics
over recommended operating free-air temperature range, VCC = 3.3 V ±0.3 V, TA = –40°C to 125°C, see
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A or B
Y
CL = 50 pF
TA = 25°C
MIN
MIN
MAX
14.5
1
16.5
14.5
1
16.5
MIN
MAX
TYP
MAX
9.5
9.5
UNIT
ns
7.7 Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ±0.5 V, TA = –40°C to 125°C, see
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A or B
Y
CL = 50 pF
TA = 25°C
MIN
TYP
MAX
6.3
8.8
1
10
6.3
8.8
1
10
UNIT
ns
7.8 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
TYP
No load, f = 1 MHz
18
UNIT
pF
7.9 Typical Characteristics
6
8
7
5
6
TPD (ns)
TPD (ns)
4
3
5
4
3
2
2
1
1
TPD in ns
0
-100
TPD in ns
0
-50
0
50
Temperature (qC)
100
150
0
1
D001
Figure 1. TPD vs Temperature
6
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2
3
VCC
4
5
6
D002
Figure 2. TPD vs VCC at 25°C
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8 Parameter Measurement Information
Figure 3. Load Circuit and Voltage Waveforms
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9 Detailed Description
9.1 Overview
The SN74AHC1G86-Q1 is an automotive qualified device that performs the Boolean function Y = AB + AB in
positive logic. This single 2-input exclusive-OR gate is designed for 2-V to 5.5-V VCC operation.
A common application is as a true or complementary element. If one of the inputs is low, the other input is
reproduced in true form at the output. If one of the inputs is high, the signal on the other input is reproduced
inverted at the output.
9.2 Functional Block Diagram
EXCLUSIVE OR
=1
Copyright © 2017, Texas Instruments Incorporated
These are five equivalent exclusive-OR symbols valid for an SN74AHC1G86-Q1 gate in positive logic; negation may
be shown at any two ports.
9.3 Feature Description
9.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device may
create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined the in the must be followed at all times.
9.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the . The worst case resistance is calculated with the maximum input voltage, given in the ,
and the maximum input leakage current, given in the , using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in to avoid excessive current
consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input
should be used to condition the input signal prior to the standard CMOS input.
9.3.3 Clamping Diodes
The inputs have negative clamping diodes, and the outputs have positive and negative clamping diodes as
depicted in Figure 4.
CAUTION
Voltages beyond the values specified in the table can cause damage to the device.
The input negative-voltage and output voltage ratings may be exceeded if the input
and output clamp-current ratings are observed.
8
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Feature Description (continued)
Device
VCC
+IOK
Logic
Input
-IIK
Output
-IOK
GND
Figure 4. Electrical Placement of Clamping Diodes for Each Input and Output
9.3.4 Over-voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the .
9.4 Function Table
Table 1 lists the functional modes of the SN74AHC1G86-Q1 device.
Table 1. Function Table
INPUTS
A
B
OUTPUT
Y
L
L
L
L
H
H
H
L
H
H
H
L
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN74AHC1G86-Q1 is a low-drive CMOS device that can be used for a multitude of bus interface type
applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and
undershoot on the outputs. The inputs can accept voltages to 5.5 V at any valid VCC making it Ideal for down
translation.
10.2 Typical Application
5-V accessory
3.3-V or 5-V regulated
0.1 µF
5-V
System
Logic
µC or
System
Logic
Figure 5. Typical Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– For rise time and fall time specifications, see Δt/ΔV in the table.
– For specified High and low levels, see VIH and VIL in the table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommended Output Conditions
– Load currents should not exceed 8 mA per output.
– Outputs should not be pulled above VCC.
10
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Typical Application (continued)
10.2.3 Application Curve
Figure 6. Switching Characteristics Comparison
11 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
table.
Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply,
0.1 µF is recommended. If there are multiple VCC pins, 0.01 µF or 0.022 µF is recommended for each power pin.
It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1-µF and 1-µF are
commonly used in parallel. The bypass capacitor must be installed as close to the power pin as possible for best
results.
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12 Layout
12.1 Layout Guidelines
Even low data rate digital signals can have high frequency signal components due to fast edge rates. When a
PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the
change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. shows progressively better techniques of rounding corners. Only the last example (BEST) maintains
constant trace width and minimizes reflections.
12.2 Layout Example
WORST
BETTER
BEST
Figure 7. Trace Example
12
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13 Device and Documentation Support
13.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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15-May-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
SN74AHC1G86QDBVRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOT-23
DBV
5
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
ACYU
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74AHC1G86-Q1 :
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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15-May-2019
• Catalog: SN74AHC1G86
• Enhanced Product: SN74AHC1G86-EP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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15-May-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74AHC1G86QDBVRQ
1
Package Package Pins
Type Drawing
SPQ
SOT-23
3000
DBV
5
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
179.0
8.4
Pack Materials-Page 1
3.2
B0
(mm)
K0
(mm)
P1
(mm)
3.2
1.4
4.0
W
Pin1
(mm) Quadrant
8.0
Q3
PACKAGE MATERIALS INFORMATION
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15-May-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AHC1G86QDBVRQ1
SOT-23
DBV
5
3000
203.0
203.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
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EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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