Texas Instruments | SN74AXCH1T45 Single-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation, Tri-State Outputs, and Bus-Hold Inputs (Rev. A) | Datasheet | Texas Instruments SN74AXCH1T45 Single-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation, Tri-State Outputs, and Bus-Hold Inputs (Rev. A) Datasheet

Texas Instruments SN74AXCH1T45 Single-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation, Tri-State Outputs, and Bus-Hold Inputs (Rev. A) Datasheet
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SN74AXCH1T45
SCES883A – DECEMBER 2018 – REVISED JANUARY 2019
SN74AXCH1T45 Single-Bit Dual-Supply Bus Transceiver
with Configurable Voltage Translation, Tri-State Outputs, and Bus-Hold Inputs
1 Features
•
1
•
•
•
•
•
•
•
•
•
Fully Configurable Dual-Rail Design Allows Each
Port to Operate With a Power Supply Range from
0.65 V to 3.6 V
Operating Temperature: –40°C to +125°C
Glitch-Free Power Supply Sequencing
Bus-hold on Data Inputs Eliminates the Need for
External Pullup or Pulldown Resistors
Maximum Quiescent Current (ICCA + ICCB) of 8 µA
(85°C Maximum) and 14 µA (125°C Maximum)
Up to 500-Mbps Support When Translating from
1.8 to 3.3V
VCC Isolation Feature
– If Either VCC Input is Below 100 mV, All I/Os
Outputs are Disabled and Become HighImpedance
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 8000-V Human Body Model
– 1000-V Charged-Device Model
The DIR pin determines the direction of signal
propagation. With the DIR pin configured HIGH,
translation is from Port A to Port B. With DIR
configured LOW, translation is from Port B to Port A.
The DIR pin is referenced to VCCA, meaning that its
logic-high and logic-low thresholds track with VCCA.
Active bus-hold circuitry holds unused or undriven
inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not
recommended. If a supply is present for VCCA or
VCCB, the bus-hold circuitry always remains active on
the A or B inputs respectively, independent of the
state of the direction control pin.
This device is fully specified for partial-power-down
applications using the Ioff current. The Ioff protection
circuitry ensures that no excessive current is drawn
from or to an input, output, or combined I/O that is
biased to a specific voltage while the device is
powered down.
The VCC isolation feature ensures that if either VCCA
or VCCB is less than 100 mV, both I/O ports enter a
high-impedance state by disabling their outputs.
Glitch-free power supply sequencing allows either
supply rail to be powered on or off in any order while
providing robust power sequencing performance.
2 Applications
•
•
•
•
•
•
Personal Electronics
Enterprise and Communications
Wireless Infrastructure
Building Automation
Electronic Point of Sale
Enterprise Solid State Drive
Device Information(1)
PACKAGE
BODY SIZE (NOM)
SN74AXCH1T45DBV
PART NUMBER
SOT-23 (6)
2.90 mm × 1.60 mm
SN74AXCH1T45DCK
SC70 (6)
2.00 mm × 1.25 mm
SN74AXCH1T45DTQ
X2SON (6)
1.00 mm x 0.80 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
3 Description
The SN74AXCH1T45 is a single-bit noninverting bus
transceiver that uses two individually configurable
power-supply rails. The device is operational with
both VCCA and VCCB supplies as low as 0.65 V. The A
port is designed to track VCCA, which accepts any
supply voltage from 0.65 V to 3.6 V. The B port is
designed to track VCCB, which also accepts any
supply voltage from 0.65 V to 3.6 V. Additionally the
SN74AXCH1T45 is compatible with a single-supply
system.
VCCA
VCCB
DIR
Bus-Hold
A
B
Bus-Hold
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AXCH1T45
SCES883A – DECEMBER 2018 – REVISED JANUARY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Operating Characteristics: TA = 25°C ..................... 16
Typical Characteristics ............................................ 17
7
Parameter Measurement Information ................ 19
8
Detailed Description ............................................ 21
7.1 Load Circuit and Voltage Waveforms ..................... 19
8.1 Overview ................................................................. 21
8.2 Functional Block Diagram ....................................... 21
8.3 Feature Description................................................. 21
8.4 Device Functional Modes........................................ 23
9
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Applications ................................................ 24
10 Power Supply Recommendations ..................... 27
11 Layout................................................................... 27
11.1 Layout Guidelines ................................................. 27
11.2 Layout Example .................................................... 27
12 Device and Documentation Support ................. 28
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
28
13 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
Changes from Original (December 2018) to Revision A
Page
•
Added DBV and DTQ package options to Device Information table ..................................................................................... 1
•
Updated Revision History section........................................................................................................................................... 1
•
Added pinout drawings for DBV and DTQ packages ............................................................................................................ 3
2
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SCES883A – DECEMBER 2018 – REVISED JANUARY 2019
5 Pin Configuration and Functions
DCK Package
6-Pin SC70
Top View
DBV Package
6-Pin SOT-23
Top View
VCCA
1
6
VCCA
1
6
VCCB
GND
2
5
DIR
A
3
4
B
VCCB
GND
2
5
DIR
A
3
4
B
DTQ Package
6-Pin X2SON
Transparent Top View
VCCA
2
GND
A
6
1
3
5
VCCB
DIR
4
B
Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
1
VCCA
—
A-port supply voltage. 0.65V ≤ VCCA ≤ 3.6 V
2
GND
—
Ground
3
A
I/O
Input/output A. This pin is referenced to VCCA.
4
B
I/O
Input/output B. This pin is referenced to VCCB.
5
DIR
I
Direction control signal. See for functionality
6
VCCB
—
B-port supply voltage. 0.65V ≤ VCCB ≤ 3.6 V.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCCA
Supply voltage A
VCCB
Supply voltage B
Input Voltage (2)
VI
MIN
MAX
–0.5
4.2
V
V
–0.5
4.2
I/O Ports (A Port)
–0.5
4.2
I/O Ports (B Port)
–0.5
4.2
Control Inputs
–0.5
4.2
A Port
–0.5
4.2
B Port
–0.5
4.2
A Port
–0.5 VCCA + 0.2
B Port
–0.5 VCCB + 0.2
UNIT
V
VO
Voltage applied to any output in the high-impedance or power-off state (2)
VO
Voltage applied to any output in the high or low state (2)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
(3)
Continuous current through VCC or GND
Tj
Junction Temperature
Tstg
Storage temperature
(1)
(2)
(3)
V
V
–50
50
mA
–100
100
mA
150
°C
150
°C
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The output positive-voltage rating may be exceeded up to 4.2 V maximum if the output current rating is observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±8000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SCES883A – DECEMBER 2018 – REVISED JANUARY 2019
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
(2) (3)
MIN
MAX
UNIT
VCCA
Supply voltage A
0.65
3.6
V
VCCB
Supply voltage B
0.65
3.6
V
Data Inputs
VCCI = 0.65 V - 0.75 V
VCCI x 0.70
VCCI = 0.76 V - 1 V
VCCI x 0.70
VCCI = 1.1 V - 1.95 V
VCCI x 0.65
VCCI = 2.3 V - 2.7 V
VIH
1.6
VCCI = 3 V - 3.6 V
High-level input voltage
Control Input (DIR)
Referenced to VCCA
2
VCCA = 0.65 V - 0.75 V
VCCA x 0.70
VCCA = 0.76 V - 1 V
VCCA x 0.70
VCCA = 1.1 V - 1.95 V
VCCA x 0.65
VCCA = 2.3 V - 2.7 V
1.6
VCCA = 3 V - 3.6 V
Data Inputs
VIL
Low-level input voltage
Control Input (DIR)
Referenced to VCCA
V
2
VCCI = 0.65 V - 0.75 V
VCCI x 0.30
VCCI = 0.76 V - 1 V
VCCI x 0.30
VCCI = 1.1 V - 1.95 V
VCCI x 0.35
VCCI = 2.3 V - 2.7 V
0.7
VCCI = 3 V - 3.6 V
0.8
VCCA = 0.65 V - 0.75 V
VCCA x 0.30
VCCA = 0.76 V - 1 V
VCCA x 0.30
VCCA = 1.1 V - 1.95 V
VCCA x 0.35
VCCA = 2.3 V - 2.7 V
0.7
VCCA = 3 V - 3.6 V
VI
Input voltage
0
3.6
Active State
0
VCCO
Tri-State
0
3.6
Output voltage
Δt/Δv
Input transition rate
TA
Operating free-air temperature
(1)
(2)
(3)
0.8
(3)
VO
V
–40
V
V
100
ns/V
125
°C
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs.
6.4 Thermal Information
SN74AXCH1T45
THERMAL METRIC
(1)
DBV (SOT-23)
DCK (SC70)
DTQ (X2SON)
6 PINS
6 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
214.0
223.9
327.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
151.8
150.9
194.9
°C/W
RθJB
Junction-to-board thermal resistance
93.6
75.3
248.4
°C/W
ψJT
Junction-to-top characterization parameter
78.1
58.2
24.1
°C/W
ψJB
Junction-to-board characterization parameter
93.4
75.0
247.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
(1) (2)
over operating free-air temperature range (unless otherwise noted)
Operating free-air temperature (TA)
PARAMETER
TEST CONDITIONS
VCCA
VCCB
-40°C to 85°C
MIN TYP (3)
VOH
VOL
IBHL
IBHH
(1)
(2)
(3)
(4)
(5)
6
High-level
output
voltage
Low-level
output
voltage
Bus-hold low
sustaining
current (4)
Bus-hold
high
sustaining
current (5)
VI = VIH
VI = VIL
-40°C to 125°C
MAX
MIN
TYP
UNIT
MAX
VCCO
– 0.1
VCCO
– 0.1
0.65 V
0.55
0.55
0.76 V
0.58
0.58
0.85 V
0.85 V
0.65
0.65
IOH = -3 mA
1.1 V
1.1 V
0.85
0.85
IOH = -6 mA
1.4 V
1.4 V
1.05
1.05
IOH = -8 mA
1.65 V
1.65 V
1.2
1.2
IOH = -9 mA
2.3 V
2.3 V
1.75
1.75
IOH = -12 mA
3V
3V
IOL = 100 µA
0.7 V - 3.6 V
0.7 V - 3.6 V
0.1
0.1
IOL = 50 µA
0.65 V
0.65 V
0.1
0.1
IOL = 200 µA
0.76 V
0.76 V
0.18
0.18
IOL = 500 µA
0.85 V
0.85 V
0.2
0.2
IOL = 3 mA
1.1 V
1.1 V
0.25
0.25
IOL = 6 mA
1.4 V
1.4 V
0.35
0.35
IOL = 8 mA
1.65 V
1.65 V
0.45
0.45
IOL = 9 mA
2.3 V
2.3 V
0.55
0.55
IOL = 12 mA
3V
3V
0.7
0.7
IOH = -100 µA
0.7 V - 3.6 V
0.7 V - 3.6 V
IOH = -50 µA
0.65 V
IOH = -200 µA
0.76 V
IOH = -500 µA
2.3
V
2.3
VI= 0.20 V
0.65 V
0.65 V
4
VI= 0.23 V
0.76 V
0.76 V
8
7
VI= 0.26 V
0.85 V
0.85 V
10
10
VI= 0.39 V
1.1 V
1.1 V
20
20
VI= 0.49 V
1.4 V
1.4 V
40
30
VI= 0.58 V
1.65 V
1.65 V
55
45
VI= 0.7 V
2.3 V
2.3 V
90
80
VI= 0.8 V
3V
3V
145
135
VI= 0.45 V
0.65 V
0.65 V
–4
–4
VI= 0.53 V
0.76 V
0.76 V
–8
–7
VI= 0.59 V
0.85 V
0.85 V
–10
–10
VI= 0.71 V
1.1 V
1.1 V
–20
–20
VI= 0.91 V
1.4 V
1.4 V
–40
–30
VI= 1.07 V
1.65 V
1.65 V
–55
–45
VI= 1.6 V
2.3 V
2.3 V
–90
–80
VI= 2.0 V
3V
3V
–145
–135
V
4
µA
µA
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
All typical data is taken at 25°C.
The bus-hold circuit can sink at least the minimum low sustaining current at VIL(MAX). IBHL should be measured after lowering VI to
GND and then raising it to VIL(MAX).
The bus-hold circuit can source at least the minimum high sustaining current at VIH(MIN). IBHH should be measured after raising VI to
VCC and then lowering it to VIH(MIN).
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SCES883A – DECEMBER 2018 – REVISED JANUARY 2019
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted) (1) (2)
Operating free-air temperature (TA)
PARAMETER
TEST CONDITIONS
VCCA
VCCB
-40°C to 85°C
MIN TYP (3)
IBHLO
IBHHO
II
Bus-hold low
overdrive
current (6)
Bus-hold
high
overdrive
current (7)
VI= 0 to VCC
VI= 0 to VCC
Control input (DIR): VI =
Input leakage VCCA or GND
current
A or B Port: Vi = VCCI or
GND
Partial power A or B Port: Vi or Vo = 0 V down current 3.6 V
ICCA
VCCA supply
current
0.75 V
0.75 V
40
40
0.84 V
0.84 V
50
50
0.95 V
0.95 V
65
65
1.3 V
1.3 V
105
105
1.6 V
1.6 V
150
150
1.95 V
1.95 V
205
205
2.7 V
2.7 V
335
335
3.6V
3.6V
480
480
0.75 V
0.75 V
–40
–40
0.84 V
0.84 V
–50
–50
0.95 V
0.95 V
–65
–65
1.3 V
1.3 V
–105
–105
1.6 V
1.6 V
–150
–150
1.95 V
1.95 V
–205
–205
2.7 V
2.7 V
–335
–335
3.6V
3.6V
–480
–480
VCCB supply
current
Combined
ICCA +
supply
ICCB
current
VI = VCCI
or GND
VI = VCCI
or GND
TYP
UNIT
MAX
µA
µA
0.65 V- 3.6 V 0.65 V- 3.6 V
–0.5
0.5
–1
1
0.65 V- 3.6 V 0.65 V- 3.6 V
–4
4
–8
8
0V
0 V - 3.6 V
–8
8
–12
12
0 V - 3.6 V
0V
–8
8
–12
12
0.65 V- 3.6 V 0.65 V- 3.6 V
ICCB
MIN
µA
Ioff
VI = VCCI
or GND
-40°C to 125°C
MAX
IO = 0
IO = 0
IO = 0
0V
3.6 V
3.6 V
0V
6
–2
9
–8
µA
2
8
0.65 V- 3.6 V 0.65 V- 3.6 V
6
9
0V
3.6 V
2
3.6 V
0V
–2
µA
8
µA
14
µA
–8
0.65 V- 3.6 V 0.65 V- 3.6 V
8
Ci
Control input
capacitance
VI = 3.3 V or GND
3.3 V
3.3 V
4.3
4.3
pF
Cio
Data I/O
capacitance,
A Port
VO = 1.65V DC +1 MHz -16
dBm sine wave
3.3 V
0V
7.4
7.4
pF
Cio
Data I/O
capacitance,
B Port
VO = 1.65V DC +1 MHz -16
dBm sine wave
0V
3.3 V
7.4
7.4
pF
(6)
(7)
An external driver must source at least IBHLO to switch this node from low to high.
An external driver must sink at least IBHHO to switch this node from high to low.
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Table 1. Switching Characteristics, VCCA = 0.7 V
B-Port Supply Voltage (VCCB)
PARAMETER
tpd
FROM
A
B
B
A
Propagation
delay
DIR
tdis
ten
A
Disable time
DIR
B
DIR
A
Enable time
DIR
8
TO
B
Test
Conditions
0.7 ± 0.05 V
1.2 ± 0.1 V
1.5 ± 0.1 V
2.5 ± 0.2 V
3.3 ± 0.3 V
MIN
MAX
0.8 ± 0.04 V
MIN
MAX
0.9 ± 0.045 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
-40°C to 85°C
0.5
181
0.5
119
0.5
85
0.5
51
0.5
49
0.5
52
0.5
65
0.5
152
-40°C to 125°C
0.5
181
0.5
119
0.5
85
0.5
51
0.5
49
0.5
52
0.5
65
0.5
152
-40°C to 85°C
0.5
181
0.5
162
0.5
136
0.5
96
0.5
91
0.5
89
0.5
88
0.5
88
-40°C to 125°C
0.5
181
0.5
162
0.5
136
0.5
96
0.5
91
0.5
89
0.5
88
0.5
88
-40°C to 85°C
0.5
152
0.5
152
0.5
152
0.5
152
0.5
152
0.5
152
0.5
152
0.5
152
-40°C to 125°C
0.5
152
0.5
152
0.5
152
0.5
152
0.5
152
0.5
152
0.5
152
0.5
152
-40°C to 85°C
0.5
170
0.5
127
0.5
102
0.5
48
0.5
42
0.5
46
0.5
58
0.5
108
-40°C to 125°C
0.5
170
0.5
127
0.5
102
0.5
48
0.5
42
0.5
46
0.5
58
0.5
108
-40°C to 85°C
0.5
343
0.5
278
0.5
231
0.5
141
0.5
132
0.5
134
0.5
144
0.5
193
-40°C to 125°C
0.5
343
0.5
278
0.5
231
0.5
141
0.5
132
0.5
134
0.5
144
0.5
193
-40°C to 85°C
0.5
326
0.5
257
0.5
222
0.5
194
0.5
191
0.5
191
0.5
197
0.5
277
-40°C to 125°C
0.5
326
0.5
257
0.5
222
0.5
194
0.5
191
0.5
191
0.5
197
0.5
277
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1.8 ± 0.15 V
UNIT
ns
ns
ns
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SCES883A – DECEMBER 2018 – REVISED JANUARY 2019
Table 2. Switching Characteristics, VCCA = 0.8 V
B-Port Supply Voltage (VCCB)
PARAMETER
tpd
FROM
A
B
B
A
Propagation
delay
DIR
tdis
ten
TO
A
Disable time
DIR
B
DIR
A
Enable time
DIR
B
Test
Conditions
0.7 ± 0.05 V
1.2 ± 0.1 V
1.5 ± 0.1 V
2.5 ± 0.2 V
3.3 ± 0.3 V
MIN
MAX
0.8 ± 0.04 V
MIN
MAX
0.9 ± 0.045 V
MIN
MAX
MIN
MAX
MIN
MAX
1.8 ± 0.15 V
MIN
MAX
MIN
MAX
MIN
MAX
-40°C to 85°C
0.5
162
0.5
98
0.5
65
0.5
33
0.5
28
0.5
26
0.5
27
0.5
37
-40°C to 125°C
0.5
162
0.5
98
0.5
65
0.5
33
0.5
28
0.5
26
0.5
27
0.5
37
-40°C to 85°C
0.5
119
0.5
98
0.5
81
0.5
54
0.5
45
0.5
44
0.5
43
0.5
42
-40°C to 125°C
0.5
119
0.5
98
0.5
81
0.5
54
0.5
45
0.5
44
0.5
43
0.5
42
-40°C to 85°C
0.5
107
0.5
107
0.5
107
0.5
107
0.5
107
0.5
107
0.5
107
0.5
107
-40°C to 125°C
0.5
107
0.5
107
0.5
107
0.5
107
0.5
107
0.5
107
0.5
107
0.5
107
-40°C to 85°C
0.5
160
0.5
117
0.5
90
0.5
39
0.5
31
0.5
29
0.5
29
0.5
37
-40°C to 125°C
0.5
160
0.5
117
0.5
90
0.5
39
0.5
31
0.5
29
0.5
29
0.5
37
-40°C to 85°C
0.5
268
0.5
205
0.5
165
0.5
90
0.5
74
0.5
71
0.5
70
0.5
77
-40°C to 125°C
0.5
268
0.5
205
0.5
165
0.5
90
0.5
74
0.5
71
0.5
70
0.5
77
-40°C to 85°C
0.5
257
0.5
194
0.5
161
0.5
130
0.5
125
0.5
126
0.5
125
0.5
132
-40°C to 125°C
0.5
257
0.5
194
0.5
161
0.5
130
0.5
125
0.5
126
0.5
125
0.5
132
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: SN74AXCH1T45
UNIT
ns
ns
ns
9
SN74AXCH1T45
SCES883A – DECEMBER 2018 – REVISED JANUARY 2019
www.ti.com
Table 3. Switching Characteristics, VCCA = 0.9 V
B-Port Supply Voltage (VCCB)
PARAMETER
tpd
FROM
A
B
B
A
Propagation
delay
DIR
tdis
ten
A
Disable time
DIR
B
DIR
A
Enable time
DIR
10
TO
B
Test
Conditions
0.7 ± 0.05 V
1.2 ± 0.1 V
1.5 ± 0.1 V
2.5 ± 0.2 V
3.3 ± 0.3 V
MIN
MAX
0.8 ± 0.04 V
MIN
MAX
0.9 ± 0.045 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
-40°C to 85°C
0.5
135
0.5
81
0.5
54
0.5
24
0.5
18
0.5
17
0.5
15
0.5
18
-40°C to 125°C
0.5
135
0.5
81
0.5
54
0.5
24
0.5
18
0.5
17
0.5
15
0.5
18
-40°C to 85°C
0.5
86
0.5
65
0.5
54
0.5
41
0.5
30
0.5
26
0.5
23
0.5
23
-40°C to 125°C
0.5
86
0.5
65
0.5
54
0.5
41
0.5
30
0.5
26
0.5
23
0.5
23
-40°C to 85°C
0.5
79
0.5
79
0.5
79
0.5
79
0.5
79
0.5
79
0.5
79
0.5
79
-40°C to 125°C
0.5
79
0.5
79
0.5
79
0.5
79
0.5
79
0.5
79
0.5
79
0.5
79
-40°C to 85°C
0.5
154
0.5
111
0.5
85
0.5
34
0.5
27
0.5
25
0.5
21
0.5
23
-40°C to 125°C
0.5
154
0.5
111
0.5
85
0.5
34
0.5
27
0.5
25
0.5
21
0.5
23
-40°C to 85°C
0.5
227
0.5
166
0.5
131
0.5
71
0.5
53
0.5
48
0.5
42
0.5
44
-40°C to 125°C
0.5
227
0.5
166
0.5
131
0.5
71
0.5
53
0.5
48
0.5
42
0.5
44
-40°C to 85°C
0.5
206
0.5
152
0.5
125
0.5
96
0.5
91
0.5
89
0.5
89
0.5
92
-40°C to 125°C
0.5
206
0.5
152
0.5
125
0.5
96
0.5
91
0.5
89
0.5
89
0.5
92
Submit Documentation Feedback
1.8 ± 0.15 V
UNIT
ns
ns
ns
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: SN74AXCH1T45
SN74AXCH1T45
www.ti.com
SCES883A – DECEMBER 2018 – REVISED JANUARY 2019
Table 4. Switching Characteristics, VCCA = 1.2 V
B-Port Supply Voltage (VCCB)
PARAMETER
tpd
FROM
A
B
B
A
Propagation
delay
DIR
tdis
ten
TO
A
Disable time
DIR
B
DIR
A
Enable time
DIR
B
Test
Conditions
0.7 ± 0.05 V
1.2 ± 0.1 V
1.5 ± 0.1 V
2.5 ± 0.2 V
3.3 ± 0.3 V
MIN
MAX
0.8 ± 0.04 V
MIN
MAX
0.9 ± 0.045 V
MIN
MAX
MIN
MAX
MIN
MAX
1.8 ± 0.15 V
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
-40°C to 85°C
0.5
95
0.5
54
0.5
41
0.5
16
0.5
11
0.5
9
0.5
8
0.5
8
-40°C to 125°C
0.5
95
0.5
54
0.5
41
0.5
16
0.5
11
0.5
9
0.5
8
0.5
8
-40°C to 85°C
0.5
51
0.5
33
0.5
24
0.5
16
0.5
13
0.5
11
0.5
8
0.5
8
-40°C to 125°C
0.5
51
0.5
33
0.5
24
0.5
16
0.5
13
0.5
11
0.5
8
0.5
8
-40°C to 85°C
0.5
28
0.5
28
0.5
28
0.5
28
0.5
28
0.5
28
0.5
28
0.5
28
-40°C to 125°C
0.5
28
0.5
28
0.5
28
0.5
28
0.5
28
0.5
28
0.5
28
0.5
28
-40°C to 85°C
0.5
148
0.5
105
0.5
78
0.5
30
0.5
23
0.5
20
0.5
16
0.5
16
-40°C to 125°C
0.5
148
0.5
105
0.5
78
0.5
30
0.5
23
0.5
20
0.5
16
0.5
16
-40°C to 85°C
0.5
191
0.5
129
0.5
96
0.5
43
0.5
34
0.5
30
0.5
23
0.5
22
-40°C to 125°C
0.5
191
0.5
129
0.5
96
0.5
43
0.5
34
0.5
30
0.5
23
0.5
22
-40°C to 85°C
0.5
116
0.5
75
0.5
61
0.5
41
0.5
37
0.5
36
0.5
35
0.5
35
-40°C to 125°C
0.5
116
0.5
75
0.5
61
0.5
41
0.5
37
0.5
36
0.5
35
0.5
35
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: SN74AXCH1T45
ns
ns
ns
11
SN74AXCH1T45
SCES883A – DECEMBER 2018 – REVISED JANUARY 2019
www.ti.com
Table 5. Switching Characteristics, VCCA = 1.5 V
B-Port Supply Voltage (VCCB)
PARAMETER
tpd
FROM
A
B
B
A
Propagation
delay
DIR
tdis
ten
A
Disable time
DIR
B
DIR
A
Enable time
DIR
12
TO
B
Test
Conditions
0.7 ± 0.05 V
1.2 ± 0.1 V
1.5 ± 0.1 V
2.5 ± 0.2 V
3.3 ± 0.3 V
MIN
MAX
0.8 ± 0.04 V
MIN
MAX
0.9 ± 0.045 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
-40°C to 85°C
0.5
91
0.5
45
0.5
30
0.5
13
0.5
9
0.5
8
0.5
6
0.5
6
-40°C to 125°C
0.5
91
0.5
45
0.5
30
0.5
13
0.5
9
0.5
8
0.5
6
0.5
6
-40°C to 85°C
0.5
49
0.5
28
0.5
18
0.5
11
0.5
9
0.5
8
0.5
6
0.5
5
-40°C to 125°C
0.5
49
0.5
28
0.5
18
0.5
11
0.5
9
0.5
8
0.5
6
0.5
5
-40°C to 85°C
0.5
20
0.5
20
0.5
20
0.5
20
0.5
20
0.5
20
0.5
20
0.5
20
-40°C to 125°C
0.5
20
0.5
20
0.5
20
0.5
20
0.5
20
0.5
20
0.5
20
0.5
20
-40°C to 85°C
0.5
146
0.5
103
0.5
76
0.5
28
0.5
21
0.5
19
0.5
15
0.5
14
-40°C to 125°C
0.5
146
0.5
103
0.5
76
0.5
28
0.5
21
0.5
19
0.5
15
0.5
14
-40°C to 85°C
0.5
186
0.5
124
0.5
89
0.5
38
0.5
29
0.5
26
0.5
20
0.5
18
-40°C to 125°C
0.5
186
0.5
124
0.5
89
0.5
38
0.5
29
0.5
26
0.5
20
0.5
18
-40°C to 85°C
0.5
104
0.5
58
0.5
43
0.5
31
0.5
28
0.5
27
0.5
25
0.5
25
-40°C to 125°C
0.5
104
0.5
58
0.5
43
0.5
31
0.5
28
0.5
27
0.5
25
0.5
25
Submit Documentation Feedback
1.8 ± 0.15 V
UNIT
ns
ns
ns
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: SN74AXCH1T45
SN74AXCH1T45
www.ti.com
SCES883A – DECEMBER 2018 – REVISED JANUARY 2019
Table 6. Switching Characteristics, VCCA = 1.8 V
B-Port Supply Voltage (VCCB)
PARAMETER
tpd
FROM
A
B
B
A
Propagation
delay
DIR
tdis
ten
TO
A
Disable time
DIR
B
DIR
A
Enable time
DIR
B
Test
Conditions
0.7 ± 0.05 V
1.2 ± 0.1 V
1.5 ± 0.1 V
2.5 ± 0.2 V
3.3 ± 0.3 V
MIN
MAX
0.8 ± 0.04 V
MIN
MAX
0.9 ± 0.045 V
MIN
MAX
MIN
MAX
MIN
MAX
1.8 ± 0.15 V
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
-40°C to 85°C
0.5
89
0.5
44
0.5
26
0.5
11
0.5
8
0.5
7
0.5
6
0.5
5
-40°C to 125°C
0.5
89
0.5
44
0.5
26
0.5
11
0.5
8
0.5
7
0.5
6
0.5
5
-40°C to 85°C
0.5
52
0.5
26
0.5
17
0.5
9
0.5
8
0.5
7
0.5
6
0.5
5
-40°C to 125°C
0.5
52
0.5
26
0.5
17
0.5
9
0.5
8
0.5
7
0.5
6
0.5
5
-40°C to 85°C
0.5
17
0.5
17
0.5
17
0.5
17
0.5
17
0.5
17
0.5
17
0.5
17
-40°C to 125°C
0.5
17
0.5
17
0.5
17
0.5
17
0.5
17
0.5
17
0.5
17
0.5
17
-40°C to 85°C
0.5
147
0.5
103
0.5
76
0.5
27
0.5
20
0.5
18
0.5
14
0.5
13
-40°C to 125°C
0.5
147
0.5
103
0.5
76
0.5
27
0.5
20
0.5
18
0.5
14
0.5
13
-40°C to 85°C
0.5
185
0.5
122
0.5
86
0.5
35
0.5
27
0.5
24
0.5
19
0.5
17
-40°C to 125°C
0.5
185
0.5
122
0.5
86
0.5
35
0.5
27
0.5
24
0.5
19
0.5
17
-40°C to 85°C
0.5
100
0.5
54
0.5
37
0.5
27
0.5
25
0.5
24
0.5
22
0.5
22
-40°C to 125°C
0.5
100
0.5
54
0.5
37
0.5
27
0.5
25
0.5
24
0.5
22
0.5
22
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: SN74AXCH1T45
ns
ns
ns
13
SN74AXCH1T45
SCES883A – DECEMBER 2018 – REVISED JANUARY 2019
www.ti.com
Table 7. Switching Characteristics, VCCA = 2.5 V
B-Port Supply Voltage (VCCB)
PARAMETER
tpd
FROM
A
B
B
A
Propagation
delay
DIR
tdis
ten
A
Disable time
DIR
B
DIR
A
Enable time
DIR
14
TO
B
Test
Conditions
0.7 ± 0.05 V
1.2 ± 0.1 V
1.5 ± 0.1 V
2.5 ± 0.2 V
3.3 ± 0.3 V
MIN
MAX
0.8 ± 0.04 V
MIN
MAX
0.9 ± 0.045 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
-40°C to 85°C
0.5
88
0.5
42
0.5
23
0.5
8
0.5
6
0.5
6
0.5
5
0.5
5
-40°C to 125°C
0.5
88
0.5
42
0.5
23
0.5
8
0.5
6
0.5
6
0.5
5
0.5
5
-40°C to 85°C
0.5
65
0.5
27
0.5
15
0.5
8
0.5
6
0.5
6
0.5
5
0.5
4
-40°C to 125°C
0.5
65
0.5
27
0.5
15
0.5
8
0.5
6
0.5
6
0.5
5
0.5
4
-40°C to 85°C
0.5
13
0.5
13
0.5
13
0.5
13
0.5
13
0.5
13
0.5
13
0.5
13
-40°C to 125°C
0.5
13
0.5
13
0.5
13
0.5
13
0.5
13
0.5
13
0.5
13
0.5
13
-40°C to 85°C
0.5
146
0.5
102
0.5
75
0.5
27
0.5
19
0.5
17
0.5
13
0.5
12
-40°C to 125°C
0.5
146
0.5
102
0.5
75
0.5
27
0.5
19
0.5
17
0.5
13
0.5
12
-40°C to 85°C
0.5
191
0.5
122
0.5
85
0.5
33
0.5
25
0.5
22
0.5
17
0.5
16
-40°C to 125°C
0.5
191
0.5
122
0.5
85
0.5
33
0.5
25
0.5
22
0.5
17
0.5
16
-40°C to 85°C
0.5
95
0.5
50
0.5
31
0.5
20
0.5
18
0.5
17
0.5
17
0.5
17
-40°C to 125°C
0.5
95
0.5
50
0.5
31
0.5
20
0.5
18
0.5
17
0.5
17
0.5
17
Submit Documentation Feedback
1.8 ± 0.15 V
UNIT
ns
ns
ns
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: SN74AXCH1T45
SN74AXCH1T45
www.ti.com
SCES883A – DECEMBER 2018 – REVISED JANUARY 2019
Table 8. Switching Characteristics, VCCA = 3.3 V
B-Port Supply Voltage (VCCB)
PARAMETER
tpd
FROM
A
B
B
A
Propagation
delay
DIR
tdis
ten
TO
A
Disable time
DIR
B
DIR
A
Enable time
DIR
B
Test
Conditions
0.7 ± 0.05 V
1.2 ± 0.1 V
1.5 ± 0.1 V
2.5 ± 0.2 V
3.3 ± 0.3 V
MIN
MAX
0.8 ± 0.04 V
MIN
MAX
0.9 ± 0.045 V
MIN
MAX
MIN
MAX
MIN
MAX
1.8 ± 0.15 V
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
-40°C to 85°C
0.5
87
0.5
42
0.5
23
0.5
8
0.5
5
0.5
5
0.5
4
0.5
4
-40°C to 125°C
0.5
87
0.5
42
0.5
23
0.5
8
0.5
5
0.5
5
0.5
4
0.5
4
-40°C to 85°C
0.5
154
0.5
37
0.5
18
0.5
8
0.5
6
0.5
5
0.5
5
0.5
4
-40°C to 125°C
0.5
154
0.5
37
0.5
18
0.5
8
0.5
6
0.5
5
0.5
5
0.5
4
-40°C to 85°C
0.5
12
0.5
12
0.5
12
0.5
12
0.5
12
0.5
12
0.5
12
0.5
12
-40°C to 125°C
0.5
12
0.5
12
0.5
12
0.5
12
0.5
12
0.5
12
0.5
12
0.5
12
-40°C to 85°C
0.5
147
0.5
102
0.5
75
0.5
26
0.5
19
0.5
17
0.5
13
0.5
12
-40°C to 125°C
0.5
147
0.5
102
0.5
75
0.5
26
0.5
19
0.5
17
0.5
13
0.5
12
-40°C to 85°C
0.5
275
0.5
129
0.5
88
0.5
34
0.5
24
0.5
21
0.5
17
0.5
16
-40°C to 125°C
0.5
275
0.5
129
0.5
88
0.5
34
0.5
24
0.5
21
0.5
17
0.5
16
-40°C to 85°C
0.5
94
0.5
49
0.5
30
0.5
18
0.5
16
0.5
16
0.5
15
0.5
15
-40°C to 125°C
0.5
94
0.5
49
0.5
30
0.5
18
0.5
16
0.5
16
0.5
15
0.5
15
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ns
ns
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6.6 Operating Characteristics: TA = 25°C
PARAMETER
Power Dissipation Capacitance
per transceiver (A to B: outputs
enabled)
TEST CONDITIONS
CL = 0, RL = Open f = 1
MHz, tr = tf = 1 ns
CpdA
Power Dissipation Capacitance
per transceiver (B to A: outputs
enabled)
Power Dissipation Capacitance
per transceiver (A to B: outputs
enabled)
CL = 0, RL = Open f = 1
MHz, tr = tf = 1 ns
CL = 0, RL = Open f = 1
MHz, tr = tf = 1 ns
CpdB
Power Dissipation Capacitance
per transceiver (B to A: outputs
enabled)
16
CL = 0, RL = Open f = 1
MHz, tr = tf = 1 ns
VCCA
VCCB
MIN
TYP
0.7 V
0.7 V
2.0
0.8 V
0.8 V
2.0
0.9 V
0.9 V
2.0
1.2 V
1.2 V
2.0
1.5 V
1.5 V
1.9
1.8 V
1.8 V
2.0
2.5 V
2.5 V
2.4
3.3 V
3.3 V
3.0
0.7 V
0.7 V
12
0.8 V
0.8 V
12
0.9 V
0.9 V
12
1.2 V
1.2 V
12
1.5 V
1.5 V
13
1.8 V
1.8 V
13
2.5 V
2.5 V
17
3.3 V
3.3 V
21
0.7 V
0.7 V
12
0.8 V
0.8 V
12
0.9 V
0.9 V
12
1.2 V
1.2 V
12
1.5 V
1.5 V
13
1.8 V
1.8 V
13
2.5 V
2.5 V
17
3.3 V
3.3 V
21
0.7 V
0.7 V
2.1
0.8 V
0.8 V
2.2
0.9 V
0.9 V
2.2
1.2 V
1.2 V
2.2
1.5 V
1.5 V
2.3
1.8 V
1.8 V
2.3
2.5 V
2.5 V
2.6
3.3 V
3.3 V
3.3
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MAX
UNIT
pF
pF
pF
pF
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6.7 Typical Characteristics
50
45
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
TA = 25°C
40
35
30
25
20
15
0.9
1.2
1.5
1.8
2.1
Supply B (V)
2.4
2.7
3
3.3
TA = 25°C
1.5
1.8
2.1
Supply B (V)
2.4
2.7
3
3.3
D001
VCCA = 0.8 V
30
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
Propagation delay (ns)
27
25
20
15
10
24
21
18
15
12
9
5
0.6
0.9
1.2
1.5
1.8
2.1
Supply B (V)
2.4
2.7
3
6
0.6
3.3
0.9
1.2
1.5
D002
VCCA = 0.9 V
TA = 25°C
Figure 3. Typical Propagation Delay of Low-to-High
(A to B) vs Load Capacitance
1.8
2.1
Supply B (V)
2.4
2.7
3
3.3
D003
VCCA = 1.2 V
Figure 4. Typical Propagation Delay of Low-to-High
(A to B) vs Load Capacitance
30
27
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
24
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
24
Propagation delay (ns)
27
21
18
15
12
9
21
18
15
12
9
6
6
0.6
TA = 25°C
1.2
Figure 2. Typical Propagation Delay of Low-to-High
(A to B) vs Load Capacitance
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
30
TA = 25°C
0.9
D016
35
Propagation delay (ns)
25
10
0.6
40
Propagation delay (ns)
30
15
0.6
VCCA = 0.7 V
0.9
1.2
1.5
1.8
2.1
Supply B (V)
2.4
2.7
3
3
0.6
3.3
0.9
1.2
1.5
D004
VCCA = 1.5 V
TA = 25°C
Figure 5. Typical Propagation Delay of Low-to-High
(A to B) vs Load Capacitance
1.8
2.1
Supply B (V)
2.4
2.7
3
3.3
D005
VCCA = 1.8 V
Figure 6. Typical Propagation Delay of Low-to-High
(A to B) vs Load Capacitance
27
27
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
21
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
24
Propagation delay (ns)
24
Propagation delay (ns)
35
20
Figure 1. Typical Propagation Delay of Low-to-High
(A to B) vs Load Capacitance
18
15
12
9
6
21
18
15
12
9
6
3
0.6
TA = 25°C
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
40
Propagation delay (ns)
Propagation delay (ns)
45
0.9
1.2
1.5
1.8
2.1
Supply B (V)
2.4
2.7
3
3
0.6
3.3
0.9
1.2
1.5
D007
VCCA = 3.3 V
TA = 25°C
Figure 7. Typical Propagation Delay of Low-to-High
(A to B) vs Load Capacitance
1.8
2.1
Supply B (V)
2.4
2.7
3
3.3
D006
VCCA = 2.5 V
Figure 8. Typical Propagation Delay of Low-to-High
(A to B) vs Load Capacitance
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Typical Characteristics (continued)
40
50
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
40
35
30
25
15
0.6
0.9
1.2
1.5
1.8
2.1
Supply A (V)
2.4
2.7
3
TA = 25°C
1.5
1.8
2.1
Supply A (V)
2.4
2.7
3
3.3
D009
Figure 10. Typical Propagation Delay of Low-to-High
(B to A) vs Load Capacitance
30
27
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
25
Propagation delay (ns)
Propagation delay (ns)
1.2
27.5
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
33
24
21
18
15
22.5
20
17.5
15
12.5
10
12
9
0.6
0.9
1.2
1.5
1.8
2.1
Supply A (V)
2.4
2.7
3
7.5
0.6
3.3
TA = 25°C
Figure 11. Typical Propagation Delay of Low-to-High
(B to A) vs Load Capacitance
1.2
1.5
1.8
2.1
Supply A (V)
2.4
2.7
3
3.3
D011
VCCA = 1.2 V
Figure 12. Typical Propagation Delay of Low-to-High
(B to A) vs Load Capacitance
30
25
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
24
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
22.5
Propagation delay (ns)
27
21
18
15
12
9
6
0.6
0.9
D010
VCCA = 0.9 V
Propagation delay (ns)
0.9
VCCA = 0.8 V
36
20
17.5
15
12.5
10
7.5
0.9
1.2
1.5
1.8
2.1
Supply A (V)
2.4
2.7
3
5
0.6
3.3
0.9
1.2
1.5
1.8
2.1
Supply A (V)
D012
VCCA = 1.5 V
TA = 25°C
Figure 13. Typical Propagation Delay of Low-to-High
(B to A) vs Load Capacitance
2.4
2.7
3
3.3
D013
VCCA = 1.8 V
Figure 14. Typical Propagation Delay of Low-to-High
(B to A) vs Load Capacitance
30
30
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
27
Propagation delay (ns)
25
Propagation delay (ns)
20
D008
Figure 9. Typical Propagation Delay of Low-to-High
(B to A) vs Load Capacitance
TA = 25°C
25
10
0.6
3.3
VCCA = 0.7 V
TA = 25°C
30
15
20
TA = 25°C
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
35
Propagation delay (ns)
Propagation delay (ns)
45
20
15
10
24
21
18
15
12
9
6
5
0.6
TA = 25°C
0.9
1.2
1.5
1.8
2.1
Supply A (V)
2.4
2.7
3
0.9
1.2
1.5
D014
VCCA = 2.5 V
TA = 25°C
Figure 15. Typical Propagation Delay of Low-to-High
(B to A) vs Load Capacitance
18
3
0.6
3.3
1.8
2.1
Supply A (V)
2.4
2.7
3
3.3
D015
VCCA = 3.3 V
Figure 16. Typical Propagation Delay of Low-to-High
(B to A) vs Load Capacitance
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7 Parameter Measurement Information
7.1 Load Circuit and Voltage Waveforms
Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:
• f = 1 MHz
• ZO = 50 Ω
• dv/dt ≤ 1 ns/V
Measurement Point
2 x VCCO
S1
RL
Open
Output Pin
Under Test
GND
CL(1)
(1)
RL
CL includes probe and jig capacitance.
Figure 17. Load Circuit
Table 9. Load Circuit Conditions
Parameter
VCCO
RL
CL
S1
VTP
Δt/Δv
Input transition rise or fall rate
0.65 V – 3.6 V
1 MΩ
15 pF
Open
N/A
1.1 V – 3.6 V
2 kΩ
15 pF
Open
N/A
tpd
Propagation (delay) time
0.65 V – 0.95
V
20 kΩ
15 pF
Open
N/A
ten, tdis Enable time, disable time
ten, tdis Enable time, disable time
3 V – 3.6 V
2 kΩ
15 pF
2 × VCCO
0.3 V
1.65 V – 2.7 V
2 kΩ
15 pF
2 × VCCO
0.15 V
1.1 V – 1.6 V
2 kΩ
15 pF
2 × VCCO
0.1 V
0.65 V – 0.95
V
20 kΩ
15 pF
2 × VCCO
0.1 V
3 V – 3.6 V
2 kΩ
15 pF
GND
0.3 V
1.65 V – 2.7 V
2 kΩ
15 pF
GND
0.15 V
1.1 V – 1.6 V
2 kΩ
15 pF
GND
0.1 V
0.65 V – 0.95
V
20 kΩ
15 pF
GND
0.1 V
VCCI(1)
VCCI(1)
Input A, B
Input A, B
VCCI / 2
VCCI / 2
100 kHz
500 ps/V ± 100 ns/V
0V
tpd
VOH(2)
tpd
VOH(2)
Output B, A
VCCI / 2
Output B, A
Ensure Monotonic
Rising and Falling Edge
VCCI / 2
VOL(2)
1.
2.
0V
VCCI is the supply pin associated with the input port.
VOH and VOL are typical output voltage levels that occur with
specified RL, CL, and S1
1.
2.
VOL(2)
VCCI is the supply pin associated with the input port.
VOH and VOL are typical output voltage levels that occur with
specified RL, CL, and S1
Figure 19. Input Transition Rise or Fall Rate
Figure 18. Propagation Delay
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VCCA
DIR
VCCA / 2
VCCA / 2
GND
ten(1)
Output A(2)
VCCO(5)
VCCO / 2
VOL + VTP
VOL(6)
tdis
VOH(6)
VOH - VTP
Output A(3)
VCCO / 2
GND
ten
Output B
(1)
(2)
VCCO(5)
VCCO / 2
VOL + VTP
VOL(6)
tdis
VOH(6)
Output B(3)
VOH - VTP
VCCO / 2
GND
1.
Illustrative purposes only. Enable Time is a calculation as described in the data sheet.
2.
Output waveform on the condition that input is driven to a valid Logic Low.
3.
Output waveform on the condition that input is driven to a valid Logic High.
4.
VCCI is the supply pin associated with the input port
5.
VCCO is the supply pin associated with the output port.
6.
VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1
Figure 20. Disable and Enable Time
20
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8 Detailed Description
8.1 Overview
The SN74AXCH1T45 is single-bit, dual-supply, noninverting voltage level translator. Pin A and the direction
control pin are referenced to VCCA logic levels and pin B is referenced to VCCB logic levels, as depicted in . The A
port can accept I/O voltages ranging from 0.65 V to 3.6 V, and the B port can accept I/O voltages from 0.65 V to
3.6 V. A logic high on the DIR pin enables data transmission from A to B and a logic low on the DIR pin enables
data transmission from B to A.
8.2 Functional Block Diagram
VCCA
VCCB
DIR
Bus-Hold
B
A
Bus-Hold
Figure 21. Functional Block Diagram
8.3 Feature Description
8.3.1 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating
Conditions to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a
device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.
8.3.2 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at
all times.
8.3.3 Partial Power Down (Ioff)
The inputs and outputs for this device enter a high-impedance state when the device is powered down, inhibiting
current backflow into the device. The maximum leakage into or out of any input or output pin on the device is
specified by Ioff in the Electrical Characteristics.
8.3.4 VCC Isolation
The inputs and outputs for this device enter a high-impedance state when either supply is <100mV.
8.3.5 Over-voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Recommended Operating Conditions.
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Feature Description (continued)
8.3.6 Negative Clamping Diodes
The inputs and outputs to this device have negative clamping diodes as depicted in Figure 22.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
Device
VCC
Logic
Input
-IIK
Output
-IOK
GND
Figure 22. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.7 Fully Configurable Dual-Rail Design
Both the VCCA and VCCB pins can be supplied at any voltage from 0.65 V to 3.6 V, making the device suitable for
translating between any of the voltage nodes (0.7 V, 0.8 V, 0.9 V, 1.2 V, 1.8 V, 2.5 V and 3.3 V).
8.3.8 Supports High-Speed Translation
The SN74AXCH1T45 device can support high data-rate applications. The translated signal data rate can be up
to 500 Mbps when the signal is translated from 1.8 V to 3.3 V.
8.3.9 Bus-Hold Data Inputs
Each data input on this device includes a weak latch that maintains a valid logic level on the input. The state of
these latches is unknown at startup and remains unknown until the input has been forced to a valid high or low
state. After data has been sent through a channel, the latch then maintains the previous state on the input if the
line is left floating. It is not recommended to use pull-up or pull-down resistors together with a bus-hold input, as
it may cause undefined inputs to occur which leads to excessive current consumption.
Bus-hold data inputs prevent floating inputs on this device. The Implications of Slow or Floating CMOS Inputs
application report explains the problems associated with leaving CMOS inputs floating.
These latches remain active at all times, independent of all control signals such as direction control or output
enable.
The Bus-Hold Circuit application report has additional details regarding bus-hold inputs.
Input
Logic
Output
Bus-Hold Latch
Figure 23. Simplified Schematic For Device With Bus-Hold Data Inputs
22
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8.4 Device Functional Modes
Table 10 lists the device functions for the DIR input.
Table 10. Function Table
INPUT
DIR
(1)
(1)
OPERATION
L
B data to A bus
H
A data to B bus
Input circuits of the data I/Os always are active.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74AXCH1T45 device can be used in level-translation applications for interfacing devices or systems with
one another when they are operating at different interface voltages. The maximum data rate can be up to 500
Mbps when the device translate signals from 1.8 V to 3.3 V.
9.1.1 Enable Times
Calculate the enable times for the SN74AXC1T45 using the following formulas:
tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
(1)
(2)
(3)
(4)
In a bidirectional application, these enable times provide the maximum delay time from the time the DIR bit is
switched until an output is expected. For example, if the SN74AXCH1T45 initially is transmitting from A to B, then
the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B
port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
9.2 Typical Applications
9.2.1 Interrupt Request Application
Figure 24 shows an example of the SN74AXCH1T45 being used in an application where a system controller
flags an interrupt request (IRQ) to the CPU. The system controller determines the direction of the IRQ line to
either flag an interrupt to the CPU or allow the CPU to drive data on the line. In this application the controller is
operating at 3.3 V while the CPU can be operating as low as 0.65 V.
The SN74AXCH1T45 device is used to ensure that these devices can communicate at the appropriate voltage
levels. Because the SN74AXCH1T45 does not have an output-enable (OE) pin, the system designer should take
precautions to avoid bus contention between the CPU and controller when changing directions.
0.7 V
3.3 V
0.1 µF
0.1 µF
VCCA
CPU
IRQ
Data
A
VCCB
SN74AXCH1T45
GND
B
DIR
IRQ
Data
Controller
IRQ
Direction
Figure 24. Interrupt Request Application
9.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 11.
24
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Typical Applications (continued)
Table 11. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUES
Input voltage range
0.65 V to 3.6 V
Output voltage range
0.65 V to 3.6 V
9.2.1.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the SN74AXCH1T45 device to determine the input
voltage range. For a valid logic-high, the value must exceed the high-level input voltage (VIH) of the input
port. For a valid logic low the value must be less than the low-level input voltage (VIL) of the input port.
• Output voltage range
– Use the supply voltage of the device that the SN74AXCH1T45 device is driving to determine the output
voltage range.
9.2.1.3 Application Curve
Figure 25. Up Translation at 2.5 MHz (0.7 V to 3.3 V)
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9.2.2 Universal Asynchronous Receiver-Transmitter (UART) Interface Application
Figure 26 shows the SN74AXCH1T45 being used for the two-bit UART interface application. One
SN74AXCH1T45 device is used to level shift the voltage and drive the TX from the processor to the GPS Module
while a second SN74AXCH1T45 device is used to drive the TX Data line from the GPS Module to the Processor.
Devices with bus-hold inputs remove the requirement for external pullup resistors to maintain a valid logic level at
the input.
0.7 V
3.3 V
0.1 µF
0.1 µF
VCCA
A
TX
VCCB
SN74AXCH1T45
DIR
B
GND
0.1 µF
0.1 µF
Processor
VCCA
A
RX
DIR
RX
GPS Module
VCCB
SN74AXCH1T45
B
TX
GND
Figure 26. UART Interface Application
9.2.2.1 Design Requirements
Refer to Design Requirements.
9.2.2.2 Detailed Design Procedure
Refer to Detailed Design Procedure.
26
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SN74AXCH1T45
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SCES883A – DECEMBER 2018 – REVISED JANUARY 2019
10 Power Supply Recommendations
Always apply a ground reference to the GND pins first. This device is designed for glitch free power sequencing
without any supply sequencing requirements such as ramp order or ramp rate.
This device was designed with various power supply sequencing methods in mind to help prevent unintended
triggering of downstream devices. For more information regarding the power up glitch performance of the AXC
family of level translators, see the Power Sequencing for AXC Family of Devices application report
11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, following common printed-circuit board layout guidelines are recommended:
• Use bypass capacitors on the power supply pins and place them as close to the device as possible.
• Use short trace lengths to avoid excessive loading.
11.2 Layout Example
LEGEND
VIA to Power Plane
Polygonal Copper Pour
VIA to GND Plane (Inner Layer)
VCCB
VCCA
1
VCCA
VCCB 6
2
GND
DIR 5
3
A
VCCA
B 4
From Controller
To System
Figure 27. PCB Layout Example
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Product Folder Links: SN74AXCH1T45
27
SN74AXCH1T45
SCES883A – DECEMBER 2018 – REVISED JANUARY 2019
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
For related documentation see the following:
• Texas Instruments, Evaluate SN74AXC1T45DRL Using a Generic EVM application report
• Texas Instruments, System Considerations For Using Bus-hold Circuits To Avoid Floating Inputsapplication
report
• Texas Instruments, Power Sequencing for the AXC Family of Devices application report
• Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
28
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SCES883A – DECEMBER 2018 – REVISED JANUARY 2019
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: SN74AXCH1T45
29
PACKAGE OPTION ADDENDUM
www.ti.com
4-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74AXCH1T45DBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
1PNL
SN74AXCH1T45DCKR
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
1CC
SN74AXCH1T45DTQR
ACTIVE
X2SON
DTQ
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
DM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Apr-2019
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
6
2X 0.95
1.9
1.45 MAX
3.05
2.75
5
2
4
0.50
6X
0.25
0.2
C A B
3
(1.1)
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X (0.95)
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214840/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X(0.95)
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DTQ0006A
X2SON - 0.4 mm max height
SCALE 12.000
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
B
A
PIN 1 INDEX AREA
0.85
0.75
0.40 MAX
C
SEATING PLANE
(0.1) TYP
0.05 C
(0.1)
2X 0.6
(0.027) TYP
0.4
3
0.25
+0.05
TYP
-0.03
0.05
0.00
4
PKG
2
5
(0.08)
4X
PIN 1 ID
(OPTIONAL)
NOTE 5
1
PKG
0.25
0.17
6
4X
0.30
0.22
0.1
0.05
C A B
C
4224056/A 11/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pads must be soldered to the printed circuit board for optimal thermal and mechanical performance.
4. The size and shape of this feature may vary.
5. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
www.ti.com
EXAMPLE BOARD LAYOUT
DTQ0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SOLDER MASK OPEING
TYP
SYMM
4X (0.25)
0.05 MIN
ALL AROUND
TYP
6
1
(0.25)
TYP
4X (0.4)
SYMM
(0.8)
5
2
(0.2) TYP
EXPOSED METAL
CLEARANCE
METAL UNDER
SOLDER MASK
TYP
3
4
(0.027) TYP
(0.2)
TYP
(R0.05) TYP
(0.4)
(0.6)
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:50X
4224056/A 11/2017
NOTES: (continued)
6. This package is designed to be soldered to a thermal pads on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
7. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DTQ0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.25)
SYMM
(0.027) TYP
(0.279)
TYP
6
1
4X (0.4)
SYMM
5
2
(0.8)
(0.2) TYP
SOLDER MASK
EDGE, 2X
METAL UNDER
SOLDER MASK
TYP
3
4
(0.2)
TYP
(R0.05) TYP
(0.21)
(0.367)
4X (0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.07 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:50X
4224056/A 11/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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