Texas Instruments | TXB0108 8-Bit Bidirectional Voltage-Level Translator with Auto-Direction Sensing and ±15-kV ESD Protection (Rev. G) | Datasheet | Texas Instruments TXB0108 8-Bit Bidirectional Voltage-Level Translator with Auto-Direction Sensing and ±15-kV ESD Protection (Rev. G) Datasheet

Texas Instruments TXB0108 8-Bit Bidirectional Voltage-Level Translator with Auto-Direction Sensing and ±15-kV ESD Protection (Rev. G) Datasheet
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TXB0108
SCES643G – NOVEMBER 2006 – REVISED DECEMBER 2018
TXB0108 8-Bit Bidirectional Voltage-Level Translator with Auto-Direction Sensing and
±15-kV ESD Protection
1 Features
3 Description
•
This 8-bit noninverting translator uses two separate
configurable power-supply rails. The A port is
designed to track VCCA. VCCA accepts any supply
voltage from 1.2 V to 3.6 V. The B port is designed to
track VCCB. VCCB accepts any supply voltage from
1.65 V to 5.5 V. This allows for universal low-voltage
bidirectional translation between any of the 1.2-V,
1.5-V, 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.
VCCA should not exceed VCCB.
1
•
•
•
•
•
•
1.2 V to 3.6 V on A Port and 1.65 V to 5.5 V on
B Port (VCCA ≤ VCCB)
VCC Isolation Feature – If Either VCC Input Is at
GND, All Outputs Are in the High-Impedance
State
OE Input Circuit Referenced to VCCA
Low Power Consumption, 4-μA Max ICC
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– A Port
– 2000-V Human-Body Model (A114-B)
– 1000-V Charged-Device Model (C101)
– B Port
– ±15-kV Human-Body Model (A114-B)
– ±8-kV Human-Body Model (A114-B)
(YZP Package Only)
– 1000-V Charged-Device Model (C101)
When the output-enable (OE) input is low, all outputs
are placed in the high-impedance state.
The TXB0108 is designed so that the OE input circuit
is supplied by VCCA.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
To ensure the high-impedance state during power-up
or power-down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
2 Applications
•
•
•
•
Device Information(1)
Handset
Smartphone
Tablet
Desktop PC
PART NUMBER
TXB0108
PACKAGE
BODY SIZE (NOM)
TVSOP (20)
5.00 mm x 4.40 mm
SON (20)
2.00 mm x 4.00 mm
BGA MICROSTAR
JUNIOR (20)
2.50 mm x 3.00 mm
TSSOP (20)
6.50 mm x 4.40 mm
VQFN (20)
4.50 mm x 3.50 mm
DSGBA (20)
1.90 mm x 2.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application Block Diagram for TXB010X
VCCA
Processor
VCCB
Peripheral
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TXB0108
SCES643G – NOVEMBER 2006 – REVISED DECEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
1
1
1
2
3
5
Absolute Maximum Ratings ..................................... 5
Handling Ratings....................................................... 5
Recommended Operating Conditions ...................... 5
Thermal Information .................................................. 6
Electrical Characteristics .......................................... 6
Timing Requirements: VCCA = 1.2 V ......................... 7
Timing Requirements: VCCA = 1.5 V ± 0.1 V ............ 7
Timing Requirements: VCCA = 1.8 V ± 0.15 V .......... 7
Timing Requirements: VCCA = 2.5 V ± 0.2 V ............ 7
Timing Requirements: VCCA = 3.3 V ± 0.3 V .......... 7
Switching Characteristics: VCCA = 1.2 V ................. 8
Switching Characteristics: VCCA = 1.5 V ± 0.1 V .... 8
Switching Characteristics: VCCA = 1.8 V ± 0.15 V .. 8
Switching Characteristics: VCCA = 2.5 V ± 0.2 V .... 9
Switching Characteristics: VCCA = 3.3 V ± 0.3 V .... 9
Operating Characteristics........................................ 9
Typical Characteristics .......................................... 10
7
8
Parameter Measurement Information ................ 11
Detailed Description ............................................ 12
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
13
14
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
10 Power Supply Recommendations ..................... 17
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 17
12 Device and Documentation Support ................. 18
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 18
13.1 Package Addendum.............................................. 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (November 2014) to Revision G
Page
•
Added pinout image for the ZYPR2 package option ............................................................................................................. 3
•
Added text string 'GRID LOCATOR' to Pin Functions table YZP column to clarify pin location from 'Signal Name' ............ 4
Changes from Revision E (April 2012) to Revision F
Page
•
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
•
Changed VOLA value 0.9 to 0.3 .............................................................................................................................................. 6
Changes from Revision D (September 2011) to Revision E
•
Added notes to pin out graphics............................................................................................................................................. 3
Changes from Revision C (August 2011) to Revision D
•
2
Page
Page
Added ±8-kV Human-Body Model (A114-B) (YZP Package Only) to Features ..................................................................... 1
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SCES643G – NOVEMBER 2006 – REVISED DECEMBER 2018
5 Pin Configuration and Functions
PW PACKAGE
(TOP VIEW)
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
B1
B2
B3
B4
VCCB
GND
B5
B6
B7
B8
A1
1
20
VCCA
2
19
A2
A3
A4
A5
3
18
4
17
5
16
6
15
A6
A7
7
14
8
13
9
12
10
11
B2
B3
B4
B5
VCCA
A2
A3
A4
A5
A6
A7
A8
B6
B7
B8
GND
1
20
Note:
YZP PACKAGE
(BALL SIDE VIEW)
E
B6
B8
A8
A6
D
GND
B7
A7
OE
4
19 VCCB
18 B2
17 B3
5
6
16 B4
15 B5
C
VCCB
B5
A5
VCCA
7
14 B6
13 B7
B
B4
B3
A3
A4
12 B8
A
B2
B1
A1
A2
1
2
3
4
2
3
8
9
10
11
OE
A8
OE
B1
VCCB
B1
1
GND
A1
A2
A3
A4
VCCA
OE
A5
A6
A7
A8
RGY PACKAGE
(TOP VIEW)
A1
DQS PACKAGE
(TOP VIEW)
For the RGY package, the exposed center thermal pad must be connected to ground.
A.
Pullup resistors are not required on both sides for Logic I/O.
B.
If pullup or pulldown resistors are needed, the resistor value must be over 50 kΩ.
C.
50 kΩ is a safe recommended value, if the customer can accept higher VOL or lower VOH, smaller pullup or pulldown
resistor is allowed, the draft estimation is VOL = VCCOUT × 4.5 k/(4.5 k + RPU) and VOH = VCCOUT × RDW/(4.5 k + RDW).
D.
If pullup resistors are needed, please refer to the TXS0108 or contact TI.
E.
For detailed information, please refer to application note SCEA043.
(1)
YZPR2 PACKAGE
(BALL SIDE VIEW)
E
B6
B8
A8
A6
D
GND
B7
A7
OE
C
VCCB
B5
A5
VCCA
B
B4
B3
A3
A4
A
B2
B1
A1
A2
1
2
3
4
Pin A1- area
indicator
(1)
See orderable addendum at the end of the data sheet
GXY OR ZXY PACKAGE
(BOTTOM VIEW)
1
2
3
4
5
D
C
B
A
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SCES643G – NOVEMBER 2006 – REVISED DECEMBER 2018
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Pin Functions
PIN
SIGNAL
NAME
PW, RGY NO.
DQS
NO.
I/O (1)
FUNCTION
A1
1
1
A3
I/O
VCCA
2
5
C4
S
A2
3
2
A4
I/O
Input/output 2. Referenced to VCCA.
A3
4
3
B3
I/O
Input/output 3. Referenced to VCCA.
A4
5
4
B4
I/O
Input/output 4. Referenced to VCCA.
A5
6
7
C3
I/O
Input/output 5. Referenced to VCCA.
A6
7
8
E4
I/O
Input/output 6. Referenced to VCCA.
A7
8
9
D3
I/O
Input/output 7. Referenced to VCCA.
A8
9
10
E3
I/O
Input/output 8. Referenced to VCCA.
OE
10
6
D4
I
Output enable. Pull OE low to place all outputs in 3-state mode. Referenced to VCCA.
GND
11
15
D1
S
Ground
B8
12
11
E2
I/O
Input/output 8. Referenced to VCCB.
B7
13
12
D2
I/O
Input/output 7. Referenced to VCCB.
B6
14
13
E1
I/O
Input/output 6. Referenced to VCCB.
B5
15
14
C2
I/O
Input/output 5. Referenced to VCCB.
B4
16
17
B1
I/O
Input/output 4. Referenced to VCCB.
B3
17
18
B2
I/O
Input/output 3. Referenced to VCCB.
B2
18
19
A1
I/O
Input/output 2. Referenced to VCCB.
VCCB
19
16
C1
S
B1
20
20
A2
I/O
Input/output 1. Referenced to VCCB.
—
For the RGY package, the exposed center thermal pad must be connected to ground.
Thermal
Pad
(1)
YZP
GRID LOCATOR
—
Input/output 1. Referenced to VCCA.
A-port supply voltage. 1.1 V ≤ VCCA ≤ 3.6 V, VCCA ≤ VCCB.
B-port supply voltage. 1.65 V ≤ VCCB ≤ 5.5 V.
I = input, O = output, I/O = input and output, S = power supply
Pin Assignments (20-Ball GXY/ZXY Package)
4
1
2
3
4
5
D
VCCB
B2
B4
B6
B8
C
B1
B3
B5
B7
GND
B
A1
A3
A5
A7
OE
A
VCCA
A2
A4
A6
A8
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SCES643G – NOVEMBER 2006 – REVISED DECEMBER 2018
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCCA
Supply voltage range
–0.5
4.6
V
VCCB
Supply voltage range
–0.5
6.5
V
VI
Input voltage range (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2)
A inputs
–0.5
VCCA + 0.5
B inputs
–0.5
VCCB + 0.5
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCCA, VCCB, or GND
±100
mA
150
°C
150
°C
Tstg
Storage temperature range
TJ
Junction temperature
(1)
(2)
(3)
(3)
–65
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCCA and VCCB are provided in the recommended operating conditions table.
6.2 Handling Ratings
MIN
MAX
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1), A Port
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1), B Port
V(ESD)
Electrostatic discharge
–15
15
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2), A Port
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2), A Port (YZP Package only)
1
–8
kV
8
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2), B Port
(1)
(2)
UNIT
2
1
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCCA
VCCA
VCCB
VCCB
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
Δt/Δv
Input transition
rise or fall rate
(1)
(2)
(3)
(2)
Data inputs
OE
1.2 V to 3.6 V
Data inputs
1.2 V to 5.5 V
OE
1.2 V to 3.6 V
A-port inputs
1.2 V to 3.6 V
B-port inputs
1.2 V to 3.6 V
1.65 V to 5.5 V
1.65 V to 5.5 V
MIN
MAX
1.2
3.6
1.65
5.5
VCCI x 0.65 (3)
VCCI
VCCA x 0.65
5.5
0
VCCI x 0.35 (3)
0
VCCA x 0.35
1.65 V to 5.5 V
40
1.65 V to 3.6 V
40
4.5 V to 5.5 V
30
UNIT
V
V
V
ns/V
The A and B sides of an unused data I/O pair must be held in the same state, i.e., both at VCCI or both at GND.
VCCA must be less than or equal to VCCB and must not exceed 3.6 V.
VCCI is the supply voltage associated with the input port.
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)(1) (2)
VCCA
TA
VCCB
Operating free-air temperature
MIN
MAX
–40
85
UNIT
°C
6.4 Thermal Information
TXB0108
THERMAL METRIC (1)
PW
RGY
DQS
YZP
GXY
ZXY
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
101.8
35.3
108.5
66.2
156.7
156.7
°C/W
RθJC(to
Junction-to-case (top) thermal resistance
35.5
42.1
32.3
0.4
39.9
39.9
°C/W
RθJB
Junction-to-board thermal resistance
52.8
11.1
42.4
52.0
85.9
85.9
°C/W
ψJT
Junction-to-top characterization parameter
2.2
0.7
0.7
1.5
1.1
1.1
°C/W
ψJB
Junction-to-board characterization parameter
52.2
11.2
42
51.9
85.4
85.4
°C/W
RθJC(b
Junction-to-case (bottom) thermal resistance
–
3.8
–
–
–
–
°C/W
p)
ot)
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (1) (2)
PARAMETER
TEST
CONDITIONS
VCCA
VCCB
1.2 V
IOH = –20 μA
VOLA
IOL = 20 μA
VOHB
IOH = –20 μA
1.65 V to 5.5 V
VOLB
IOL = 20 μA
1.65 V to 5.5 V
OE
Ioff
IOZ
MAX
MIN
MAX
1.2 V
0.3
1.4 V to 3.6 V
0.4
VCCB – 0.4
V
V
μA
1.65 V to 5.5 V
±1
±2
0V
0 V to 5.5 V
±1
±2
B port
0 V to 3.6 V
0V
±1
±2
1.2 V to 3.6 V
1.65 V to 5.5 V
±1
±2
OE = GND
VI = VCCI or GND,
IO = 0
1.4 V to 3.6 V
3.6 V
0V
0V
5.5 V
1.2 V
VI = VCCI or GND,
IO = 0
1.4 V to 3.6 V
ICCA + ICCB
VI = VCCI or GND,
IO = 0
1.2 V
ICCZA
VI = VCCI or GND,
IO = 0,
OE = GND
ICCZB
VI = VCCI or GND,
IO = 0,
OE = GND
ICCB
1.65 V to 5.5 V
1.65 V to 5.5 V
3.6 V
0V
0V
5.5 V
1.4 V to 3.6 V
1.65 V to 5.5 V
1.2 V
1.4 V to 3.6 V
μA
μA
0.06
5
2
μA
–2
3.4
5
–2
μA
2
3.5
10
μA
0.05
1.65 V to 5.5 V
1.2 V
1.4 V to 3.6 V
V
0.4
1.2 V to 3.6 V
A or B port
UNIT
V
VCCA – 0.4
A port
ICCA
6
TYP
1.4 V to 3.6 V
1.2 V
(1)
(2)
MIN
–40°C to 85°C
1.1
VOHA
II
TA = 25°C
5
μA
3.3
1.65 V to 5.5 V
5
μA
VCCI is the supply voltage associated with the input port.
VCCO is the supply voltage associated with the output port.
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Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)(1)(2)
PARAMETER
CI
Cio
TEST
CONDITIONS
OE
A port
VCCB
1.2 V to 3.6 V
1.65 V to 5.5 V
1.2 V to 3.6 V
B port
TA = 25°C
VCCA
MIN
TYP
1.65 V to 5.5 V
–40°C to 85°C
MAX
MIN
MAX
5
5.5
5
6.5
8
10
UNIT
pF
pF
6.6 Timing Requirements: VCCA = 1.2 V
TA = 25°C, VCCA = 1.2 V
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
TYP
TYP
TYP
TYP
20
20
20
20
Mbps
50
50
50
50
ns
Data rate
tw
Pulse duration
Data inputs
UNIT
6.7 Timing Requirements: VCCA = 1.5 V ± 0.1 V
over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (unless otherwise noted)
VCCB = 1.8 V
± 0.15 V
MIN
Data rate
tw
Pulse duration
VCCB = 2.5 V
± 0.2 V
MAX
MIN
MAX
50
Data inputs
VCCB = 3.3 V
± 0.3 V
MIN
MAX
50
20
VCCB = 5 V
± 0.5 V
MIN
50
20
50
20
UNIT
MAX
20
Mbps
ns
6.8 Timing Requirements: VCCA = 1.8 V ± 0.15 V
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted)
VCCB = 1.8 V
± 0.15 V
MIN
Data rate
tw
Pulse duration
VCCB = 2.5 V
± 0.2 V
MAX
MIN
MAX
52
Data inputs
19
VCCB = 3.3 V
± 0.3 V
MIN
VCCB = 5 V
± 0.5 V
MAX
60
MIN
60
17
60
17
UNIT
MAX
17
Mbps
ns
6.9 Timing Requirements: VCCA = 2.5 V ± 0.2 V
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted)
VCCB = 2.5 V
± 0.2 V
MIN
Data rate
tw
Pulse duration
VCCB = 3.3 V
± 0.3 V
MAX
MIN
MAX
70
Data inputs
VCCB = 5 V
± 0.5 V
MIN
100
14
100
10
UNIT
MAX
10
Mbps
ns
6.10 Timing Requirements: VCCA = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted)
VCCB = 3.3 V
± 0.3 V
MIN
Data rate
tw
Pulse duration
VCCB = 5 V
± 0.5 V
MAX
MIN
100
Data inputs
10
UNIT
MAX
100
10
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6.11 Switching Characteristics: VCCA = 1.2 V
TA = 25°C, VCCA = 1.2 V
FROM
(INPUT)
TO
(OUTPUT)
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
TYP
TYP
TYP
TYP
A
B
9.5
7.9
7.6
8.5
B
A
9.2
8.8
8.4
8
A
1
1
1
1
B
1
1
1
1
A
20
17
17
18
B
20
16
15
15
trA, tfA
A-port rise and fall times
4.1
4.4
4.1
3.9
ns
trB, tfB
B-port rise and fall times
5
5
5.1
5.1
ns
tSK(O)
Channel-to-channel skew
2.4
1.7
1.9
7
ns
20
20
20
20
Mbps
PARAMETER
tpd
ten
OE
tdis
OE
Max data rate
UNIT
ns
μs
ns
6.12 Switching Characteristics: VCCA = 1.5 V ± 0.1 V
over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (unless otherwise noted)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
B
ten
OE
tdis
OE
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
B
1.4
12.9
1.2
10.1
1.1
10
0.8
9.9
A
0.9
14.2
0.7
12
0.4
11.7
0.3
13.7
A
1
1
1
1
B
1
1
1
1
ns
μs
A
6.6
33
6.4
25.3
6.1
23.1
5.9
24.6
B
6.6
35.6
5.8
25.6
5.5
22.1
5.6
20.6
A-port rise and fall times
0.8
6.5
0.8
6.3
0.8
6.3
0.8
6.3
ns
trB, tfB
B-port rise and fall times
1
7.3
0.7
4.9
0.7
4.6
0.6
4.6
ns
tSK(O)
Channel-to-channel skew
trA, tfA
Max data rate
2.6
1.9
50
50
1.6
50
1.3
50
ns
ns
Mbps
6.13 Switching Characteristics: VCCA = 1.8 V ± 0.15 V
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
B
ten
OE
tdis
OE
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
B
1.6
11
1.4
7.7
1.3
6.8
1.2
6.5
A
1.5
12
1.2
8.4
0.8
7.6
0.5
7.1
A
1
1
1
1
B
1
1
1
1
ns
μs
A
5.9
26.7
5.6
21.6
5.4
18.9
4.8
18.7
B
6.1
33.9
5.2
23.7
5
19.9
5
17.6
trA, tfA
A-port rise and fall times
0.7
5.1
0.7
5
1
5
0.7
5
ns
trB, tfB
B-port rise and fall times
1
7.3
0.7
5
0.7
3.9
0.6
3.8
ns
tSK(O)
Channel-to-channel skew
0.6
ns
Max data rate
8
VCCB = 1.8 V
± 0.15 V
0.8
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60
0.6
60
60
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6.14 Switching Characteristics: VCCA = 2.5 V ± 0.2 V
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
B
ten
OE
tdis
OE
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
MIN
MAX
B
1.1
A
1
VCCB = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
6.4
1
5.3
0.9
4.7
7
0.6
5.6
0.3
4.4
A
1
1
1
B
1
1
1
A
5
16.9
4.9
15
4.5
13.8
B
4.8
21.8
4.5
17.9
4.4
15.2
ns
μs
ns
trA, tfA
A-port rise and fall times
0.8
3.6
0.6
3.6
0.5
3.5
ns
trB, tfB
B-port rise and fall times
0.6
4.9
0.7
3.9
0.6
3.2
ns
tSK(O)
Channel-to-channel skew
0.3
ns
0.4
Max data rate
0.3
70
100
100
Mbps
6.15 Switching Characteristics: VCCA = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
B
ten
OE
tdis
OE
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
B
0.9
4.9
0.8
4
A
0.5
5.4
0.2
4
A
1
1
B
1
1
ns
μs
A
4.5
13.9
4.1
12.4
B
4.1
17.3
4
14.4
A-port rise and fall times
0.5
3
0.5
3
ns
trB, tfB
B-port rise and fall times
0.7
3.9
0.6
3.2
ns
tSK(O)
Channel-to-channel skew
trA, tfA
0.4
Max data rate
ns
0.3
100
ns
100
Mbps
6.16 Operating Characteristics
TA = 25°C
VCCA
1.2 V
1.2 V
1.5 V
1.8 V
2.5 V
2.5 V
3.3 V
5V
3.3 V
to
5V
VCCB
PARAMETER
TEST CONDITIONS
5V
CpdA
CpdB
CpdA
CpdB
A-port input, B-port output
B-port input, A-port output
A-port input, B-port output
B-port input, A-port output
A-port input, B-port output
B-port input, A-port output
A-port input, B-port output
B-port input, A-port output
CL = 0, f = 10 MHz,
tr = tf = 1 ns,
OE = VCCA
(outputs enabled)
CL = 0, f = 10 MHz,
tr = tf = 1 ns,
OE = GND
(outputs disabled)
1.8 V
1.8 V
1.8 V
2.5 V
UNIT
TYP
TYP
TYP
TYP
TYP
TYP
TYP
9
8
7
7
7
7
8
12
11
11
11
11
11
11
35
26
27
27
27
27
28
26
19
18
18
18
20
21
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.03
0.01
0.01
0.01
0.01
0.01
0.01
0.03
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6.17 Typical Characteristics
VCCB = 3.3 V
VCCB = 3.3 V
Figure 1. Input Capacitance for OE Pin (CI) vs Power Supply
(VCCA)
Figure 2. Capacitance for A Port I/O Pins (CIO) vs Power
Supply (VCCA)
VCCA = 1.8 V
Figure 3. Capacitance fpr B Port I/O Pins (CIO) vs Power Supply (VCCB)
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7 Parameter Measurement Information
2 × VCCO
From Output
Under Test
15 pF
15 pF
1 MW
Open
50 kW
TEST
tPZL/tPLZ
tPHZ/tPZH
LOAD CIRCUIT FOR
ENABLE/DISABLE
TIME MEASUREMENT
LOAD CIRCUIT FOR MAX DATA RATE,
PULSE DURATION PROPAGATION
DELAY OUTPUT RISE AND FALL TIME
MEASUREMENT
S1
50 kW
From Output
Under Test
S1
2 × VCCO
Open
VCCI
Input
VCCI/2
VCCI/2
0V
tPLH
tPHL
tw
Output
VCCO/2
0.9 y VCCO
0.1 y VCCO
VOH
tf
tr
VCCI
VCCO/2
VOL
Input
VCCI/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
A.
B.
C.
D.
E.
F.
G.
VCCI/2
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns.
The outputs are measured one at a time, with one transition per measurement.
tPLH and tPHL are the same as tpd.
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuits and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The TXB0108 device is an 8-bit, directionless voltage-level translator specifically designed for translating logic
voltage levels. The A port is able to accept I/O voltages ranging from 1.2 V to 3.6 V, while the B port can accept
I/O voltages from 1.65 V to 5.5 V. The device is a buffered architecture with edge-rate accelerators (one-shots)
to improve the overall data rate. This device can only translate push-pull CMOS logic outputs. If for open-drain
signal translation, please refer to TI TXS products.
8.2 Functional Block Diagram
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8.3 Feature Description
8.3.1 Architecture
The TXB0108 architecture (see Figure 5) does not require a direction-control signal to control the direction of
data flow from A to B or from B to A. In a dc state, the output drivers of the TXB0108 can maintain a high or low,
but are designed to be weak so that they can be overdriven by an external driver when data on the bus starts
flowing the opposite direction. The output one-shots detect rising or falling edges on the A or B ports. During a
rising edge, the one-shot turns on the PMOS transistors (T1, T3) for a short duration, which speeds up the lowto-high transition. Similarly, during a falling edge, the one-shot turns on the NMOS transistors (T2, T4) for a short
duration, which speeds up the high-to-low transition. The typical output impedance during output transition is 70
Ω at VCCO = 1.2 V to 1.8 V, 50 Ω at VCCO = 1.8 V to 3.3 V and 40 Ω at VCCO = 3.3 V to 5 V.
VCCA
VCCB
One
Shot
T1
4k
One
Shot
T2
A
B
One
Shot
T3
4k
T4
One
Shot
Figure 5. Architecture of TXB0108 I/O Cell
8.3.2 Input Driver Requirements
Typical IIN vs VIN characteristics of the TXB0108 are shown in Figure 6. For proper operation, the device driving
the data I/Os of the TXB0108 must have drive strength of at least ±2 mA.
IIN
VT/4 kW
VIN
–(VD – VT)/4 kW
A. VT is the input threshold voltage of the TXB0108 (typically VCCI/2).
B. VD is the supply voltage of the external driver.
Figure 6. Typical IIN vs VIN Curve
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Feature Description (continued)
8.3.3 Output Load Considerations
TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading
and to ensure that proper O.S. triggering takes place. PCB signal trace-lengths should be kept short enough
such that the round-trip delay of any reflection is less than the one-shot duration. This improves signal integrity
by ensuring that any reflection sees a low impedance at the driver. The O.S. circuits have been designed to stay
on for approximately 10 ns. The maximum capacitance of the lumped load that can be driven also depends
directly on the one-shot duration. With very heavy capacitive loads, the one-shot can time-out before the signal is
driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between dynamic ICC,
load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to the
capacitance that the TXB0108 output sees, so it is recommended that this lumped-load capacitance be
considered to avoid O.S. re-triggering, bus contention, output signal oscillations, or other adverse system-level
affects.
8.3.4 Enable and Disable
The TXB0108 has an OE input that is used to disable the device by setting OE = low, which places all I/Os in the
high-impedance (Hi-Z) state. The disable time (tdis) indicates the delay between when OE goes low and when
the outputs actually get disabled (Hi-Z). The enable time (ten) indicates the amount of time the user must allow
for the one-shot circuitry to become operational after the OE is high.
8.3.5 Pullup or Pulldown Resistors on I/O Lines
The TXB0108 is designed to drive capacitive loads of up to 70 pF. The output drivers of the TXB0108 have low
dc drive strength. If pullup or pulldown resistors are connected externally to the data I/Os, their values must be
kept higher than 50 kΩ to ensure that they do not contend with the output drivers of the TXB0108. For the same
reason, the TXB0108 should not be used in applications such as I2C or 1-Wire where an open-drain driver is
connected on the bidirectional data I/O. For these applications, use a device from the TI TXS01xx series of level
translators.
8.4 Device Functional Modes
The TXB0108 device has two functional modes, enabled and disabled. To disable the device, set the OE input
low, which places all I/Os in a high impedance state. Setting the OE input high will enable the device.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TXB0108 can be used in level-translation applications for interfacing devices or systems operating at
different interface voltages with one another. It can only translate push-pull CMOS logic outputs. If for open-drain
signal translation, please refer to TI TXS010X products. Any external pulldown or pullup resistors are
recommended to be larger than 50kΩ.
9.2 Typical Application
Figure 7. Typical Operating Circuit
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 1. Make sure the VCCA ≤VCCB.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
1.2 V to 3.6 V
Output voltage range
1.65 V to 5.5 V
9.2.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
- Use the supply voltage of the device that is driving the TXB0108 device to determine the input voltage
range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low, the
value must be less than the VIL of the input port.
• Output voltage range
- Use the supply voltage of the device that the TXB0108 device is driving to determine the output voltage
range.
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- Do not recommend having the external pullup or pulldown resistors. If mandatory, it is recommended
the value should be larger than 50 kΩ.
• An external pulldown or pullup resistor decreases the output VOH and VOL. Use the below equations to draft
estimate the VOH and VOL as a result of an external pulldown and pullup resistor.
VOH = VCCx × RPD / (RPD + 4.5 kΩ)
VOL = VCCx × 4.5kΩ / (RPU + 4.5 kΩ)
Where:
• VCCx is the output port supply voltage on either VCCA or VCCB
• RPD is the value of the external pull down resistor
• RPU is the value of the external pull up resistor
• 4.5 kΩ is the counting the variation of the serial resistor 4 kΩ in the I/O line. Refer to the Effects
of external pullup and pulldown resistors on TXB application note
9.2.3 Application Curves
Figure 8. Level-Translation of a 2.5-MHz Signal
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10 Power Supply Recommendations
During operation, ensure that VCCA ≤ VCCB at all times. During power-up sequencing, VCCA ≥ VCCB does not
damage the device, so any power supply can be ramped up first. The TXB0108 has circuitry that disables all
output ports when either VCC is switched off (VCCA/B = 0 V).
The output-enable (OE) input circuit is designed so that it is supplied by VCCA and when the (OE) input is low, all
outputs are placed in the high-impedance state. To ensure the high-impedance state of the outputs during
power-up or power-down, the OE input pin must be tied to GND through a pulldown resistor and must not be
enabled until VCCA and VCCB are fully ramped and stable. The minimum value of the pulldown resistor to ground
is determined by the current-sourcing capability of the driver.
11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, the following common printed-circuit board layout guidelines is recommended.
• Bypass capacitors should be used on power supplies and should be placed as close as possible to the VCCA,
VCCB pin and GND pin.
• Short trace lengths should be used to avoid excessive loading.
• PCB signal trace-lengths must be kept short enough so that the round-trip delay of any reflection is less than
the one-shot duration, approximately 10 ns, ensuring that any reflection encounters low impedance at the
source driver.
11.2 Layout Example
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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13.1 Package Addendum
13.1.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
P1
K0
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
TXB0108DQSR
USON
DQS
20
3000
177.8
12.4
2.21
4.22
0.81
4.0
12.0
Q1
TXB0108RGYR
VQFN
RGY
20
3000
330.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
TXB0108YZPR
DSBGA
YZP
20
3000
180.0
8.4
1.99
2.49
0.56
4.0
8.0
Q1
TXB0108YZPR2
DSBGA
YZP
20
3000
180.0
8.4
1.99
2.49
0.56
4.0
8.0
Q2
TXB0108ZXYR
BGA
MICROSTAR
JUNIOR
ZXY
20
2500
330.0
12.4
2.8
4.22
3.3
1.0
12.0
Q2
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
L
W
20
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TXB0108DQSR
USON
DQS
20
3000
202.0
201.0
28.0
TXB0108RGYR
VQFN
RGY
20
3000
355.0
350.0
50.0
TXB0108YZPR
DSBGA
YZP
20
3000
182.0
182.0
20.0
TXB0108YZPR2
DSBGA
YZP
20
3000
182.0
182.0
20.0
TXB0108ZXYR
BGA
MICROSTAR
JUNIOR
ZXY
20
2500
336.6
336.6
28.6
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14-Dec-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TXB0108DQSR
ACTIVE
USON
DQS
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
5MR
5MH
TXB0108PWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
YE08
TXB0108PWRG4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
YE08
TXB0108RGYR
ACTIVE
VQFN
RGY
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
YE08
TXB0108YZPR
ACTIVE
DSBGA
YZP
20
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
5M
TXB0108YZPR2
ACTIVE
DSBGA
YZP
20
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
EK
TXB0108ZXYR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZXY
20
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
YE08
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Dec-2018
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TXB0108DQSR
USON
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DQS
20
3000
177.8
12.4
2.21
4.22
0.81
4.0
12.0
Q1
TXB0108PWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.0
1.4
8.0
16.0
Q1
TXB0108RGYR
VQFN
RGY
20
3000
330.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
TXB0108YZPR
DSBGA
YZP
20
3000
180.0
8.4
1.99
2.49
0.56
4.0
8.0
Q1
TXB0108YZPR2
DSBGA
YZP
20
3000
180.0
8.4
1.99
2.49
0.56
4.0
8.0
Q2
TXB0108ZXYR
BGA MI
CROSTA
R JUNI
OR
ZXY
20
2500
330.0
12.4
2.8
3.3
1.0
4.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TXB0108DQSR
USON
DQS
20
3000
202.0
201.0
28.0
TXB0108PWR
TSSOP
PW
20
2000
367.0
367.0
38.0
TXB0108RGYR
VQFN
RGY
20
3000
367.0
367.0
35.0
TXB0108YZPR
DSBGA
YZP
20
3000
182.0
182.0
20.0
TXB0108YZPR2
DSBGA
YZP
20
3000
182.0
182.0
20.0
TXB0108ZXYR
BGA MICROSTAR
JUNIOR
ZXY
20
2500
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
ZXY0020A
VFBGA - 0.61 mm max height
SCALE 4.800
PLASTIC BALL GRID ARRAY
3.1
2.9
B
A
BALL A1 CORNER
2.6
2.4
C
0.61 MAX
SEATING PLANE
0.25
TYP
0.15
BALL TYP
0.08 C
2 TYP
SYMM
(0.5) TYP
D
(0.5) TYP
1.5
TYP
C
SYMM
B
20X
A
0.5 TYP
1
PIN 1 ID
(WITHOUT SOLDER)
2
3
4
5
0.35
0.25
0.15
0.05
C B A
C
0.5 TYP
4222996/A 12/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ZXY0020A
VFBGA - 0.61 mm max height
PLASTIC BALL GRID ARRAY
(0.5) TYP
20X ( 0.25)
1
2
3
5
4
A
(0.5) TYP
B
SYMM
C
D
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:25X
( 0.25)
METAL
0.05 MAX
METAL UNDER
SOLDER MASK
0.05 MIN
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
( 0.25)
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NOT TO SCALE
4222996/A 12/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ZXY0020A
VFBGA - 0.61 mm max height
PLASTIC BALL GRID ARRAY
(0.5) TYP
20X ( 0.25)
1
2
3
4
5
A
(0.5) TYP
B
SYMM
C
(R0.05) TYP
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 25X
4222996/A 12/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
D: Max = 2.418 mm, Min =2.358 mm
E: Max = 1.918 mm, Min =1.858 mm
GENERIC PACKAGE VIEW
RGY 20
VQFN - 1 mm max height
PLASTIC QUAD FGLATPACK - NO LEAD
3.5 x 4.5, 0.5 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225264/A
www.ti.com
PACKAGE OUTLINE
RGY0020A
VQFN - 1 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
3.65
3.35
A
B
PIN 1 INDEX AREA
4.65
4.35
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
2.05 0.1
2X 1.5
(0.2) TYP
10
11
9
EXPOSED
THERMAL PAD
12
14X 0.5
2X
3.5
21
SYMM
3.05 0.1
2
PIN 1 ID
19
20X
20
1
SYMM
0.30
0.18
0.1
0.05
0.5
20X
0.3
C A B
4225320/A 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGY0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.05)
SYMM
1
20
20X (0.6)
2
19
20X (0.24)
(1.275)
(4.3)
21
SYMM
(3.05)
14X (0.5)
(0.775)
9
12
(R0.05) TYP
( 0.2) TYP
VIA
11
10
(0.75) TYP
(3.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4225320/A 09/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGY0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
4X (0.92)
(R0.05) TYP
20
1
20X (0.6)
2
19
20X (0.24)
4X
(1.33)
21
SYMM
(4.3)
(0.77)
14X (0.5)
(0.56)
9
12
METAL
TYP
11
10
(0.75)
TYP
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 21
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4225320/A 09/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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