Texas Instruments | SN74AXC4T774 4-Bit Dual-Supply Bus Transceiver with Independent Direction Control, Configurable Voltage Translation, and Tri-State Outputs | Datasheet | Texas Instruments SN74AXC4T774 4-Bit Dual-Supply Bus Transceiver with Independent Direction Control, Configurable Voltage Translation, and Tri-State Outputs Datasheet

Texas Instruments SN74AXC4T774 4-Bit Dual-Supply Bus Transceiver with Independent Direction Control, Configurable Voltage Translation, and Tri-State Outputs Datasheet
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SN74AXC4T774
SCES898 – JULY 2019
SN74AXC4T774 4-Bit Dual-Supply Bus Transceiver with Independent Direction Control,
Configurable Voltage Translation, and Tri-State Outputs
1 Features
•
1
•
•
•
•
•
•
•
•
•
Fully configurable dual-rail design allows each
port to operate with a power supply range from
0.65 V to 3.6 V
Operating temperature from –40°C to +125°C
Independent direction control pins to allow
configurable up and down translation
Glitch-free power supply sequencing
Up to 310 Mbps support when translating from 1.8
V to 3.3 V
VCC isolation feature
– If either VCC input is below 100 mV, all I/Os
outputs are disabled and become highimpedance
Ioff supports partial-power-down mode operation
Compatible with AVC family level shifters
Latch-up performance exceeds 100 mA per JESD
78, Class II
ESD protection exceeds JESD 22
– 8000-V human-body model
– 1000-V charged-device model
The SN74AXC4T774 device is designed for
asynchronous communication between data buses.
The device transmits data from the A bus to the B
bus or from the B bus to the A bus, depending on the
logic level of the direction-control inputs (DIRx). The
output-enable input (OE) is used to disable the
outputs so the buses are effectively isolated. The
SN74AXC4T774 device is designed so the control
pins (DIRx and OE) are referenced to VCCA.
To ensure the high-impedance state of the level
shifter I/Os during power up or power down, the OE
pin should be tied to VCCA through a pullup resistor.
This device is fully specified for partial-power-down
applications using the Ioff current. The Ioff protection
circuitry ensures that no excessive current is drawn
from or to an input, output, or combined I/O that is
biased to a specific voltage while the device is
powered down.
The VCC isolation feature ensures that if either VCCA
or VCCB is less than 100 mV, both I/O ports are set to
the high-impedance state by disabling their outputs.
Glitch-free power supply sequencing allows either
supply rail to be powered on or off in any order while
providing robust power sequencing performance.
2 Applications
•
•
•
•
•
•
Enterprise and communications
Industrial
Personal electronics
Wireless infrastructure
Building automation
Point of sale
Device Information(1)
PART NUMBER
BODY SIZE (NOM)
TSSOP (16)
5.00 mm x 4.40 mm
SN74AXC4T774RSV
UQFN (16)
2.60 mm x 1.80 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
One of Four Transceivers
3 Description
The SN74AXC4T774 is a four-bit non-inverting bus
transceiver that uses two individually configurable
power-supply rails. The device is operational with
both VCCA and VCCB supplies as low as 0.65 V. The A
port is designed to track VCCA, which accepts any
supply voltage from 0.65 V to 3.6 V. The B port is
designed to track VCCB, which also accepts any
supply voltage from 0.65 V to 3.6 V. Additionally the
SN74AXC4T774 is compatible with a single-supply
system.
PACKAGE
SN74AXC4T774PW
VCCA
VCCB
DIRx
OE
Ax
Bx
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AXC4T774
SCES898 – JULY 2019
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
7
7.1 Load Circuit and Voltage Waveforms ..................... 18
1
1
1
2
3
4
8
Detailed Description ............................................ 20
8.1
8.2
8.3
8.4
9
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Switching Characteristics, VCCA = 0.7 ± 0.05 V ........ 7
Switching Characteristics, VCCA = 0.8 ± 0.04 V ........ 8
Switching Characteristics, VCCA = 0.9 ± 0.045 V ...... 9
Switching Characteristics, VCCA = 1.2 ± 0.1 V ........ 10
Switching Characteristics, VCCA = 1.5 ± 0.1 V ...... 11
Switching Characteristics, VCCA = 1.8 ± 0.15 V .... 12
Switching Characteristics, VCCA = 2.5 ± 0.2 V ...... 13
Switching Characteristics, VCCA = 3.3 ± 0.3 V ...... 14
Operating Characteristics: TA = 25°C ................... 15
Typical Characteristics .......................................... 17
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
20
20
20
21
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Application ................................................. 22
10 Power Supply Recommendations ..................... 24
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 24
12 Device and Documentation Support ................. 25
12.1
12.2
12.3
12.4
12.5
12.6
Related Documentation .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
Parameter Measurement Information ................ 18
4 Revision History
2
DATE
REVISION
NOTES
July 2019
*
Initial release.
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SCES898 – JULY 2019
5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
DIR1
RSV Package
16-Pin UQFN
Transparent Top View
3
14
B1
A2
4
13
B2
A1
1
12
B1
A3
5
12
11
B3
A2
2
11
B2
B4
A3
3
10
B3
10
9
GND
A4
4
9
B4
8
OE
13
5
6
7
8
OE
DIR4
14
GND
7
15
DIR4
6
16
DIR3
A4
DIR3
VCCB
A1
VCCA
VCCA
VCCB
DIR1
15
DIR2
1
2
16
DIR2
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
PW
RSV
A1
3
1
I/O
Input/output A1. Referenced to VCCA.
A2
4
2
I/O
Input/output A2. Referenced to VCCA.
A3
5
3
I/O
Input/output A3. Referenced to VCCA.
A4
6
4
I/O
Input/output A4. Referenced to VCCA.
B1
14
12
I/O
Input/output B1. Referenced to VCCB.
B2
13
11
I/O
Input/output B2. Referenced to VCCB.
B3
12
10
I/O
Input/output B3. Referenced to VCCB.
B4
11
9
I/O
Input/output B4. Referenced to VCCB.
DIR1
1
15
I
Direction-control input for port 1. Referenced to VCCA.
DIR2
2
16
I
Direction-control input for port 2. Referenced to VCCA.
DIR3
7
5
I
Direction-control input for port 3. Referenced to VCCA.
DIR4
8
6
I
Direction-control input for port 4. Referenced to VCCA.
OE
9
7
I
Tri-state output enable. Pull OE high to place all outputs in tri-state mode.
Referenced to VCCA.
GND
10
8
—
Ground
VCCA
16
14
—
A-port power supply voltage. 0.65 V ≤ VCCA ≤ 3.6 V
VCCB
15
13
—
B-port power supply voltage. 0.65 V ≤ VCCB ≤ 3.6 V
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCCA
Supply voltage A
VCCB
Supply voltage B
Input Voltage (2)
VI
MIN
MAX
–0.5
4.2
V
V
–0.5
4.2
I/O Ports (A Port)
–0.5
4.2
I/O Ports (B Port)
–0.5
4.2
Control Inputs
–0.5
4.2
A Port
–0.5
4.2
B Port
–0.5
4.2
A Port
–0.5 VCCA + 0.2
B Port
–0.5 VCCB + 0.2
UNIT
V
VO
Voltage applied to any output in the high-impedance or power-off state (2)
VO
Voltage applied to any output in the high or low state (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
Continuous current through VCC or GND
Tj
Junction Temperature
Tstg
Storage temperature
(1)
(2)
(3)
V
V
–50
50
mA
–100
100
mA
150
°C
150
°C
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The output positive-voltage rating may be exceeded up to 4.2 V maximum if the output current rating is observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±8000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN
MAX
UNIT
VCCA
Supply voltage A
0.65
3.6
V
VCCB
Supply voltage B
0.65
3.6
V
Data Inputs
VCCI = 0.65 V - 0.75 V
VCCI x 0.70
VCCI = 0.76 V - 1 V
VCCI x 0.70
VCCI = 1.1 V - 1.95 V
VCCI x 0.65
VCCI = 2.3 V - 2.7 V
VIH
1.6
VCCI = 3 V - 3.6 V
High-level input voltage
Control Inputs(DIRx,
OE), Referenced to VCCA
2
VCCA = 0.65 V - 0.75 V
VCCA x 0.70
VCCA = 0.76 V - 1 V
VCCA x 0.70
VCCA = 1.1 V - 1.95 V
VCCA x 0.65
VCCA = 2.3 V - 2.7 V
1.6
VCCA = 3 V - 3.6 V
Data Inputs
VIL
Low-level input voltage
Control Inputs(DIRx,
OE), Referenced to VCCA
2
VCCI = 0.65 V - 0.75 V
VCCI x 0.30
VCCI = 0.76 V - 1 V
VCCI x 0.30
VCCI = 1.1 V - 1.95 V
VCCI x 0.35
VCCI = 2.3 V - 2.7 V
0.7
VCCI = 3 V - 3.6 V
0.8
VCCA = 0.65 V - 0.75 V
VCCA x 0.30
VCCA = 0.76 V - 1 V
VCCA x 0.30
VCCA = 1.1 V - 1.95 V
VCCA x 0.35
VCCA = 2.3 V - 2.7 V
0.7
VCCA = 3 V - 3.6 V
VI
Input voltage
0.8
(3)
0
3.6
Active State
0
VCCO
Tri-State
0
3.6
10
ns/V
–40
125
°C
VO
Output voltage
Δt/Δv (2)
Input transition rise and fall time
TA
Operating free-air temperature
(1)
(2)
(3)
V
V
V
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
6.4 Thermal Information
SN74AXC4T774
THERMAL METRIC
PW (TSSOP)
RSV (UQFN)
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
118.2
130.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
48.6
69.1
°C/W
RθJB
Junction-to-board thermal resistance
64.5
59.9
°C/W
YJT
Junction-to-top characterization parameter
7.3
3.9
°C/W
YJB
Junction-to-board characterization parameter
63.9
58.3
°C/W
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
(1) (2)
Operating free-air temperature (TA)
PARAMETER
TEST CONDITIONS
VCCA
VCCB
-40°C to 85°C
MIN
High-level
output
voltage
VOH
Low-level
output
voltage
VOL
VI = VIH
VI = VIL
Partial power
down current
Ioff
TYP
UNIT
MAX
0.65 V
0.55
0.55
0.76 V
0.58
0.58
0.85 V
0.85 V
0.65
0.65
IOH = -3 mA
1.1 V
1.1 V
0.85
0.85
IOH = -6 mA
1.4 V
1.4 V
1.05
1.05
IOH = -8 mA
1.65 V
1.65 V
1.2
1.2
IOH = -9 mA
2.3 V
2.3 V
1.75
1.75
IOH = -12 mA
3V
3V
IOL = 100 µA
0.7 V - 3.6 V
0.7 V - 3.6 V
0.1
0.1
IOL = 50 µA
0.65 V
0.65 V
0.1
0.1
IOL = 200 µA
0.76 V
0.76 V
0.18
0.18
IOL = 500 µA
0.85 V
0.85 V
0.2
0.2
IOL = 3 mA
1.1 V
1.1 V
0.25
0.25
IOL = 6 mA
1.4 V
1.4 V
0.35
0.35
IOL = 8 mA
1.65 V
1.65 V
0.45
0.45
IOL = 9 mA
2.3 V
2.3 V
0.55
0.55
IOL = 12 mA
3V
3V
0.7
0.7
0.7 V - 3.6 V
IOH = -50 µA
0.65 V
IOH = -200 µA
0.76 V
IOH = -500 µA
2.3
V
2.3
V
0.65 V- 3.6 V 0.65 V- 3.6 V
–0.5
0.5
–1
1
µA
0.65 V- 3.6 V 0.65 V- 3.6 V
–4
4
–8
8
µA
A Port: VI or VO = 0 V 3.6 V
0V
0 V - 3.6 V
–4
4
–8
8
B Port: VI or VO = 0 V 3.6 V
0 V - 3.6 V
0V
–4
4
–8
8
3.6 V
–4
4
–8
8
µA
Tri-state
output
current (3)
A or B Port, VI = VCCI or
GND, VO = VCCO or GND, 3.6 V
OE = VIH
ICCA
VCCA supply
current
VI =
VCCI or
GND
IO = 0
VI =
VCCI or
GND
IO = 0
IO = 0
VCCB supply
current
MIN
VCCO
– 0.1
0.7 V - 3.6 V
IOZ
ICCB
-40°C to 125°C
MAX
VCCO
– 0.1
IOH = -100 µA
Control inputs (DIRx,
Input leakage OE):VI = VCCA or GND
current
Data Inputs (Ax, Bx),VI =
VCCI or GND
II
TYP
0.65 V- 3.6 V 0.65 V- 3.6 V
0V
3.6 V
3.6 V
0V
15
–2
27
–12
µA
10
18
0.65 V- 3.6 V 0.65 V- 3.6 V
15
27
0V
3.6 V
10
3.6 V
0V
–2
µA
18
µA
40
µA
–12
ICCA +
ICCB
Combined
supply
current
VI =
VCCI or
GND
Ci
Control Input
Capacitance
VI = 3.3 V or GND
3.3 V
3.3 V
4.5
4.5
pF
Cio
Data I/O
Capacitance
OE = VCCA, VO = 1.65V
DC +1 MHz -16 dBm sine
wave
3.3 V
3.3 V
6.5
6.5
pF
(1)
(2)
(3)
6
0.65 V- 3.6 V 0.65 V- 3.6 V
21
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
For I/O ports, the parameter IOZ includes the input leakage current.
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6.6 Switching Characteristics, VCCA = 0.7 ± 0.05 V
See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.
B-Port Supply Voltage (VCCB)
PARAMETER
FROM
A
tpd
tdis
B
Propagation
delay
B
A
OE
A
Disable time
OE
OE
ten
TO
B
A
Enable time
OE
B
Test Conditions
0.7 ± 0.05 V
0.8 ± 0.04 V
0.9 ± 0.045 V
1.2 ± 0.1 V
1.5 ± 0.1 V
2.5 ± 0.2 V
3.3 ± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1.8 ± 0.15 V
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
-40°C to 85°C
0.5
172
0.5
120
0.5
88
0.5
51
0.5
46
0.5
56
0.5
78
0.5
221
-40°C to 125°C
0.5
172
0.5
120
0.5
88
0.5
51
0.5
46
0.5
56
0.5
78
0.5
221
-40°C to 85°C
0.5
172
0.5
141
0.5
109
0.5
51
0.5
16
0.5
12
0.5
9
0.5
9
-40°C to 125°C
0.5
172
0.5
141
0.5
109
0.5
51
0.5
16
0.5
12
0.5
9
0.5
9
-40°C to 85°C
0.5
205
0.5
205
0.5
205
0.5
205
0.5
205
0.5
205
0.5
205
0.5
205
-40°C to 125°C
0.5
205
0.5
205
0.5
205
0.5
205
0.5
205
0.5
205
0.5
205
0.5
205
-40°C to 85°C
0.5
189
0.5
161
0.5
145
0.5
102
0.5
99
0.5
102
0.5
113
0.5
176
-40°C to 125°C
0.5
189
0.5
161
0.5
145
0.5
102
0.5
99
0.5
102
0.5
113
0.5
176
-40°C to 85°C
0.5
287
0.5
287
0.5
287
0.5
287
0.5
287
0.5
287
0.5
287
0.5
287
-40°C to 125°C
0.5
287
0.5
287
0.5
287
0.5
287
0.5
287
0.5
287
0.5
287
0.5
287
-40°C to 85°C
0.5
309
0.5
219
0.5
177
0.5
133
0.5
127
0.5
132
0.5
165
0.5
418
-40°C to 125°C
0.5
309
0.5
219
0.5
177
0.5
133
0.5
127
0.5
132
0.5
165
0.5
418
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ns
ns
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6.7 Switching Characteristics, VCCA = 0.8 ± 0.04 V
See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.
B-Port Supply Voltage (VCCB)
PARAMETER
FROM
A
tpd
tdis
B
A
OE
A
Disable time
OE
B
A
Enable time
OE
8
B
Propagation
delay
OE
ten
TO
B
Test Conditions
0.7 ± 0.05 V
0.8 ± 0.04 V
0.9 ± 0.045 V
1.2 ± 0.1 V
1.5 ± 0.1 V
2.5 ± 0.2 V
3.3 ± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
-40°C to 85°C
0.5
141
0.5
96
0.5
73
0.5
39
0.5
29
0.5
28
0.5
29
0.5
40
-40°C to 125°C
0.5
141
0.5
96
0.5
73
0.5
39
0.5
29
0.5
28
0.5
29
0.5
40
-40°C to 85°C
0.5
120
0.5
96
0.5
76
0.5
39
0.5
16
0.5
11
0.5
9
0.5
9
-40°C to 125°C
0.5
120
0.5
96
0.5
76
0.5
39
0.5
16
0.5
12
0.5
9
0.5
9
-40°C to 85°C
0.5
114
0.5
114
0.5
114
0.5
114
0.5
114
0.5
114
0.5
114
0.5
114
-40°C to 125°C
0.5
114
0.5
114
0.5
114
0.5
114
0.5
114
0.5
114
0.5
114
0.5
114
-40°C to 85°C
0.5
156
0.5
131
0.5
116
0.5
71
0.5
67
0.5
68
0.5
70
0.5
84
-40°C to 125°C
0.5
156
0.5
131
0.5
116
0.5
71
0.5
67
0.5
68
0.5
70
0.5
84
-40°C to 85°C
0.5
161
0.5
161
0.5
161
0.5
161
0.5
161
0.5
161
0.5
161
0.5
161
-40°C to 125°C
0.5
161
0.5
161
0.5
161
0.5
161
0.5
161
0.5
161
0.5
161
0.5
161
-40°C to 85°C
0.5
258
0.5
174
0.5
137
0.5
90
0.5
73
0.5
71
0.5
77
0.5
106
-40°C to 125°C
0.5
258
0.5
174
0.5
137
0.5
90
0.5
73
0.5
71
0.5
77
0.5
106
Submit Documentation Feedback
1.8 ± 0.15 V
UNIT
ns
ns
ns
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: SN74AXC4T774
SN74AXC4T774
www.ti.com
SCES898 – JULY 2019
6.8 Switching Characteristics, VCCA = 0.9 ± 0.045 V
See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.
B-Port Supply Voltage (VCCB)
PARAMETER
FROM
A
tpd
tdis
B
Propagation
delay
B
A
OE
A
Disable time
OE
OE
ten
TO
B
A
Enable time
OE
B
Test Conditions
0.7 ± 0.05 V
0.8 ± 0.04 V
0.9 ± 0.045 V
1.2 ± 0.1 V
1.5 ± 0.1 V
2.5 ± 0.2 V
3.3 ± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1.8 ± 0.15 V
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
-40°C to 85°C
0.5
109
0.5
76
0.5
60
0.5
33
0.5
23
0.5
21
0.5
21
0.5
24
-40°C to 125°C
0.5
109
0.5
76
0.5
60
0.5
33
0.5
23
0.5
21
0.5
21
0.5
24
-40°C to 85°C
0.5
88
0.5
73
0.5
60
0.5
33
0.5
16
0.5
11
0.5
9
0.5
9
-40°C to 125°C
0.5
88
0.5
73
0.5
60
0.5
33
0.5
16
0.5
12
0.5
9
0.5
9
-40°C to 85°C
0.5
83
0.5
83
0.5
83
0.5
83
0.5
83
0.5
83
0.5
83
0.5
83
-40°C to 125°C
0.5
83
0.5
83
0.5
83
0.5
83
0.5
83
0.5
83
0.5
83
0.5
83
-40°C to 85°C
0.5
138
0.5
112
0.5
97
0.5
51
0.5
46
0.5
46
0.5
46
0.5
54
-40°C to 125°C
0.5
138
0.5
112
0.5
97
0.5
51
0.5
46
0.5
46
0.5
46
0.5
54
-40°C to 85°C
0.5
94
0.5
94
0.5
94
0.5
94
0.5
94
0.5
94
0.5
94
0.5
94
-40°C to 125°C
0.5
94
0.5
94
0.5
94
0.5
94
0.5
94
0.5
94
0.5
94
0.5
94
-40°C to 85°C
0.5
203
0.5
140
0.5
110
0.5
70
0.5
52
0.5
45
0.5
43
0.5
51
-40°C to 125°C
0.5
203
0.5
140
0.5
110
0.5
74
0.5
54
0.5
47
0.5
43
0.5
51
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: SN74AXC4T774
ns
ns
ns
9
SN74AXC4T774
SCES898 – JULY 2019
www.ti.com
6.9 Switching Characteristics, VCCA = 1.2 ± 0.1 V
See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.
B-Port Supply Voltage (VCCB)
PARAMETER
FROM
A
tpd
tdis
B
A
OE
A
Disable time
OE
B
A
Enable time
OE
10
B
Propagation
delay
OE
ten
TO
B
Test Conditions
0.7 ± 0.05 V
0.8 ± 0.04 V
0.9 ± 0.045 V
1.2 ± 0.1 V
1.5 ± 0.1 V
2.5 ± 0.2 V
3.3 ± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
-40°C to 85°C
0.5
50
0.5
39
0.5
33
0.5
20
0.5
14
0.5
12
0.5
10
0.5
12
-40°C to 125°C
0.5
50
0.5
39
0.5
33
0.5
20
0.5
14
0.5
12
0.5
10
0.5
12
-40°C to 85°C
0.5
51
0.5
39
0.5
33
0.5
20
0.5
15
0.5
11
0.5
8
0.5
7
-40°C to 125°C
0.5
51
0.5
39
0.5
33
0.5
20
0.5
15
0.5
12
0.5
8
0.5
7
-40°C to 85°C
0.5
28
0.5
28
0.5
28
0.5
28
0.5
28
0.5
28
0.5
28
0.5
28
-40°C to 125°C
0.5
29
0.5
29
0.5
29
0.5
29
0.5
29
0.5
29
0.5
29
0.5
29
-40°C to 85°C
0.5
123
0.5
95
0.5
78
0.5
33
0.5
26
0.5
25
0.5
23
0.5
26
-40°C to 125°C
0.5
124
0.5
95
0.5
79
0.5
34
0.5
27
0.5
26
0.5
24
0.5
26
-40°C to 85°C
0.5
39
0.5
39
0.5
39
0.5
39
0.5
39
0.5
39
0.5
39
0.5
39
-40°C to 125°C
0.5
40
0.5
40
0.5
40
0.5
40
0.5
40
0.5
40
0.5
40
0.5
40
-40°C to 85°C
0.5
124
0.5
87
0.5
70
0.5
51
0.5
38
0.5
33
0.5
26
0.5
25
-40°C to 125°C
0.5
124
0.5
87
0.5
70
0.5
55
0.5
42
0.5
36
0.5
28
0.5
26
Submit Documentation Feedback
1.8 ± 0.15 V
UNIT
ns
ns
ns
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: SN74AXC4T774
SN74AXC4T774
www.ti.com
SCES898 – JULY 2019
6.10 Switching Characteristics, VCCA = 1.5 ± 0.1 V
See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.
B-Port Supply Voltage (VCCB)
PARAMETER
FROM
A
tpd
tdis
B
Propagation
delay
B
A
OE
A
Disable time
OE
OE
ten
TO
B
A
Enable time
OE
B
Test Conditions
0.7 ± 0.05 V
0.8 ± 0.04 V
0.9 ± 0.045 V
1.2 ± 0.1 V
1.5 ± 0.1 V
2.5 ± 0.2 V
3.3 ± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1.8 ± 0.15 V
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
-40°C to 85°C
0.5
16
0.5
16
0.5
16
0.5
15
0.5
11
0.5
10
0.5
8
0.5
10
-40°C to 125°C
0.5
16
0.5
16
0.5
16
0.5
15
0.5
11
0.5
10
0.5
8
0.5
10
-40°C to 85°C
0.5
47
0.5
29
0.5
23
0.5
14
0.5
11
0.5
9
0.5
7
0.5
6
-40°C to 125°C
0.5
47
0.5
29
0.5
23
0.5
14
0.5
11
0.5
9
0.5
7
0.5
6
-40°C to 85°C
0.5
19
0.5
19
0.5
19
0.5
19
0.5
19
0.5
19
0.5
19
0.5
19
-40°C to 125°C
0.5
20
0.5
20
0.5
20
0.5
20
0.5
20
0.5
20
0.5
20
0.5
20
-40°C to 85°C
0.5
120
0.5
91
0.5
74
0.5
29
0.5
22
0.5
20
0.5
20
0.5
20
-40°C to 125°C
0.5
120
0.5
92
0.5
75
0.5
30
0.5
23
0.5
22
0.5
19
0.5
20
-40°C to 85°C
0.5
24
0.5
24
0.5
24
0.5
24
0.5
24
0.5
24
0.5
24
0.5
24
-40°C to 125°C
0.5
25
0.5
25
0.5
25
0.5
25
0.5
25
0.5
25
0.5
25
0.5
25
-40°C to 85°C
0.5
28
0.5
29
0.5
33
0.5
41
0.5
31
0.5
27
0.5
22
0.5
19
-40°C to 125°C
0.5
29
0.5
30
0.5
33
0.5
42
0.5
33
0.5
29
0.5
24
0.5
21
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: SN74AXC4T774
ns
ns
ns
11
SN74AXC4T774
SCES898 – JULY 2019
www.ti.com
6.11 Switching Characteristics, VCCA = 1.8 ± 0.15 V
See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.
B-Port Supply Voltage (VCCB)
PARAMETER
FROM
A
tpd
tdis
B
A
OE
A
Disable time
OE
B
A
Enable time
OE
12
B
Propagation
delay
OE
ten
TO
B
Test Conditions
0.7 ± 0.05 V
0.8 ± 0.04 V
0.9 ± 0.045 V
1.2 ± 0.1 V
1.5 ± 0.1 V
2.5 ± 0.2 V
3.3 ± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
-40°C to 85°C
0.5
12
0.5
11
0.5
11
0.5
11
0.5
9
0.5
8
0.5
7
0.5
7
-40°C to 125°C
0.5
12
0.5
12
0.5
12
0.5
12
0.5
9
0.5
9
0.5
7
0.5
7
-40°C to 85°C
0.5
56
0.5
28
0.5
21
0.5
12
0.5
10
0.5
8
0.5
6
0.5
5
-40°C to 125°C
0.5
56
0.5
28
0.5
21
0.5
12
0.5
10
0.5
9
0.5
7
0.5
6
-40°C to 85°C
0.5
17
0.5
17
0.5
17
0.5
17
0.5
17
0.5
17
0.5
17
0.5
17
-40°C to 125°C
0.5
18
0.5
18
0.5
18
0.5
18
0.5
18
0.5
18
0.5
18
0.5
18
-40°C to 85°C
0.5
117
0.5
90
0.5
73
0.5
28
0.5
21
0.5
19
0.5
16
0.5
18
-40°C to 125°C
0.5
119
0.5
90
0.5
74
0.5
29
0.5
22
0.5
20
0.5
17
0.5
18
-40°C to 85°C
0.5
19
0.5
19
0.5
19
0.5
19
0.5
19
0.5
19
0.5
19
0.5
19
-40°C to 125°C
0.5
20
0.5
20
0.5
20
0.5
20
0.5
20
0.5
20
0.5
20
0.5
20
-40°C to 85°C
0.5
21
0.5
20
0.5
20
0.5
32
0.5
27
0.5
24
0.5
20
0.5
18
-40°C to 125°C
0.5
22
0.5
22
0.5
22
0.5
34
0.5
29
0.5
26
0.5
22
0.5
19
Submit Documentation Feedback
1.8 ± 0.15 V
UNIT
ns
ns
ns
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: SN74AXC4T774
SN74AXC4T774
www.ti.com
SCES898 – JULY 2019
6.12 Switching Characteristics, VCCA = 2.5 ± 0.2 V
See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.
B-Port Supply Voltage (VCCB)
PARAMETER
FROM
A
tpd
tdis
B
Propagation
delay
B
A
OE
A
Disable time
OE
OE
ten
TO
B
A
Enable time
OE
B
Test Conditions
0.7 ± 0.05 V
0.8 ± 0.04 V
0.9 ± 0.045 V
1.2 ± 0.1 V
1.5 ± 0.1 V
2.5 ± 0.2 V
3.3 ± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1.8 ± 0.15 V
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
-40°C to 85°C
0.5
10
0.5
10
0.5
9
0.5
8
0.5
7
0.5
6
0.5
6
0.5
6
-40°C to 125°C
0.5
10
0.5
10
0.5
9
0.5
8
0.5
7
0.5
7
0.5
6
0.5
6
-40°C to 85°C
0.5
78
0.5
30
0.5
21
0.5
10
0.5
8
0.5
7
0.5
6
0.5
5
-40°C to 125°C
0.5
78
0.5
30
0.5
21
0.5
10
0.5
8
0.5
7
0.5
6
0.5
5
-40°C to 85°C
0.5
13
0.5
13
0.5
13
0.5
13
0.5
13
0.5
13
0.5
13
0.5
13
-40°C to 125°C
0.5
14
0.5
14
0.5
14
0.5
14
0.5
14
0.5
14
0.5
14
0.5
14
-40°C to 85°C
0.5
115
0.5
89
0.5
72
0.5
26
0.5
19
0.5
18
0.5
14
0.5
17
-40°C to 125°C
0.5
117
0.5
89
0.5
72
0.5
28
0.5
21
0.5
19
0.5
15
0.5
17
-40°C to 85°C
0.5
14
0.5
14
0.5
14
0.5
14
0.5
14
0.5
14
0.5
14
0.5
14
-40°C to 125°C
0.5
16
0.5
16
0.5
16
0.5
16
0.5
16
0.5
16
0.5
16
0.5
16
-40°C to 85°C
0.5
15
0.5
14
0.5
13
0.5
14
0.5
15
0.5
16
0.5
15
0.5
15
-40°C to 125°C
0.5
16
0.5
15
0.5
15
0.5
16
0.5
17
0.5
18
0.5
17
0.5
16
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: SN74AXC4T774
ns
ns
ns
13
SN74AXC4T774
SCES898 – JULY 2019
www.ti.com
6.13 Switching Characteristics, VCCA = 3.3 ± 0.3 V
See Figure 5 and Table 1 for test circuit and loading. See Figure 6, Figure 7, and Figure 8 for measurement waveforms.
B-Port Supply Voltage (VCCB)
PARAMETER
FROM
A
tpd
tdis
B
A
OE
A
Disable time
OE
B
A
Enable time
OE
14
B
Propagation
delay
OE
ten
TO
B
Test Condtions
0.7 ± 0.05 V
0.8 ± 0.04 V
0.9 ± 0.045 V
1.2 ± 0.1 V
1.5 ± 0.1 V
2.5 ± 0.2 V
3.3 ± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
-40°C to 85°C
0.5
10
0.5
9
0.5
9
0.5
8
0.5
6
0.5
6
0.5
5
0.5
5
-40°C to 125°C
0.5
10
0.5
9
0.5
9
0.5
8
0.5
6
0.5
6
0.5
5
0.5
5
-40°C to 85°C
0.5
221
0.5
40
0.5
24
0.5
12
0.5
10
0.5
7
0.5
6
0.5
5
-40°C to 125°C
0.5
221
0.5
40
0.5
24
0.5
12
0.5
10
0.5
7
0.5
6
0.5
5
-40°C to 85°C
0.5
16
0.5
16
0.5
16
0.5
16
0.5
16
0.5
16
0.5
16
0.5
16
-40°C to 125°C
0.5
16
0.5
16
0.5
16
0.5
16
0.5
16
0.5
16
0.5
16
0.5
16
-40°C to 85°C
0.5
115
0.5
89
0.5
72
0.5
26
0.5
19
0.5
17
0.5
14
0.5
16
-40°C to 125°C
0.5
117
0.5
89
0.5
72
0.5
27
0.5
20
0.5
18
0.5
14
0.5
16
-40°C to 85°C
0.5
12
0.5
12
0.5
12
0.5
12
0.5
12
0.5
12
0.5
12
0.5
12
-40°C to 125°C
0.5
13
0.5
13
0.5
13
0.5
13
0.5
13
0.5
13
0.5
13
0.5
13
-40°C to 85°C
0.5
13
0.5
12
0.5
11
0.5
11
0.5
11
0.5
12
0.5
12
0.5
12
-40°C to 125°C
0.5
14
0.5
12
0.5
12
0.5
12
0.5
12
0.5
13
0.5
13
0.5
13
Submit Documentation Feedback
1.8 ± 0.15 V
UNIT
ns
ns
ns
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: SN74AXC4T774
SN74AXC4T774
www.ti.com
SCES898 – JULY 2019
6.14 Operating Characteristics: TA = 25°C
PARAMETER
Power Dissipation Capacitance
per transceiver (A to B: outputs
enabled)
Power Dissipation Capacitance
per transceiver (A to B: outputs
disabled)
TEST CONDITIONS
CL = 0, RL = Open
f = 1 MHz
trise = tfall = 1 ns
CL = 0, RL = Open
f = 1 MHz
trise = tfall = 1 ns
CpdA
Power Dissipation Capacitance
per transceiver (B to A: outputs
enabled)
Power Dissipation Capacitance
per transceiver (B to A: outputs
disabled)
CL = 0, RL = Open
f = 1 MHz
trise = tfall = 1 ns
CL = 0, RL = Open
f = 1 MHz
trise = tfall = 1 ns
VCCA
VCCB
MIN
TYP
0.7 V
0.7 V
2.4
0.8 V
0.8 V
2.3
0.9 V
0.9 V
2.2
1.2 V
1.2 V
2.2
1.5 V
1.5 V
2.2
1.8 V
1.8 V
2.2
2.5 V
2.5 V
2.4
3.3 V
3.3 V
3.0
0.7 V
0.7 V
1.5
0.8 V
0.8 V
1.5
0.9 V
0.9 V
1.5
1.2 V
1.2 V
1.5
1.5 V
1.5 V
1.5
1.8 V
1.8 V
1.5
2.5 V
2.5 V
1.6
3.3 V
3.3 V
2.0
0.7 V
0.7 V
13.4
0.8 V
0.8 V
15.0
0.9 V
0.9 V
14.0
1.2 V
1.2 V
20.7
1.5 V
1.5 V
29.6
1.8 V
1.8 V
40.2
2.5 V
2.5 V
65.8
3.3 V
3.3 V
91.7
0.7 V
0.7 V
1.3
0.8 V
0.8 V
1.1
0.9 V
0.9 V
1.1
1.2 V
1.2 V
1.0
1.5 V
1.5 V
1.0
1.8 V
1.8 V
1.0
2.5 V
2.5 V
1.0
3.3 V
3.3 V
1.0
MAX
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UNIT
pF
pF
pF
pF
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Operating Characteristics: TA = 25°C (continued)
PARAMETER
Power Dissipation Capacitance
per transceiver (A to B: outputs
enabled)
Power Dissipation Capacitance
per transceiver (A to B: outputs
disabled)
TEST CONDITIONS
CL = 0, RL = Open
f = 1 MHz
trise = tfall = 1 ns
CL = 0, RL = Open
f = 1 MHz
trise = tfall = 1 ns
CpdB
Power Dissipation Capacitance
per transceiver (B to A: outputs
enabled)
Power Dissipation Capacitance
per transceiver (B to A: outputs
disabled)
16
CL = 0, RL = Open
f = 1 MHz
trise = tfall = 1 ns
CL = 0, RL = Open
f = 1 MHz
trise = tfall = 1 ns
VCCA
VCCB
MIN
TYP
0.7 V
0.7 V
13.4
0.8 V
0.8 V
13.8
0.9 V
0.9 V
14.9
1.2 V
1.2 V
20.6
1.5 V
1.5 V
29.6
1.8 V
1.8 V
40.3
2.5 V
2.5 V
66.2
3.3 V
3.3 V
92.5
0.7 V
0.7 V
1.3
0.8 V
0.8 V
1.2
0.9 V
0.9 V
1.1
1.2 V
1.2 V
1.1
1.5 V
1.5 V
1.1
1.8 V
1.8 V
1.1
2.5 V
2.5 V
1.1
3.3 V
3.3 V
1.1
0.7 V
0.7 V
2.5
0.8 V
0.8 V
2.4
0.9 V
0.9 V
2.3
1.2 V
1.2 V
2.2
1.5 V
1.5 V
2.3
1.8 V
1.8 V
2.3
2.5 V
2.5 V
2.5
3.3 V
3.3 V
3.0
0.7 V
0.7 V
1.6
0.8 V
0.8 V
1.5
0.9 V
0.9 V
1.5
1.2 V
1.2 V
1.5
1.5 V
1.5 V
1.5
1.8 V
1.8 V
1.5
2.5 V
2.5 V
1.6
3.3 V
3.3 V
2.0
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MAX
UNIT
pF
pF
pF
pF
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6.15 Typical Characteristics
3.4
VCC = 1.8V
VCC = 2.5V
VCC = 3.3V
3.2
3
2.6
VOH (V)
VOH (V)
2.8
2.4
2.2
2
1.8
1.6
1.4
2
4
6
8
10
12
IOH (mA)
14
16
18
VCC = 0.7V
VCC = 1.2V
0
20
0.5
1
1.5
2
D001
2.5
3
IOH (mA)
3.5
4
4.5
5
D001
Figure 1. Typical (TA=25°C) Output High Voltage (VOH) vs
Source Current (IOH)
Figure 2. Typical (TA=25°C) Output High Voltage (VOH) vs
Source Current (IOH)
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
-50
220
200
180
160
140
VOL (mV)
VOL (mV)
0
1.25
1.2
1.15
1.1
1.05
1
0.95
0.9
0.85
0.8
0.75
0.7
0.65
0.6
0.55
120
100
80
60
40
VCC = 1.8V
VCC = 2.5V
VCC = 3.3V
VCC = 0.7V
VCC = 1.2V
20
0
0
2
4
6
8
10
12
IOL (mA)
14
16
18
20
0
0.5
D001
Figure 3. Typical (TA=25°C) Output High Voltage (VOL) vs
Sink Current (IOL)
1
1.5
2
2.5
3
IOL (mA)
3.5
4
4.5
5
D001
Figure 4. Typical (TA=25°C) Output High Voltage (VOL) vs
Sink Current (IOL)
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7 Parameter Measurement Information
7.1 Load Circuit and Voltage Waveforms
Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:
• f = 1 MHz
• ZO = 50 Ω
• dv/dt ≤ 1 ns/V
Measurement Point
2 x VCCO
S1
RL
Open
Output Pin
Under Test
GND
CL(1)
(1)
RL
CL includes probe and jig capacitance.
Figure 5. Load Circuit
Table 1. Load Circuit Conditions
Parameter
VCCO
RL
CL
S1
VTP
Δt/Δv
Input transition rise or fall rate
0.65 V – 3.6 V
1 MΩ
15 pF
Open
N/A
1.1 V – 3.6 V
2 kΩ
15 pF
Open
N/A
tpd
Propagation (delay) time
0.65 V – 0.95
V
20 kΩ
15 pF
Open
N/A
ten, tdis Enable time, disable time
ten, tdis Enable time, disable time
3 V – 3.6 V
2 kΩ
15 pF
2 × VCCO
0.3 V
1.65 V – 2.7 V
2 kΩ
15 pF
2 × VCCO
0.15 V
1.1 V – 1.6 V
2 kΩ
15 pF
2 × VCCO
0.1 V
0.65 V – 0.95
V
20 kΩ
15 pF
2 × VCCO
0.1 V
3 V – 3.6 V
2 kΩ
15 pF
GND
0.3 V
1.65 V – 2.7 V
2 kΩ
15 pF
GND
0.15 V
1.1 V – 1.6 V
2 kΩ
15 pF
GND
0.1 V
0.65 V – 0.95
V
20 kΩ
15 pF
GND
0.1 V
VCCI(1)
VCCI(1)
Input A, B
Input A, B
VCCI / 2
VCCI / 2
100 kHz
500 ps/V ± 10 ns/V
0V
tpd
VOH(2)
tpd
VOH(2)
Output B, A
VCCI / 2
Output B, A
Ensure Monotonic
Rising and Falling Edge
VCCI / 2
VOL(2)
1.
2.
0V
VCCI is the supply pin associated with the input port.
VOH and VOL are typical output voltage levels that occur with
specified RL, CL, and S1
1.
2.
VOL(2)
VCCI is the supply pin associated with the input port.
VOH and VOL are typical output voltage levels that occur with
specified RL, CL, and S1
Figure 7. Input Transition Rise or Fall Rate
Figure 6. Propagation Delay
18
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VCCA
OE
VCCA / 2
VCCA / 2
GND
tdis
ten
VCCO(3)
Output(1)
VCCO / 2
VOL + VTP
VOL(4)
VOH(4)
VOH - VTP
Output(2)
VCCO / 2
GND
(1)
Output waveform on the condition that input is driven to a valid Logic Low.
(2)
Output waveform on the condition that input is driven to a valid Logic High.
(3)
VCCO is the supply pin associated with the output port.
(4)
VOH and VOL are typical output voltage levels with specified RL, CL, and S1.
Figure 8. Enable Time And Disable Time
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8 Detailed Description
8.1 Overview
The SN74AXC4T774 is a 4-bit, dual-supply noninverting bidirectional voltage level translation device. Ax pins
and control pins (DIRx and OE) are reference to VCCA logic levels, and Bx pins are referenced to VCCB logic
levels. The A port is able to accept I/O voltages ranging from 0.65 V to 3.6 V, while the B port can accept I/O
voltages from 0.65 V to 3.6 V. A high on DIR allows data transmission from A to B and a low on DIR allows data
transmission from B to A when OE is set to low. When OE is set to high, both Ax and Bx pins are in the highimpedance state. See Device Functional Modes for a summary of the operation of the control logic.
8.2 Functional Block Diagram
One of Four Transceivers
VCCA
VCCB
DIRx
OE
Bx
Ax
8.3 Feature Description
8.3.1 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating
Conditions to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a
device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.
8.3.2 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at
all times.
8.3.3 Partial Power Down (Ioff)
The inputs and outputs for this device enter a high-impedance state when the device is powered down, inhibiting
current backflow into the device. The maximum leakage into or out of any input or output pin on the device is
specified by Ioff in the Electrical Characteristics.
8.3.4 VCC Isolation
The inputs and outputs for this device enter a high-impedance state when either supply is <100mV.
20
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Feature Description (continued)
8.3.5 Over-voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Recommended Operating Conditions.
8.3.6 Glitch-free Power Supply Sequencing
Either supply rail may be powered on or off in any order without producing a glitch on the I/Os (that is, where the
output erroneously transitions to VCC when it should be held low). Glitches of this nature can be misinterpreted
by a peripheral as a valid data bit, which could trigger a false device reset of the peripheral, a false device
configuration of the peripheral, or even a false data initialization by the peripheral. For more information
regarding the power up glitch performance of the AXC family of level translators, see the Glitch Free Power
Sequencing With AXC Level Translators application report
8.3.7 Negative Clamping Diodes
The inputs and outputs to this device have negative clamping diodes as depicted in Figure 9.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
VCC
Device
Logic
Input
Output
-IIK
-IOK
GND
Figure 9. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.8 Fully Configurable Dual-Rail Design
Both the VCCA and VCCB pins can be supplied at any voltage from 0.65 V to 3.6 V, making the device suitable for
translating between any of the voltage nodes (0.7 V, 0.8 V, 0.9 V, 1.2 V, 1.8 V, 2.5 V and 3.3 V).
8.3.9 Supports High-Speed Translation
The SN74AXC4T774 device can support high data-rate applications. The translated signal data rate can be up to
310 Mbps when the signal is translated from 1.8 V to 3.3 V.
8.4 Device Functional Modes
Table 2. Function Table
(Each Transceiver) (1) (2)
CONTROL INPUTS
OE
(1)
(2)
Port Status
B PORT
OPERATION
DIR
A PORT
L
L
Output (Enabled)
Input (Hi-Z)
B data to A bus
L
H
Input (Hi-Z)
Output (Enabled)
A data to B bus
H
X
Input (Hi-Z)
Input (Hi-Z)
Isolation
Input circuits of the data I/Os are always active.
Pins configured as inputs should not be left floating.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74AXC4T774 device can be used in level-translation applications for interfacing devices or systems
operating at different interface voltages with one another. The SN74AXC4T774 device is ideal for use in
applications where a push-pull driver is connected to the data I/Os. The max data rate can be up to 310 Mbps
when device translates a signal from 1.8 V to 3.3 V.
One example application is shown in Figure 10, where the SN74AXC4T774 device is used to translate a low
voltage SPI signal from an SoC to a higher voltage signal to properly drive the inputs of a GPS module, and vice
versa.
9.2 Typical Application
Pullup Resistors keep device disabled
during power up. OE inputs may also
be tied to GND to keep device enabled
0.7 V
3.3 V
0.1 µF
0.1 µF
VCCA
VCCB
DIR1
DIR3
DIR2
DIR4
SoC
GPS
Module
GPIO1
OE
CLK
A1
B1
CLK
MOSI
A2
B2
MOSI
MISO
A3
B3
MISO
SS
A4
B4
SS
SN74AXC4T774
GND
Figure 10. Serial Peripheral Interface (SPI) Application
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 3.
Table 3. Design Parameters
22
DESIGN PARAMETERS
EXAMPLE VALUES
Input voltage range
0.65 V to 3.6 V
Output voltage range
0.65 V to 3.6 V
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9.2.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the SN74AXC4T774 device to determine the input
voltage range. For a valid logic-high, the value must exceed the high-level input voltage (VIH) of the input
port. For a valid logic low the value must be less than the low-level input voltage (VIL) of the input port.
• Output voltage range
– Use the supply voltage of the device that the SN74AXC4T774 device is driving to determine the output
voltage range.
9.2.3 Application Curve
Figure 11. Up Translation at 2.5 MHz (0.7 V to 3.3 V)
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10 Power Supply Recommendations
Always apply a ground reference to the GND pins first. This device is designed for glitch free power sequencing
without any supply sequencing requirements such as ramp order or ramp rate.
This device was designed with various power supply sequencing methods in mind to help prevent unintended
triggering of downstream devices. For more information regarding the power up glitch performance of the AXC
family of level translators, see the Glitch Free Power Sequencing With AXC Level Translators application report
11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, following common printed-circuit board layout guidelines are recommended:
• Use bypass capacitors on the power supply pins and place them as close to the device as possible. A 0.1 µF
capacitor is recommended, but transient performance can be improved by having both 1 µF and 0.1 µF
capacitors in parallel as bypass capacitors.
• The high drive capability of this device creates fast edges into light loads so routing and load conditions
should be considered to prevent ringing.
11.2 Layout Example
Legend
G
A
Via to GND
Copper Traces
B
Via to VCCA
Via to VCCB
VCCB
16
G
0.1µF
VCCA
A
DIR1
DIR2
SN74AXC4T774RSV
15
14
13
G
0.1µF
B
1
12
B1
CLK to Module
MOSI from SoC
A2
2
11
B2
MOSI to Module
MISO to SoC
A3
3
10
B3
MISO from Module
SS from SoC
A4
4
9
B4
SS to Module
G
6
7
8
GND
DIR3
5
OE
A1
DIR4
CLK from SoC
G
Figure 12. Layout Example
24
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12 Device and Documentation Support
12.1 Related Documentation
For related documentation see the following:
Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
Texas Instruments, Power Sequencing for AXC Family of Devices application report
Texas Instruments, SN74AXC4T774 Evaluation Module Tool Folder
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74AXC4T774PWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
SN4T774
SN74AXC4T774RSVR
ACTIVE
UQFN
RSV
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1UXR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jul-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74AXC4T774PWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74AXC4T774RSVR
UQFN
RSV
16
3000
178.0
13.5
2.1
2.9
0.75
4.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jul-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AXC4T774PWR
SN74AXC4T774RSVR
TSSOP
PW
16
2000
367.0
367.0
35.0
UQFN
RSV
16
3000
189.0
185.0
36.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
RSV0016A
UQFN - 0.55 mm max height
SCALE 5.000
ULTRA THIN QUAD FLATPACK - NO LEAD
1.85
1.75
B
A
PIN 1 INDEX AREA
2.65
2.55
C
0.55
0.45
SEATING PLANE
0.05 C
0.05
0.00
2X 1.2
SYMM
5
(0.13) TYP
8
15X
4
0.45
0.35
9
SYMM
2X 1.2
12X 0.4
1
12
16
0.55
0.45
16X
0.25
0.15
0.07
0.05
C A B
13
PIN 1 ID
(45 X 0.1)
4220314/B 05/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
SYMM
(0.7)
16
SEE SOLDER MASK
DETAIL
13
12
1
16X (0.2)
SYMM
12X (0.4)
(R0.05) TYP
(2.4)
9
4
15X (0.6)
8
5
(1.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK DEFINED
SOLDER MASK DETAILS
4220314/B 05/2019
NOTES: (continued)
3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
(0.7)
13
16
16X (0.2)
12
1
SYMM
12X (0.4)
(2.4)
(R0.05) TYP
4
9
15X (0.6)
5
8
SYMM
(1.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 25X
4220314/B 05/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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