Texas Instruments | SN74AXC8T245 8-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and Tri-State Outputs (Rev. B) | Datasheet | Texas Instruments SN74AXC8T245 8-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and Tri-State Outputs (Rev. B) Datasheet

Texas Instruments SN74AXC8T245 8-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and Tri-State Outputs (Rev. B) Datasheet
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SN74AXC8T245
SCES875B – MARCH 2018 – REVISED AUGUST 2018
SN74AXC8T245 8-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation
and Tri-State Outputs
1 Features
•
1
•
•
•
•
•
•
•
•
Qualified Fully Configurable Dual-Rail Design
Allows Each Port to Operate With a Power Supply
Range From 0.65 V to 3.6 V
Operating Temperature From –40°C to +125°C
Multiple Direction Control Pins to Allow
Simultaneous Up and Down Translation
Up to 380 Mbps Support When Translating from
1.8 V to 3.3 V
VCC Isolation Feature to Effectively Isolate Both
Buses in a Power-Down Scenario
Partial Power-Down Mode to Limit Backflow
Current in a Power-Down Scenario
Compatible With SN74AVC8T245 and
74AVC8T245 Level Shifters
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 8000-V Human-Body Model
– 1000-V Charged-Device Model
The SN74AXC8T245 device is designed for
asynchronous communication between data buses.
The device transmits data from the A bus to the B
bus or from the B bus to the A bus, depending on the
logic level of the direction-control inputs (DIR1 and
DIR2). The output-enable (OE) input is used to
disable the outputs so the buses are effectively
isolated.
The SN74AXC8T245 device is designed so the
control pins (DIR and OE) are referenced to VCCA.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs when the device is powered down. This
inhibits current backflow into the device which
prevents damage to the device.
The VCC isolation feature ensures that if either VCC
input supply is below 100 mV, all level shifter outputs
are disabled and placed into a high-impedance state.
To ensure the high-impedance state of the level
shifter I/Os during power up or power down, OE
should be tied to VCCA through a pullup resistor; the
minimum value of the resistor is determined by the
current-sinking capability of the driver.
2 Applications
•
•
•
•
•
•
Enterprise and Communications
Industrial
Personal Electronics
Wireless Infrastructure
Building Automation
Point of Sale
Device Information(1)
PART NUMBER
The device operates by using two independent
power-supply rails (VCCA and VCCB) that operate as
low as 0.65 V. Data pins A1 through A8 are designed
to track VCCA, which accepts any supply voltage from
0.65 V to 3.6 V. Data pins B1 through B8 are
designed to track VCCB, which accepts any supply
voltage from 0.65 V to 3.6 V.
BODY SIZE (NOM)
SN74AXC8T245PW
TSSOP (24)
4.40 mm × 7.80 mm
SN74AXC8T245RHL
VQFN (24)
3.50 mm × 5.50 mm
SN74AXC8T245RJW
UQFN (24)
2.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
3 Description
The SN74AXC8T245 device is an 8-bit non-inverting
bus transceiver that resolves voltage level mismatch
between devices operating at the latest voltage
nodes (0.7 V, 0.8 V, and 0.9 V) and devices
operating at industry standard voltage nodes (1.8 V,
2.5 V, 3.3 V) and vice versa.
PACKAGE
3.3 V
1.5 V
Processor
Control Block
VCCA DIR1 DIR2
VCCB
A1
B1
A2
B2
B3
A3
Data Block
A4
SN74AXC8T245
B4
A5
B5
A6
B6
A8
Register Map
B7
A7
Interrupts
Power Management
GND
B8
Sensor Block
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AXC8T245
SCES875B – MARCH 2018 – REVISED AUGUST 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
7
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Switching Characteristics, VCCA = 0.7 V ................... 8
Switching Characteristics, VCCA = 0.8 V ................... 9
Switching Characteristics, VCCA = 0.9 V ................. 10
Switching Characteristics, VCCA = 1.2 V ................. 11
Switching Characteristics, VCCA = 1.5 V ............... 12
Switching Characteristics, VCCA = 1.8 V ............... 13
Switching Characteristics, VCCA = 2.5 V ............... 14
Switching Characteristics, VCCA = 3.3 V ............... 15
Operating Characteristics: TA = 25°C ................... 16
Parameter Measurement Information ................ 18
8
Detailed Description ............................................ 20
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
20
20
21
21
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Application ................................................. 22
10 Power Supply Recommendations ..................... 24
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 24
12 Device and Documentation Support ................. 25
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
Changes from Revision A (July 2018) to Revision B
Page
•
Changed data sheet status from Mixed Production to Production Data ............................................................................... 1
•
Removed package preview note from RJW package ........................................................................................................... 1
Changes from Original (March 2018) to Revision A
•
2
Page
Added RJW as a new package option (preview).................................................................................................................... 1
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SCES875B – MARCH 2018 – REVISED AUGUST 2018
5 Pin Configuration and Functions
PW Package
24-Pin TSSOP
Top View
VCCB
OE
21 B1
20 B2
19 B3
18 B4
17 B5
16 B6
15 B7
14 B8
VCCB
24
2
23
3
22
4
5
6
PAD
7
8
9
10
11
13
DIR1
A1
A2
A3
A4
A5
A6
A7
A8
DIR2
GND
VCCB
VCCB
OE
B1
B2
B3
B4
B5
B6
B7
B8
GND
VCCA
24
23
22
21
20
19
18
17
16
15
14
13
1
1
2
3
4
5
6
7
8
9
10
11
12
GND 12
VCCA
DIR1
A1
A2
A3
A4
A5
A6
A7
A8
DIR2
GND
RHL Package
24-Pin VQFN
Top View
1
A1
VCCB
DIR1
VCCA
RJW Package
24-Pin UQFN
Top View
24
23
2
21
OE
A2
3
20
B1
A3
4
19
B2
A4
5
18
B3
A5
6
17
B4
A6
7
16
B5
A7
8
15
B6
A8
9
14
B7
13
B8
DIR2
10
11
12
GND
VCCB
GND
22
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Pin Functions
PIN
NAME
I/O
DESCRIPTION
PW, RHL
RJW
A1
3
2
I/O
Input/output A1. Referenced to VCCA.
A2
4
3
I/O
Input/output A2. Referenced to VCCA.
A3
5
4
I/O
Input/output A3. Referenced to VCCA.
A4
6
5
I/O
Input/output A4. Referenced to VCCA.
A5
7
6
I/O
Input/output A5. Referenced to VCCA.
A6
8
7
I/O
Input/output A6. Referenced to VCCA.
A7
9
8
I/O
Input/output A7. Referenced to VCCA.
A8
10
9
I/O
Input/output A8. Referenced to VCCA.
B1
21
20
I/O
Input/output B1. Referenced to VCCB.
B2
20
19
I/O
Input/output B2. Referenced to VCCB.
B3
19
18
I/O
Input/output B3. Referenced to VCCB.
B4
18
17
I/O
Input/output B4. Referenced to VCCB.
B5
17
16
I/O
Input/output B5. Referenced to VCCB.
B6
16
15
I/O
Input/output B6. Referenced to VCCB.
B7
15
14
I/O
Input/output B7. Referenced to VCCB.
B8
14
13
I/O
Input/output B8. Referenced to VCCB.
DIR1
2
1
I
Direction-control signal. Referenced to VCCA.
DIR2
11
10
I
Direction-control signal when both VCCA and VCCB ≥ 1.4 V.
Referenced to VCCA. Tie to GND to maintain backward compatibility with
SN74AVC8T245 device.
12
11
—
Ground
13
12
—
Ground
22
21
I
GND
OE
VCCA
VCCB
4
Output Enable. Pull to GND to enable all outputs. Pull to VCCA to place all
outputs in high-impedance mode. Referenced to VCCA.
1
24
—
A-port supply voltage. 0.65 V ≤ VCCA ≤ 3.6 V
23
22
—
B-port supply voltage. 0.65 V ≤ VCCB ≤ 3.6 V
24
23
—
B-port supply voltage. 0.65 V ≤ VCCB ≤ 3.6 V
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage, VCCA
Supply voltage, VCCB
MIN
MAX
UNIT
–0.5
4.2
V
V
–0.5
4.2
I/O ports (A port)
–0.5
4.2
I/O ports (B port)
–0.5
4.2
Control inputs
–0.5
4.2
A port
–0.5
4.2
B port
–0.5
4.2
A port
–0.5
VCCA + 0.2
B port
–0.5
VCCB + 0.2
Input clamp current, IIK
VI < 0
–50
mA
Output clamp current, IOK
VO < 0
–50
mA
Input voltage, VI (2)
Voltage applied to any output
in the high-impedance or power-off state, VO (2)
Voltage applied to any output in the high or low state, VO (2)
(3)
V
V
V
Continuous output current, IO
–50
50
mA
Continuous current through VCCA, VCCB, or GND
–100
100
mA
150
°C
150
°C
Junction Temperature, TJ
Storage temperature, Tstg
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The output positive-voltage rating may be exceeded up to 4.2 V maximum if the output current rating is observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±8000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
(1) (2) (3)
MIN
MAX
UNIT
VCCA
Supply voltage
0.65
3.6
V
VCCB
Supply voltage
0.65
3.6
V
Data inputs
VIH
VCCI = 0.65 V - 0.75 V
VCCI × 0.70
VCCI = 0.76 V - 1 V
VCCI × 0.70
VCCI = 1.1 V - 1.95 V
VCCI × 0.65
VCCI = 2.3 V - 2.7 V
1.6
VCCI = 3 V - 3.6 V
High-level input voltage
Control inputs
(DIR, OE)
Referenced to VCCA
2
VCCA = 0.65 V - 0.75 V
VCCA × 0.70
VCCA = 0.76 V - 1 V
VCCA × 0.70
VCCA = 1.1 V - 1.95 V
VCCA × 0.65
VCCA = 2.3 V - 2.7 V
1.6
VCCA = 3 V - 3.6 V
Data inputs
VIL
Low-level input voltage
Control inputs
(DIR, OE)
Referenced to VCCA
V
2
VCCI = 0.65 V - 0.75 V
VCCI × 0.30
VCCI = 0.76 V - 1 V
VCCI × 0.30
VCCI = 1.1 V - 1.95 V
VCCI × 0.35
VCCI = 2.3 V - 2.7 V
0.7
VCCI = 3 V - 3.6 V
0.8
VCCA = 0.65 V - 0.75 V
VCCA × 0.30
VCCA = 0.76 V - 1 V
VCCA × 0.30
VCCA = 1.1 V - 1.95 V
VCCA × 0.35
VCCA = 2.3 V - 2.7 V
0.7
VCCA = 3 V - 3.6 V
VO
Output voltage
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
(2)
(3)
0.8
Input voltage (3)
VI
V
0
3.6
Active state
0
VCCO
V
Tri-state
0
3.6
10
ns/V
–40
125
°C
(2)
V
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. See the Implications of Slow or
Floating CMOS Inputs application report.
6.4 Thermal Information
SN74AXC8T245
THERMAL METRIC
PW (TSSOP)
RHL (VQFN)
RJW (UQFN)
24 PINS
24 PINS
24 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
92.0
35.0
123.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
29.3
39.9
65.0
°C/W
RθJB
Junction-to-board thermal resistance
46.7
13.8
55.3
°C/W
ψJT
Junction-to-top characterization parameter
1.5
0.3
3.9
°C/W
ψJB
Junction-to-board characterization parameter
46.2
13.8
54.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
1.4
N/A
°C/W
6
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6.5 Electrical Characteristics
Over recommended operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
VOH
VOL
High-level
output
voltage
Low-level
output
voltage
II
Input leakage
current
Ioff
Partial power
down current
IOZ
ICCA
ICCB
Highimpedance
state output
current
VCCA supply
current
VCCB supply
current
TEST CONDITIONS
–40°C to 85°C
–40°C to 125°C
VCCA
VCCB
IOH = –100 µA
0.7 V - 3.6 V
0.7 V - 3.6 V
VCCO – 0.1
VCCO – 0.1
IOH = –50 µA
0.65 V
0.65 V
0.55
0.55
IOH = –200 µA
0.76 V
0.76 V
0.58
0.58
IOH = –500 µA
0.85 V
0.85 V
0.65
0.65
IOH = -3 mA
1.1 V
1.1 V
0.85
0.85
IOH = -6 mA
1.4 V
1.4 V
1.05
1.05
IOH = -8 mA
1.65 V
1.65 V
1.2
1.2
IOH = -9 mA
2.3 V
2.3 V
1.75
1.75
IOH = -12 mA
3V
3V
2.3
2.3
IOL = 100 µA
0.7 V - 3.6 V
0.7 V - 3.6 V
0.1
IOL = 50 µA
0.65 V
0.65 V
0.1
0.1
IOL = 200 µA
0.76 V
0.76 V
0.18
0.18
IOL = 500 µA
0.85 V
0.85 V
0.2
0.2
IOL = 3 mA
1.1 V
1.1 V
0.25
0.25
IOL = 6 mA
1.4 V
1.4 V
0.35
0.35
IOL = 8 mA
1.65 V
1.65 V
0.45
0.45
IOL = 9 mA
2.3 V
2.3 V
0.55
0.55
IOL = 12 mA
3V
3V
0.7
0.7
0.65 V - 3.6 V
0.65 V - 3.6 V
A Port:
VI or VO = 0 V - 3.6 V
0V
B Port:
VI or VO = 0 V - 3.6 V
VI = VIH
VI = VIL
Control Inputs (DIR, OE):
VI = VCCA or GND
MIN
TYP (2)
MAX
MIN
TYP (2)
MAX
UNIT
V
0.1
-0.5
0.5
-1
1
0 V - 3.6 V
-4
4
-8
8
0 V - 3.6 V
0V
-4
4
-8
8
A Port:
VO = VCCO or GND, VI = VCCI
or GND, OE = VIH
3.6 V
3.6 V
-4
4
-8
8
B Port:
VO = VCCO or GND, VI = VCCI
or GND, OE = VIH
3.6 V
3.6 V
-4
4
-8
8
0.65 V - 3.6 V
0.65 V - 3.6 V
0V
3.6 V
3.6 V
0V
12
25
0.65 V - 3.6 V
0.65 V - 3.6 V
18
38
0V
3.6 V
12
3.6 V
0V
0.65 V - 3.6 V
0.65 V - 3.6 V
V
µA
µA
µA
VI = VCCI or GND, IO = 0 mA
VI = VCCI or GND, IO = 0 mA
19
-2
40
-12
-2
µA
25
µA
55
µA
-12
ICCA
+
ICCB
Combined
supply
current
VI = VCCI or GND, IO = 0 mA
Ci
Input
capacitance
Control Inputs (DIR, OE):
VI = 3.3 V or GND
3.3 V
3.3 V
4.5
4.5
pF
Cio
Data I/O
capacitance
Ports A and B:
OE = VCCA, VO = 1.65V DC +
1 MHz -16 dBm sine wave
3.3 V
3.3 V
5.7
5.7
pF
(1)
(2)
25
VCCO is the VCC associated with the output port.
All typical values are for TA = 25°C
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6.6 Switching Characteristics, VCCA = 0.7 V
See Figure 1 and Figure 2 for test circuit and loading conditions. See Figure 3 and Figure 4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB)
PARAMETER
Propagation
delay
tpd
tdis
ten
TEST CONDITIONS
0.7 V ± 0.05 V
0.8 V ± 0.04 V
0.9 V ± 0.045 V
1.2 V ± 0.1 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
From input A
to output B
–40°C to 85°C
0.5
172
0.5
114
0.5
82
0.5
49
–40°C to 125°C
0.5
172
0.5
114
0.5
82
0.5
49
From input B
to output A
–40°C to 85°C
0.5
172
0.5
153
0.5
126
0.5
88
–40°C to 125°C
0.5
172
0.5
153
0.5
126
0.5
88
From inputOE
to output A
–40°C to 85°C
0.5
192
0.5
192
0.5
192
0.5
192
–40°C to 125°C
0.5
195
0.5
195
0.5
195
0.5
195
From inputOE
to output B
–40°C to 85°C
0.5
156
0.5
129
0.5
118
0.5
120
–40°C to 125°C
0.5
157
0.5
129
0.5
120
0.5
122
From input OE
to output A
–40°C to 85°C
0.5
237
0.5
237
0.5
237
0.5
237
–40°C to 125°C
0.5
237
0.5
237
0.5
237
0.5
237
From input OE
to output B
–40°C to 85°C
0.5
223
0.5
145
0.5
106
0.5
74
–40°C to 125°C
0.5
223
0.5
145
0.5
106
0.5
74
Disable time
Enable time
UNIT
ns
ns
ns
B-PORT SUPPLY VOLTAGE (VCCB)
PARAMETER
tpd
tdis
ten
8
Propagation
delay
TEST CONDITIONS
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
From input A
to output B
–40°C to 85°C
0.5
46
0.5
49
0.5
61
0.5
142
–40°C to 125°C
0.5
46
0.5
49
0.5
61
0.5
142
From input B
to output A
–40°C to 85°C
0.5
83
0.5
82
0.5
81
0.5
81
–40°C to 125°C
0.5
83
0.5
82
0.5
81
0.5
81
From inputOE
to output A
–40°C to 85°C
0.5
192
0.5
192
0.5
192
0.5
192
–40°C to 125°C
0.5
195
0.5
195
0.5
195
0.5
195
From inputOE
to output B
–40°C to 85°C
0.5
69
0.5
66
0.5
67
0.5
150
–40°C to 125°C
0.5
70
0.5
67
0.5
67
0.5
150
From input OE
to output A
–40°C to 85°C
0.5
237
0.5
237
0.5
237
0.5
237
–40°C to 125°C
0.5
237
0.5
237
0.5
237
0.5
237
From input OE
to output B
–40°C to 85°C
0.5
68
0.5
69
0.5
84
0.5
552
–40°C to 125°C
0.5
68
0.5
69
0.5
84
0.5
552
Disable time
Enable time
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UNIT
ns
ns
ns
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN74AXC8T245
SN74AXC8T245
www.ti.com
SCES875B – MARCH 2018 – REVISED AUGUST 2018
6.7 Switching Characteristics, VCCA = 0.8 V
See Figure 1 and Figure 2 for test circuit and loading conditions. See Figure 3 and Figure 4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB)
PARAMETER
Propagation
delay
tpd
tdis
ten
TEST CONDITIONS
0.7 V ± 0.05 V
0.8 V ± 0.04 V
0.9 V ± 0.045 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
1.2 V ± 0.1 V
MAX
From input A
to output B
–40°C to 85°C
0.5
153
0.5
95
0.5
62
0.5
32
–40°C to 125°C
0.5
153
0.5
95
0.5
62
0.5
32
From input B
to output A
–40°C to 85°C
0.5
114
0.5
95
0.5
78
0.5
52
–40°C to 125°C
0.5
114
0.5
95
0.5
78
0.5
52
From inputOE
to output A
–40°C to 85°C
0.5
101
0.5
101
0.5
101
0.5
101
–40°C to 125°C
0.5
103
0.5
103
0.5
103
0.5
103
From inputOE
to output B
–40°C to 85°C
0.5
141
0.5
114
0.5
104
0.5
106
–40°C to 125°C
0.5
142
0.5
115
0.5
106
0.5
109
From input OE
to output A
–40°C to 85°C
0.5
102
0.5
102
0.5
102
0.5
102
–40°C to 125°C
0.5
102
0.5
102
0.5
102
0.5
102
From input OE
to output B
–40°C to 85°C
0.5
202
0.5
124
0.5
86
0.5
52
–40°C to 125°C
0.5
202
0.5
124
0.5
86
0.5
52
Disable time
Enable time
UNIT
ns
ns
ns
B-PORT SUPPLY VOLTAGE (VCCB)
PARAMETER
tpd
tdis
ten
Propagation
delay
TEST CONDITIONS
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
From input A
to output B
–40°C to 85°C
0.5
26
0.5
25
0.5
25
0.5
35
–40°C to 125°C
0.5
26
0.5
25
0.5
25
0.5
35
From input B
to output A
–40°C to 85°C
0.5
42
0.5
41
0.5
40
0.5
40
–40°C to 125°C
0.5
42
0.5
41
0.5
40
0.5
40
From inputOE
to output A
–40°C to 85°C
0.5
101
0.5
101
0.5
101
0.5
101
–40°C to 125°C
0.5
103
0.5
103
0.5
103
0.5
103
From inputOE
to output B
–40°C to 85°C
0.5
55
0.5
51
0.5
49
0.5
51
–40°C to 125°C
0.5
57
0.5
53
0.5
50
0.5
52
From input OE
to output A
–40°C to 85°C
0.5
102
0.5
102
0.5
102
0.5
102
–40°C to 125°C
0.5
102
0.5
102
0.5
102
0.5
102
From input OE
to output B
–40°C to 85°C
0.5
44
0.5
43
0.5
45
0.5
58
–40°C to 125°C
0.5
44
0.5
43
0.5
45
0.5
58
Disable time
Enable time
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Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN74AXC8T245
UNIT
ns
ns
ns
9
SN74AXC8T245
SCES875B – MARCH 2018 – REVISED AUGUST 2018
www.ti.com
6.8 Switching Characteristics, VCCA = 0.9 V
See Figure 1 and Figure 2 for test circuit and loading conditions. See Figure 3 and Figure 4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB)
PARAMETER
Propagation
delay
tpd
tdis
ten
TEST CONDITIONS
0.7 V ± 0.05 V
0.8 V ± 0.04 V
0.9 V ± 0.045 V
1.2 V ± 0.1 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
From input A
to output B
–40°C to 85°C
0.5
127
0.5
78
0.5
52
0.5
23
–40°C to 125°C
0.5
127
0.5
78
0.5
52
0.5
23
From input B
to output A
–40°C to 85°C
0.5
82
0.5
63
0.5
52
0.5
39
–40°C to 125°C
0.5
82
0.5
63
0.5
52
0.5
39
From inputOE
to output A
–40°C to 85°C
0.5
125
0.5
125
0.5
125
0.5
125
–40°C to 125°C
0.5
128
0.5
128
0.5
128
0.5
128
From inputOE
to output B
–40°C to 85°C
0.5
131
0.5
105
0.5
96
0.5
99
–40°C to 125°C
0.5
133
0.5
107
0.5
98
0.5
101
From input OE
to output A
–40°C to 85°C
0.5
124
0.5
124
0.5
124
0.5
124
–40°C to 125°C
0.5
128
0.5
128
0.5
128
0.5
128
From input OE
to output B
–40°C to 85°C
0.5
191
0.5
113
0.5
75
0.5
41
–40°C to 125°C
0.5
191
0.5
113
0.5
75
0.5
41
Disable time
Enable time
UNIT
ns
ns
ns
B-PORT SUPPLY VOLTAGE (VCCB)
PARAMETER
tpd
tdis
ten
10
Propagation
delay
TEST CONDITIONS
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
From input A
to output B
–40°C to 85°C
0.5
17
0.5
15
0.5
14
0.5
17
–40°C to 125°C
0.5
17
0.5
15
0.5
14
0.5
17
From input B
to output A
–40°C to 85°C
0.5
28
0.5
24
0.5
22
0.5
22
–40°C to 125°C
0.5
28
0.5
24
0.5
22
0.5
22
From inputOE
to output A
–40°C to 85°C
0.5
125
0.5
125
0.5
125
0.5
125
–40°C to 125°C
0.5
128
0.5
128
0.5
128
0.5
128
From inputOE
to output B
–40°C to 85°C
0.5
47
0.5
44
0.5
40
0.5
73
–40°C to 125°C
0.5
50
0.5
46
0.5
42
0.5
73
From input OE
to output A
–40°C to 85°C
0.5
124
0.5
124
0.5
124
0.5
124
–40°C to 125°C
0.5
128
0.5
128
0.5
128
0.5
128
From input OE
to output B
–40°C to 85°C
0.5
34
0.5
32
0.5
31
0.5
35
–40°C to 125°C
0.5
34
0.5
32
0.5
31
0.5
35
Disable time
Enable time
Submit Documentation Feedback
UNIT
ns
ns
ns
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN74AXC8T245
SN74AXC8T245
www.ti.com
SCES875B – MARCH 2018 – REVISED AUGUST 2018
6.9 Switching Characteristics, VCCA = 1.2 V
See Figure 1 and Figure 2 for test circuit and loading conditions. See Figure 3 and Figure 4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB)
PARAMETER
tpd
tdis
ten
Propagation
delay
Disable
time
Enable time
TEST CONDITIONS
0.7 V ± 0.05 V
0.8 V ± 0.04 V
MIN
MAX
MIN
MAX
0.9 V ± 0.045 V
MIN
MAX
MIN
1.2 V ± 0.1 V
MAX
From input A
to output B
–40°C to 85°C
0.5
88
0.5
52
0.5
39
0.5
15
–40°C to 125°C
0.5
88
0.5
52
0.5
39
0.5
15
From input B
to output A
–40°C to 85°C
0.5
49
0.5
32
0.5
23
0.5
15
–40°C to 125°C
0.5
49
0.5
32
0.5
23
0.5
15
From
inputOE
to output A
–40°C to 85°C
0.5
87
0.5
87
0.5
87
0.5
87
–40°C to 125°C
0.5
91
0.5
91
0.5
91
0.5
91
From
inputOE
to output B
–40°C to 85°C
0.5
119
0.5
94
0.5
85
0.5
89
–40°C to 125°C
0.5
121
0.5
96
0.5
88
0.5
93
From input
OE
to output A
–40°C to 85°C
0.5
34
0.5
34
0.5
34
0.5
34
–40°C to 125°C
0.5
36
0.5
36
0.5
36
0.5
36
From input
OE
to output B
–40°C to 85°C
0.5
168
0.5
98
0.5
61
0.5
29
–40°C to 125°C
0.5
168
0.5
98
0.5
61
0.5
30
UNIT
ns
ns
ns
B-PORT SUPPLY VOLTAGE (VCCB)
PARAMETER
tpd
tdis
ten
Propagation
delay
TEST CONDITIONS
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
From input A
to output B
–40°C to 85°C
0.5
10
0.5
9
0.5
7
0.5
7
–40°C to 125°C
0.5
10
0.5
9
0.5
7
0.5
8
From input B
to output A
–40°C to 85°C
0.5
13
0.5
11
0.5
8
0.5
7
–40°C to 125°C
0.5
13
0.5
11
0.5
8
0.5
7
From inputOE
to output A
–40°C to 85°C
0.5
87
0.5
87
0.5
87
0.5
87
–40°C to 125°C
0.5
91
0.5
91
0.5
91
0.5
91
From inputOE
to output B
–40°C to 85°C
0.5
38
0.5
35
0.5
31
0.5
29
–40°C to 125°C
0.5
41
0.5
38
0.5
33
0.5
31
From input OE
to output A
–40°C to 85°C
0.5
34
0.5
34
0.5
34
0.5
34
–40°C to 125°C
0.5
36
0.5
36
0.5
36
0.5
36
From input OE
to output B
–40°C to 85°C
0.5
22
0.5
19
0.5
17
0.5
17
–40°C to 125°C
0.5
23
0.5
20
0.5
18
0.5
18
Disable time
Enable time
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN74AXC8T245
UNIT
ns
ns
ns
11
SN74AXC8T245
SCES875B – MARCH 2018 – REVISED AUGUST 2018
www.ti.com
6.10 Switching Characteristics, VCCA = 1.5 V
See Figure 1 and Figure 2 for test circuit and loading conditions. See Figure 3 and Figure 4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB)
PARAMETER
tpd
tdis
ten
Propagation
delay
TEST CONDITIONS
0.7 V ± 0.05 V
0.8 V ± 0.04 V
0.9 V ± 0.045 V
1.2 V ± 0.1 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
From input A
to output B
–40°C to 85°C
0.5
84
0.5
42
0.5
28
0.5
13
–40°C to 125°C
0.5
84
0.5
42
0.5
28
0.5
13
From input B
to output A
–40°C to 85°C
0.5
46
0.5
26
0.5
17
0.5
10
–40°C to 125°C
0.5
46
0.5
26
0.5
17
0.5
10
From inputOE
to output A
–40°C to 85°C
0.5
34
0.5
34
0.5
34
0.5
34
–40°C to 125°C
0.5
37
0.5
37
0.5
37
0.5
37
From inputOE
to output B
–40°C to 85°C
0.5
115
0.5
89
0.5
80
0.5
85
–40°C to 125°C
0.5
117
0.5
91
0.5
83
0.5
89
From input OE
to output A
–40°C to 85°C
0.5
21
0.5
21
0.5
21
0.5
21
–40°C to 125°C
0.5
23
0.5
23
0.5
23
0.5
23
From input OE
to output B
–40°C to 85°C
0.5
159
0.5
90
0.5
55
0.5
24
–40°C to 125°C
0.5
159
0.5
90
0.5
55
0.5
25
Disable time
Enable time
UNIT
ns
ns
ns
B-PORT SUPPLY VOLTAGE (VCCB)
PARAMETER
tpd
tdis
ten
12
Propagation
delay
TEST CONDITIONS
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
From input A
to output B
–40°C to 85°C
0.5
9
0.5
7
0.5
6
0.5
5
–40°C to 125°C
0.5
9
0.5
7
0.5
6
0.5
6
From input B
to output A
–40°C to 85°C
0.5
9
0.5
7
0.5
6
0.5
5
–40°C to 125°C
0.5
9
0.5
8
0.5
6
0.5
5
From inputOE
to output A
–40°C to 85°C
0.5
34
0.5
34
0.5
34
0.5
34
–40°C to 125°C
0.5
37
0.5
37
0.5
37
0.5
37
From inputOE
to output B
–40°C to 85°C
0.5
35
0.5
31
0.5
28
0.5
25
–40°C to 125°C
0.5
38
0.5
34
0.5
31
0.5
27
From input OE
to output A
–40°C to 85°C
0.5
21
0.5
21
0.5
21
0.5
21
–40°C to 125°C
0.5
23
0.5
23
0.5
23
0.5
23
From input OE
to output B
–40°C to 85°C
0.5
17
0.5
15
0.5
12
0.5
11
–40°C to 125°C
0.5
18
0.5
15
0.5
13
0.5
12
Disable time
Enable time
Submit Documentation Feedback
UNIT
ns
ns
ns
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN74AXC8T245
SN74AXC8T245
www.ti.com
SCES875B – MARCH 2018 – REVISED AUGUST 2018
6.11 Switching Characteristics, VCCA = 1.8 V
See Figure 1 and Figure 2 for test circuit and loading conditions. See Figure 3 and Figure 4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB)
PARAMETER
tpd
tdis
ten
Propagation
delay
TEST CONDITIONS
0.7 V ± 0.05 V
0.8 V ± 0.04 V
0.9 V ± 0.045 V
1.2 V ± 0.1 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
From input A
to output B
–40°C to 85°C
0.5
82
0.5
41
0.5
24
0.5
11
–40°C to 125°C
0.5
82
0.5
41
0.5
24
0.5
11
From input B
to output A
–40°C to 85°C
0.5
49
0.5
25
0.5
15
0.5
9
–40°C to 125°C
0.5
49
0.5
25
0.5
15
0.5
9
From inputOE
to output A
–40°C to 85°C
0.5
37
0.5
37
0.5
37
0.5
37
–40°C to 125°C
0.5
40
0.5
40
0.5
40
0.5
40
From inputOE
to output B
–40°C to 85°C
0.5
113
0.5
87
0.5
78
0.5
83
–40°C to 125°C
0.5
115
0.5
89
0.5
81
0.5
87
From input OE
to output A
–40°C to 85°C
0.5
17
0.5
17
0.5
17
0.5
17
–40°C to 125°C
0.5
19
0.5
19
0.5
19
0.5
19
From input OE
to output B
–40°C to 85°C
0.5
157
0.5
88
0.5
54
0.5
23
–40°C to 125°C
0.5
157
0.5
88
0.5
54
0.5
23
Disable time
Enable time
UNIT
ns
ns
ns
B-PORT SUPPLY VOLTAGE (VCCB)
PARAMETER
tpd
tdis
ten
Propagation
delay
TEST CONDITIONS
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
From input A
to output B
–40°C to 85°C
0.5
8
0.5
6
0.5
5
0.5
5
–40°C to 125°C
0.5
8
0.5
7
0.5
6
0.5
5
From input B
to output A
–40°C to 85°C
0.5
7
0.5
6
0.5
5
0.5
4
–40°C to 125°C
0.5
7
0.5
7
0.5
5
0.5
4
From inputOE
to output A
–40°C to 85°C
0.5
37
0.5
37
0.5
37
0.5
37
–40°C to 125°C
0.5
40
0.5
40
0.5
40
0.5
40
From inputOE
to output B
–40°C to 85°C
0.5
33
0.5
30
0.5
27
0.5
57
–40°C to 125°C
0.5
36
0.5
33
0.5
29
0.5
60
From input OE
to output A
–40°C to 85°C
0.5
17
0.5
17
0.5
17
0.5
17
–40°C to 125°C
0.5
19
0.5
19
0.5
19
0.5
19
From input OE
to output B
–40°C to 85°C
0.5
15
0.5
13
0.5
10
0.5
9
–40°C to 125°C
0.5
16
0.5
14
0.5
11
0.5
10
Disable time
Enable time
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN74AXC8T245
UNIT
ns
ns
ns
13
SN74AXC8T245
SCES875B – MARCH 2018 – REVISED AUGUST 2018
www.ti.com
6.12 Switching Characteristics, VCCA = 2.5 V
See Figure 1 and Figure 2 for test circuit and loading conditions. See Figure 3 and Figure 4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB)
PARAMETER
tpd
tdis
ten
Propagation
delay
TEST CONDITIONS
0.7 V ± 0.05 V
0.8 V ± 0.04 V
0.9 V ± 0.045 V
1.2 V ± 0.1 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
From input A
to output B
–40°C to 85°C
0.5
81
0.5
40
0.5
22
0.5
8
–40°C to 125°C
0.5
81
0.5
40
0.5
22
0.5
8
From input B
to output A
–40°C to 85°C
0.5
61
0.5
25
0.5
14
0.5
7
–40°C to 125°C
0.5
61
0.5
25
0.5
14
0.5
7
From inputOE
to output A
–40°C to 85°C
0.5
25
0.5
25
0.5
25
0.5
25
–40°C to 125°C
0.5
28
0.5
28
0.5
28
0.5
28
From inputOE
to output B
–40°C to 85°C
0.5
111
0.5
85
0.5
76
0.5
81
–40°C to 125°C
0.5
113
0.5
87
0.5
78
0.5
84
From input OE
to output A
–40°C to 85°C
0.5
11
0.5
11
0.5
11
0.5
11
–40°C to 125°C
0.5
12
0.5
12
0.5
12
0.5
12
From input OE
to output B
–40°C to 85°C
0.5
155
0.5
86
0.5
52
0.5
21
–40°C to 125°C
0.5
155
0.5
86
0.5
52
0.5
21
Disable time
Enable time
UNIT
ns
ns
ns
B-PORT SUPPLY VOLTAGE (VCCB)
PARAMETER
tpd
tdis
ten
14
Propagation
delay
TEST CONDITIONS
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
From input A
to output B
–40°C to 85°C
0.5
6
0.5
5
0.5
4
0.5
4
–40°C to 125°C
0.5
6
0.5
5
0.5
5
0.5
4
From input B
to output A
–40°C to 85°C
0.5
6
0.5
5
0.5
4
0.5
4
–40°C to 125°C
0.5
6
0.5
5
0.5
5
0.5
4
From inputOE
to output A
–40°C to 85°C
0.5
25
0.5
25
0.5
25
0.5
25
–40°C to 125°C
0.5
28
0.5
28
0.5
28
0.5
28
From inputOE
to output B
–40°C to 85°C
0.5
31
0.5
28
0.5
25
0.5
23
–40°C to 125°C
0.5
34
0.5
31
0.5
28
0.5
25
From input OE
to output A
–40°C to 85°C
0.5
11
0.5
11
0.5
11
0.5
11
–40°C to 125°C
0.5
12
0.5
12
0.5
12
0.5
12
From input OE
to output B
–40°C to 85°C
0.5
14
0.5
11
0.5
9
0.5
7
–40°C to 125°C
0.5
14
0.5
12
0.5
9
0.5
8
Disable time
Enable time
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UNIT
ns
ns
ns
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6.13 Switching Characteristics, VCCA = 3.3 V
See Figure 1 and Figure 2 for test circuit and loading conditions. See Figure 3 and Figure 4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB)
PARAMETER
tpd
tdis
ten
Propagation
delay
TEST CONDITIONS
0.7 V ± 0.05 V
0.8 V ± 0.04 V
0.9 V ± 0.045 V
1.2 V ± 0.1 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
From input A
to output B
–40°C to 85°C
0.5
81
0.5
40
0.5
22
0.5
7
–40°C to 125°C
0.5
81
0.5
40
0.5
22
0.5
7
From input B
to output A
–40°C to 85°C
0.5
142
0.5
35
0.5
17
0.5
7
–40°C to 125°C
0.5
142
0.5
35
0.5
17
0.5
8
From inputOE
to output A
–40°C to 85°C
0.5
22
0.5
22
0.5
22
0.5
22
–40°C to 125°C
0.5
24
0.5
24
0.5
24
0.5
24
From inputOE
to output B
–40°C to 85°C
0.5
111
0.5
84
0.5
75
0.5
80
–40°C to 125°C
0.5
113
0.5
86
0.5
78
0.5
83
From input OE
to output A
–40°C to 85°C
0.5
9
0.5
9
0.5
9
0.5
9
–40°C to 125°C
0.5
10
0.5
10
0.5
10
0.5
10
From input OE
to output B
–40°C to 85°C
0.5
154
0.5
86
0.5
51
0.5
20
–40°C to 125°C
0.5
154
0.5
86
0.5
51
0.5
20
Disable time
Enable time
UNIT
ns
ns
ns
B-PORT SUPPLY VOLTAGE (VCCB)
PARAMETER
tpd
tdis
ten
Propagation
delay
TEST CONDITIONS
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
From input A
to output B
–40°C to 85°C
0.5
5
0.5
4
0.5
4
0.5
4
–40°C to 125°C
0.5
5
0.5
4
0.5
4
0.5
4
From input B
to output A
–40°C to 85°C
0.5
5
0.5
5
0.5
4
0.5
4
–40°C to 125°C
0.5
6
0.5
5
0.5
4
0.5
4
From inputOE
to output A
–40°C to 85°C
0.5
22
0.5
22
0.5
22
0.5
22
–40°C to 125°C
0.5
24
0.5
24
0.5
24
0.5
24
From inputOE
to output B
–40°C to 85°C
0.5
30
0.5
27
0.5
25
0.5
23
–40°C to 125°C
0.5
33
0.5
30
0.5
27
0.5
25
From input OE
to output A
–40°C to 85°C
0.5
9
0.5
9
0.5
9
0.5
9
–40°C to 125°C
0.5
10
0.5
10
0.5
10
0.5
10
From input OE
to output B
–40°C to 85°C
0.5
13
0.5
10
0.5
8
0.5
7
–40°C to 125°C
0.5
14
0.5
11
0.5
8
0.5
7
Disable time
Enable time
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UNIT
ns
ns
ns
15
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SCES875B – MARCH 2018 – REVISED AUGUST 2018
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6.14 Operating Characteristics: TA = 25°C
PARAMETER
CpdA
CpdA
CpdA
CpdA
16
Power dissipation
capacitance per transceiver
(A to B: outputs enabled)
Power dissipation
capacitance per transceiver
(A to B: outputs disabled)
Power dissipation
capacitance per transceiver
(B to A: outputs enabled)
Power dissipation
capacitance per transceiver
(B to A: outputs disabled)
TEST CONDITIONS
CL = 0, RL = Open
f = 1 MHz, tr = tf = 1 ns
CL = 0, RL = Open
f = 1 MHz, tr = tf = 1 ns
CL = 0, RL = Open
f = 1 MHz, tr = tf = 1 ns
CL = 0, RL = Open
f = 1 MHz, tr = tf = 1 ns
MIN
TYP
VCCA = VCCB = 0.7 V
1.2
VCCA = VCCB = 0.8 V
1.8
VCCA = VCCB = 0.9 V
1.8
VCCA = VCCB = 1.2 V
1.7
VCCA = VCCB = 1.5 V
1.7
VCCA = VCCB = 1.8 V
1.7
VCCA = VCCB = 2.5 V
2
VCCA = VCCB = 3.3 V
2.5
VCCA = VCCB = 0.7 V
1.1
VCCA = VCCB = 0.8 V
1.8
VCCA = VCCB = 0.9 V
1.8
VCCA = VCCB = 1.2 V
1.7
VCCA = VCCB = 1.5 V
1.7
VCCA = VCCB = 1.8 V
1.7
VCCA = VCCB = 2.5 V
2
VCCA = VCCB = 3.3 V
2.1
VCCA = VCCB = 0.7 V
9.3
VCCA = VCCB = 0.8 V
11.8
VCCA = VCCB = 0.9 V
11.8
VCCA = VCCB = 1.2 V
12
VCCA = VCCB = 1.5 V
12.2
VCCA = VCCB = 1.8 V
13
VCCA = VCCB = 2.5 V
16.4
VCCA = VCCB = 3.3 V
18.1
VCCA = VCCB = 0.7 V
2.6
VCCA = VCCB = 0.8 V
1.2
VCCA = VCCB = 0.9 V
1.1
VCCA = VCCB = 1.2 V
1.2
VCCA = VCCB = 1.5 V
1.2
VCCA = VCCB = 1.8 V
1.3
VCCA = VCCB = 2.5 V
1.6
VCCA = VCCB = 3.3 V
3.9
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MAX
UNIT
pF
pF
pF
pF
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Operating Characteristics: TA = 25°C (continued)
PARAMETER
CpdB
CpdB
CpdB
CpdB
Power dissipation
capacitance per transceiver
(A to B: outputs enabled)
Power dissipation
capacitance per transceiver
(A to B: outputs disabled)
Power dissipation
capacitance per transceiver
(B to A: outputs enabled)
Power dissipation
capacitance per transceiver
(B to A: outputs disabled)
TEST CONDITIONS
CL = 0, RL = Open
f = 1 MHz, tr = tf = 1 ns
CL = 0, RL = Open
f = 1 MHz, tr = tf = 1 ns
CL = 0, RL = Open
f = 1 MHz, tr = tf = 1 ns
CL = 0, RL = Open
f = 1 MHz, tr = tf = 1 ns
MIN
TYP
VCCA = VCCB = 0.7 V
9.3
VCCA = VCCB = 0.8 V
11.7
VCCA = VCCB = 0.9 V
11.8
VCCA = VCCB = 1.2 V
11.9
VCCA = VCCB = 1.5 V
12.2
VCCA = VCCB = 1.8 V
12.9
VCCA = VCCB = 2.5 V
16.3
VCCA = VCCB = 3.3 V
18
VCCA = VCCB = 0.7 V
2.6
VCCA = VCCB = 0.8 V
11.7
VCCA = VCCB = 0.9 V
11.8
VCCA = VCCB = 1.2 V
11.9
VCCA = VCCB = 1.5 V
12.2
VCCA = VCCB = 1.8 V
12.9
VCCA = VCCB = 2.5 V
16.3
VCCA = VCCB = 3.3 V
3.9
VCCA = VCCB = 0.7 V
1.2
VCCA = VCCB = 0.8 V
1.8
VCCA = VCCB = 0.9 V
1.8
VCCA = VCCB = 1.2 V
1.7
VCCA = VCCB = 1.5 V
1.7
VCCA = VCCB = 1.8 V
1.7
VCCA = VCCB = 2.5 V
2
VCCA = VCCB = 3.3 V
2.5
VCCA = VCCB = 0.7 V
1.1
VCCA = VCCB = 0.8 V
1.8
VCCA = VCCB = 0.9 V
1.8
VCCA = VCCB = 1.2 V
1.7
VCCA = VCCB = 1.5 V
1.7
VCCA = VCCB = 1.8 V
1.7
VCCA = VCCB = 2.5 V
2
VCCA = VCCB = 3.3 V
2.1
MAX
UNIT
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pF
pF
pF
pF
17
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7 Parameter Measurement Information
Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:
• f =1 MHz
• Z0 = 50 Ω
• dv / dt ≤ 1 ns/V
Measurement Point
2 X VCCO
S1
RL
Open
Output Pin
Under Test
GND
CL(1)
(1)
RL
CL includes probe and jig capacitance.
Figure 1. Load Circuit
VCCO
CL
S1
VTP
2k
15 pF
Open
N/A
0.65 V - 0.95 V 20 k
15 pF
Open
N/A
Parameter
1.1 V - 3.6 V
tpd
ten(1), tdis(1)
3 V - 3.6 V
2k
15 pF
2 X VCCO
0.3 V
1.65 V - 2.7 V
2k
15 pF
2 X VCCO
0.15 V
1.1 V - 1.6 V
2k
15 pF
2 X VCCO
0.1 V
0.65 V - 0.95 V 20 k
15 pF
2 X VCCO
0.1 V
2k
15 pF
GND
0.3 V
1.65V - 2.7 V
2k
15 pF
GND
0.15 V
1.1 V - 1.6 V
2k
15 pF
GND
0.1 V
0.65 V - 0.95 V 20 k
15 pF
GND
0.1 V
3 V - 3.6 V
ten(2), tdis(2)
RL
(1)
Output waveform on the conditions that input is driven to a valid Logic Low.
(2)
Output waveform on the condition that input is driven to a valid Logic High.
Figure 2. Load Circuit Conditions
VCCI(1)
An, Bn Input
VCCI / 2
VCCI / 2
GND
tpd
tpd
VOH(2)
Bn, An Output
VCCO / 2
VCCO / 2
VOL(2)
(1)
VCCI is the supply pin associated with the input port.
(2)
VOH and VOL are typical output voltage levels with specified RL, CL, and S1.
Figure 3. Propagation Delay
18
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Parameter Measurement Information (continued)
VCCA
OE
VCCA / 2
VCCA / 2
GND
tdis
ten
VCCO(3)
Output(1)
VCCO / 2
VOL + VTP
VOL(4)
VOH(4)
VOH - VTP
Output(2)
VCCO / 2
GND
(1)
Output waveform on the condition that input is driven to a valid Logic Low.
(2)
Output waveform on the condition that input is driven to a valid Logic High.
(3)
VCCO is the supply pin associated with the output port.
(4)
VOH and VOL are typical output voltage levels with specified RL, CL, and S1.
Figure 4. Enable Time And Disable Time
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8 Detailed Description
8.1 Overview
The SN74AXC8T245 device is an 8-bit, dual-supply non-inverting transceiver with bidirectional voltage level
translation. The I/O pins labeled with A and the control pins (DIR1, DIR2, and OE) are supported by VCCA, and
the I/O pins labeled with B are supported by VCCB. Both the A port and the B port are able to accept I/O voltages
ranging from 0.65 V to 3.6 V.
8.2 Functional Block Diagram
OE
DIR1
Control Block To Enable or
Disable Outputs (Note: Inputs
on each buffer are always
enabled)
DIR2
20
VCCA
VCCB
GND
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
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8.3 Feature Description
8.3.1 Up-Translation and Down-Translation From 0.65 V to 3.6 V
Both supply pins are configured from 0.65 V to 3.6 V, which makes the device suitable for translating between
any of the low voltage nodes (0.7 V, 0.8 V, 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V).
8.3.2 Multiple Direction Control Pins
Two control pins are used to configure the 8 data I/Os. I/O channels 1 through 4 are grouped together and I/O
channels 5 through 8 are banked together. The benefit of this is to permit simultaneous up-translation and downtranslation within one device. This eliminates the need for multiple devices, where each device can only provide
up-translation or down-translation sequentially. Simultaneous up and down translation is supported when both
VCCA and VCCB are at least 1.40 V.
8.3.3 Ioff Supports Partial-Power-Down Mode Operation
This feature is to limit the leakage current of an I/O pin being driven to a voltage as large as 3.6 V while having
its corresponding power supply rail powered down. This is represented by the Ioff parameter in the Electrical
Characteristics table.
8.4 Device Functional Modes
All control inputs are referenced to VCCA and must be driven to a valid Logic High or Logic Low (that is, not
floating) to assure proper device operation and to prevent excessive power consumption. Table 1 summarizes
the possible modes of device operation based on the configuration of the control inputs.
Table 1. Function Table (1)
CONTROL INPUTS
(1)
Signal Direction
OE
DIR1
DIR2
H
X
X
Bits 1:4
Disabled (Hi-Z)
Bits 5:8
L
L
L
B to A
L
L
H
L
H
L
L
H
H
B to A
A to B
A to B
A to B
B to A
Input circuits of the data I/Os are always active and must be driven to a valid logic level.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74AXC8T245 device can be used in level-translation applications for interfacing devices or systems
operating at different voltage nodes. Figure 5 depicts an application in which the SN74AXC8T245 device is uptranslating a 0.7 V input to a 3.3 V output to interface between a system controller and a peripheral device.
9.2 Typical Application
0.7 V
3.3 V
0.1 µF
0.1 µF
10
NŸ
10
NŸ
VCCA
VCCB
OE
DIR1
10
NŸ
DIR2
GND
Controller
SN74AXC8T245
Peripheral
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
Figure 5. Typical Application Schematic
22
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Typical Application (continued)
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 2.
Table 2. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUE
Input voltage range
0.65 V to 3.6 V
Output voltage range
0.65 V to 3.6 V
9.2.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the SN74AXC8T245 device to determine the input
voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low
the value must be less than the VIL of the input port.
• Output voltage range
– Use the supply voltage of the device that the SN74AXC8T245 device is driving to determine the output
voltage range.
9.2.3 Application Curve
Figure 6. Translation Up (0.7 V to 3.3 V) at 2.5 MHz
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10 Power Supply Recommendations
Always apply a ground reference to the GND pins first. However, there are no additional requirements for power
supply sequencing.
This device was designed with various power supply sequencing methods in mind to help prevent unintended
triggering of downstream devices. For more information regarding the power up glitch performance of the AXC
family of level translators, see the Power Sequencing for AXC Family of Devices application report.
11 Layout
11.1 Layout Guidelines
To
•
•
•
assure reliability of the device, follow common printed-circuit board layout guidelines.
Use bypass capacitors on power supplies.
Use short trace lengths to avoid excessive loading.
Place pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of
signals depending on the system requirements.
11.2 Layout Example
LEGEND
Polygonal Copper Pour
VIA to Power Plane (Inner Layer)
VIA to GND Plane (Inner Layer)
Bypass Capacitor
Bypass
Capacitor
VCCA
1
VCCA
VCCB
24
2
DIR1
VCCB
23
From Source
3
A1
OE
22
From Source
4
A2
B1
21
To Destination
From Source
5
A3
B2
20
To Destination
From Source
6
A4
B3
19
To Destination
SN74AXC8T245
(PW Package)
From Source
7
A5
B4
18
To Destination
From Source
8
A6
B5
17
To Destination
From Source
9
A7
B6
16
To Destination
From Source
10
A8
B7
15
To Destination
11
DIR2
B8
14
To Destination
12
GND
GND
13
Figure 7. SN74AXC8T245 Device Layout Example
24
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
Texas Instruments, Power Sequencing for AXC Family of Devices application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: SN74AXC8T245
25
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74AXC8T245PWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AX8T245
SN74AXC8T245RHLR
ACTIVE
VQFN
RHL
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AX8T245
SN74AXC8T245RJWR
ACTIVE
UQFN
RJW
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AX8T245
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2018
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Aug-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74AXC8T245PWR
Package Package Pins
Type Drawing
TSSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
PW
24
2000
330.0
16.4
6.95
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8.3
1.6
8.0
16.0
Q1
SN74AXC8T245RHLR
VQFN
RHL
24
3000
330.0
12.4
3.8
5.8
1.2
8.0
12.0
Q1
SN74AXC8T245RJWR
UQFN
RJW
24
3000
177.8
12.4
2.21
4.22
0.81
4.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Aug-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AXC8T245PWR
TSSOP
PW
24
2000
367.0
367.0
38.0
SN74AXC8T245RHLR
VQFN
RHL
24
3000
367.0
367.0
35.0
SN74AXC8T245RJWR
UQFN
RJW
24
3000
183.0
183.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0024A
TSSOP - 1.2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1
2X
7.15
7.9
7.7
NOTE 3
12
13
B
0.30
0.19
0.1
C A B
24X
4.5
4.3
NOTE 4
1.2 MAX
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220208/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
24X (1.5)
(R0.05) TYP
1
24
24X (0.45)
22X (0.65)
SYMM
13
12
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
24X (1.5)
SYMM
(R0.05) TYP
1
24
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RHL0024A
PLASTIC QUAD FLATPACK- NO LEAD
A
3.6
3.4
B
PIN 1 INDEX AREA
5.6
5.4
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
2.05±0.1
2X 1.5
24X 0.5
0.3
SYMM
13
12
18X 0.5
11
(0.1) TYP
14
21
2X
4.5
SYMM
4.05±0.1
23
2
PIN 1 ID
(OPTIONAL)
1
24
4X (0.2)
2X (0.55)
24X 0.30
0.18
0.1
0.05
C A B
C
4225250/A 09/2019
NOTES:
1.
2.
3.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RHL0024A
PLASTIC QUAD FLATPACK- NO LEAD
(3.3)
(2.05)
2X (1.5)
SYMM
1
24
24X (0.6)
24X (0.24)
2X (0.4)
23
2
18X (0.5)
2X (1.105)
6X (0.67)
25
SYMM
(4.05)
4.6
4.4
(5.3)
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
(Ø 0.2) VIA
TYP
(R0.05) TYP
11
14
13
12
4X
(0.775)
4X (0.2)
2X (0.55)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED METAL
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4225250/A 09/2019
NOTES: (continued)
4.
5.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RHL0024A
PLASTIC QUAD FLATPACK- NO LEAD
(3.3)
(2.05)
2X (1.5)
SYMM
1
SOLDER MASK EDGE
TYP
24
24X (0.6)
24X (0.24)
23
2
18X (0.5)
25
SYMM
4.6
4.4
(5.3)
4X
(1.34)
METAL TYP
(R0.05) TYP
11
14
13
12
2X (0.84)
6X (0.56)
4X (0.2)
2X (0.55)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
80% PRINTED COVERAGE BY AREA
SCALE: 18X
4225250/A 09/2019
NOTES: (continued)
6.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
RJW0024A
UQFN - 0.55 mm max height
SCALE 4.300
PLASTIC QUAD FLATPACK - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
4.1
3.9
C
0.55 MAX
SEATING PLANE
0.05
0.00
0.05 C
2X 0.4
11
(0.1) TYP
12
10
13
4X
0.6
0.5
SYMM
2X
3.6
1
20X 0.4
24
23
SYMM
12X
0.85
0.75
8X
22
24X
0.25
0.15
0.1
0.05
C A B
C
0.55
0.45
4223932/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RJW0024A
UQFN - 0.55 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
12X 1
8X (0.7)
24
23
1
22
24X (0.2)
20X (0.4)
SYMM
(3.65)
(R0.05) TYP
(4X 0.75)
13
10
12
11
(1.4)
(1.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.0375 MAX
ALL AROUND
0.0375 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
METAL
UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4223932/B 04/2018
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RJW0024A
UQFN - 0.55 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
8X
(0.65)
12X 0.95
23
24
1
22
24X (0.2)
20X (0.4)
SYMM
(3.7)
(R0.05) TYP
EXPOSED METAL
TYP
4X (0.7)
13
10
12
11
(1.45)
(1.75)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICKNESS
SCALE: 25X
4223932/B 04/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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