Texas Instruments | TXB0106-Q1 6-Bit Bidirectional Voltage-Level Translator With Auto-Direction Sensing and ±10-kV ESD Protection (Rev. A) | Datasheet | Texas Instruments TXB0106-Q1 6-Bit Bidirectional Voltage-Level Translator With Auto-Direction Sensing and ±10-kV ESD Protection (Rev. A) Datasheet

Texas Instruments TXB0106-Q1 6-Bit Bidirectional Voltage-Level Translator With Auto-Direction Sensing and ±10-kV ESD Protection (Rev. A) Datasheet
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TXB0106-Q1
SCES791A – AUGUST 2009 – REVISED APRIL 2018
TXB0106-Q1 6-Bit Bidirectional Voltage-Level Translator
With Auto-Direction Sensing and ±10-kV ESD Protection
1 Features
3 Description
•
•
This 6-bit noninverting translator uses two separate
configurable power-supply rails. The A port is
designed to track VCCA. VCCA accepts any supply
voltage from 1.2 V to 3.6 V. The B port is designed to
track VCCB. VCCB accepts any supply voltage from
1.65 V to 5.5 V. This allows for universal low-voltage
bidirectional translation between any of the 1.2-V,
1.5-V, 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.
VCCA should not exceed VCCB.
1
•
•
•
•
Qualified for Automotive Applications
1.2 V to 3.6 V on A Port and 1.65 to 5.5 V on
B Port (VCCA ≤ VCCB)
VCC Isolation Feature – If Either VCC Input Is at
GND, All Outputs Are in the High-Impedance
State
OE Input Circuit Referenced to VCCA
Ioff Supports Partial-Power-Down Mode Operation
ESD Protection Exceeds AEC-Q100
– A Port
– 2000-V Human-Body Model
– 1500-V Charged-Device Model
– B Port
– ±10-kV Human-Body Model
– 1500-V Charged-Device Model
When the output-enable (OE) input is low, all outputs
are placed in the high-impedance state.
The TXB0106-Q1 device is designed so that the OE
input circuit is supplied by VCCA.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
To ensure the high-impedance state during power up
or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
2 Applications
•
•
•
Heating and Cooling
Telematics
Radar
Device Information(1)
PART NUMBER
TXB0106-Q1
PACKAGE
TSSOP (16)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Operating Circuit
1.8 V
3.3 V
VCCA
VCCB
OE
1.8-V
System
Controller
Data
3.3-V
System
TXB0106
A1
A2
B1
B2
A3
A4
A5
A6
B3
B4
B5
B6
Data
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TXB0106-Q1
SCES791A – AUGUST 2009 – REVISED APRIL 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
4
4
4
5
5
6
6
6
6
6
Absolute Maximum Ratings .....................................
ESD Ratings ............................................................
Recommended Operating Conditions ......................
Thermal Information .................................................
Electrical Characteristics ..........................................
Timing Requirements – VCCA = 1.2 V, TA = 25°C.....
Timing Requirements – VCCA = 1.5 V ± 0.1 V ..........
Timing Requirements – VCCA = 1.8 V ± 0.15 V ........
Timing Requirements – VCCA = 2.5 V ± 0.2 V ..........
Timing Requirements – VCCA = 3.3 V ± 0.3 V ........
Switching Characteristics –VCCA = 1.2 V, TA =
25°C ...........................................................................
6.12 Switching Characteristics – VCCA = 1.5 V ± 0.1 V ..
6.13 Switching Characteristics – VCCA = 1.8 V ± 0.15 V
6.14 Switching Characteristics – VCCA = 2.5 V ± 0.2 V ..
6.15 Switching Characteristics – VCCA = 3.3 V ± 0.3 V .
6.16 Operating Characteristics........................................
7
7
8
8
9
9
6.17 Typical Characteristics .......................................... 10
7
8
Parameter Measurement Information ................ 11
Detailed Description ............................................ 12
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
13
14
16
Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Application ................................................. 17
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August 2009) to Revision A
Page
•
Added Applications section, ESD Ratings table, Feature Description section, Device Functional Modes section,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1
•
Changed the entry in the TYPE column from "—" to "I" for VCCA and VCCB .......................................................................... 3
•
Added row for junction temperature to Absolute Maximum Ratings ..................................................................................... 4
•
Added parameter descriptons to Electrical Characteristics table .......................................................................................... 5
•
Added "-Q1" to the device name throughout the document................................................................................................. 12
•
Changed I to ICC in Output Load Considerations.................................................................................................................. 15
•
Changed TXS01xx series to TXS family in Pullup or Pulldown Resistors on I/O Lines ...................................................... 16
•
Changed TXS010X to TXS in Application Information ......................................................................................................... 17
•
Clarified wording of sentences and added references to two application reports ................................................................ 18
2
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SCES791A – AUGUST 2009 – REVISED APRIL 2018
5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
A1
1
16
B1
VCCA
2
15
VCCB
A2
3
14
B2
A3
4
13
B3
A4
5
12
B4
A5
6
11
B5
A6
7
10
B6
OE
8
9
GND
Pin Functions
NAME
NO.
I/O
A1
1
I/O
Input/output 1. Referenced to VCCA.
DESCRIPTION
A2
3
I/O
Input/output 2. Referenced to VCCA.
A3
4
I/O
Input/output 3. Referenced to VCCA.
A4
5
I/O
Input/output 4. Referenced to VCCA.
A5
6
I/O
Input/output 5. Referenced to VCCA.
A6
7
I/O
Input/output 6. Referenced to VCCA.
B1
16
I/O
Input/output 1. Referenced to VCCB.
B2
14
I/O
Input/output 2. Referenced to VCCB.
B3
13
I/O
Input/output 3. Referenced to VCCB.
B4
12
I/O
Input/output 4. Referenced to VCCB.
B5
11
I/O
Input/output 5. Referenced to VCCB.
B6
10
I/O
Input/output 6. Referenced to VCCB.
GND
9
—
Ground
OE
8
I
Output enable. Pull OE low to place all outputs in the high-impedance state. Referenced to VCCA.
VCCA
2
I
A-port supply voltage. 1.2 V ≤ VCCA≤ 3.6 V, VCCA≤ VCCB.
VCCB
15
I
B-port supply voltage. 1.65 V ≤ VCCB ≤ 5.5 V.
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating ambient temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCCA
Supply voltage range
–0.5
4.6
V
VCCB
Supply voltage range
–0.5
6.5
V
VI
Input voltage range (2)
–0.5
6.5
V
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
A inputs
–0.5
VCCA + 0.5
B inputs
–0.5
VCCB + 0.5
VO
Voltage range applied to any output in the high or low state (2)
(3)
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCCA, VCCB, or GND
±100
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature range
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The values of VCCA and VCCB are provided in the Recommended Operating Conditions table.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC
Q100-011
±1500
(2)
VCCA
VCCA
VCCB
VCCB
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
Δt/Δv
Input transition rise or fall rate
TA
Operating ambient temperature
4
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions (1)
(1)
(2)
(3)
All pins
UNIT
Data inputs
OE
1.2 V to 3.6 V
Data inputs
1.2 V to 5.5 V
OE
1.2 V to 3.6 V
A-port inputs
1.2 V to 3.6 V
B-port inputs
1.2 V to 3.6 V
1.65 V to 5.5 V
1.65 V to 5.5 V
MIN
MAX
1.2
3.6
1.65
5.5
VCCI× 0.65 (3)
VCCI
VCCA× 0.65
5.5
0
VCCI× 0.35 (3)
0
VCCA× 0.35
1.65 V to 5.5 V
40
1.65 V to 3.6 V
40
4.5 V to 5.5 V
UNIT
V
V
V
ns/V
30
–40
85
°C
The A and B sides of an unused data I/O pair must be held in the same state, that is, both at VCCI or both at GND.
VCCA must be less than or equal to VCCB and must not exceed 3.6 V.
VCCI is the supply voltage associated with the input port.
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6.4 Thermal Information
TXB0106-Q1
THERMAL METRIC (1)
PW (TSSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
107.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
42.3
°C/W
RθJB
Junction-to-board thermal resistance
52.6
°C/W
ψJT
Junction-to-top characterization parameter
4.2
°C/W
ψJB
Junction-to-board characterization parameter
52
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics (1)
(2)
over recommended operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
VCCA
VCCB
1.2 V
Output high
voltage, A port
IOH = –20 μA
VOLA
Output low
voltage, A port
IOL = 20 μA
VOHB
Output high
voltage, B port
IOH = –20 μA
1.65 V to 5.5 V
VOLB
Output low
voltage, B port
IOL = 20 μA
1.65 V to 5.5 V
Ilkg(off
OE
A port
)
B port
IOZ
A or B port
Input leakage
current
Off-state
leakage
current
0.4
V
μA
0V
0 V to 5.5 V
±1
±2
0 V to 3.6 V
0V
±1
±2
1.65 V to 5.5 V
±1
±2
1.2 V to 3.6 V
VCCA supply
current
VI = VCCI or
GND,
IO = 0
1.4 V to 3.6 V
1.65 V to 5.5 V
3.6 V
0V
0V
5.5 V
Combined
supply current
1.2 V
ICCA + ICCB
VI = VCCI or
GND,
IO = 0
ICCZA
Highimpedance
VCCA supply
current
VI = VCCI or
GND,
IO = 0,
OE = GND
ICCZB
Highimpedance
VCCB supply
current
VI = VCCI or
GND,
IO = 0,
OE = GND
1.65 V to 5.5 V
3.6 V
0V
0V
5.5 V
1.4 V to 3.6 V
1.2 V to 3.6 V
μA
0.06
9
2
μA
2
3.4
9
–2
μA
2
1.65 V to 5.5 V
18
μA
0.05
1.65 V to 5.5 V
1.2 V
1.4 V to 3.6 V
μA
3.5
1.2 V
1.4 V to 3.6 V
V
V
±2
1.4 V to 3.6 V
(1)
(2)
VCCB –
0.4
±1
OE = GND
Input
capacitance
0.4
1.65 V to 5.5 V
VI = VCCI or
GND,
IO = 0
OE
0.9
1.2 V to 3.6 V
Highimpedance
output current
UNIT
V
VCCA –
0.4
1.2 V
VCCB supply
current
CI
MIN MAX
1.4 V to 3.6 V
1.2 V
ICCB
TYP MAX
1.4 V to 3.6 V
1.2 V
ICCA
MIN
–40°C to 85°C
1.1
VOHA
Ilkg(I)
TA = 25°C
5
μA
3.3
1.65 V to 5.5 V
1.65 V to 5.5 V
5
5
5.5
μA
pF
VCCI is the supply voltage associated with the input port.
VCCO is the supply voltage associated with the output port.
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Electrical Characteristics(1) (2) (continued)
over recommended operating ambient temperature range (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
Cio
A port
B port
TA = 25°C
VCCA
VCCB
1.2 V to 3.6 V
1.65 V to 5.5 V
MIN
–40°C to 85°C
TYP MAX
MIN MAX
5
6.5
8
10
UNIT
pF
6.6 Timing Requirements – VCCA = 1.2 V, TA = 25°C
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
TYP
TYP
TYP
TYP
20
20
20
20
Mbps
50
50
50
50
ns
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
Data rate
tw
Pulse duration
Data inputs
UNIT
6.7 Timing Requirements – VCCA = 1.5 V ± 0.1 V
over recommended operating ambient temperature range (unless otherwise noted)
VCCB = 1.8 V
± 0.15 V
MIN
MAX
Data rate
tw
Pulse duration
VCCB = 2.5 V
± 0.2 V
MIN
MAX
50
Data inputs
MIN
50
20
MAX
MIN
50
20
50
20
UNIT
MAX
20
Mbps
ns
6.8 Timing Requirements – VCCA = 1.8 V ± 0.15 V
over recommended operating ambient temperature range (unless otherwise noted)
VCCB = 1.8 V
± 0.15 V
MIN
MAX
Data rate
tw
Pulse duration
VCCB = 2.5 V
± 0.2 V
MIN
MAX
52
Data inputs
VCCB = 3.3 V
± 0.3 V
MIN
60
19
VCCB = 5 V
± 0.5 V
MAX
MIN
60
17
60
17
UNIT
MAX
17
Mbps
ns
6.9 Timing Requirements – VCCA = 2.5 V ± 0.2 V
over recommended operating ambient temperature range (unless otherwise noted)
VCCB = 2.5 V
± 0.2 V
MIN
Data rate
tw
Pulse duration
VCCB = 3.3 V
± 0.3 V
MAX
MIN
MAX
70
Data inputs
VCCB = 5 V
± 0.5 V
MIN
100
14
UNIT
MAX
100
10
10
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
Mbps
ns
6.10 Timing Requirements – VCCA = 3.3 V ± 0.3 V
over recommended operating ambient temperature range (unless otherwise noted)
MIN
Data rate
tw
6
Pulse duration
MAX
MIN
100
Data inputs
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10
UNIT
MAX
100
10
Mbps
ns
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6.11 Switching Characteristics –VCCA = 1.2 V, TA = 25°C
FROM
(INPUT)
TO
(OUTPUT)
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
TYP
TYP
TYP
TYP
A
B
9.5
7.9
7.6
8.5
B
A
9.2
8.8
8.4
8
A
1
1
1
1
B
1
1
1
1
A
20
17
17
18
B
20
16
15
15
trA, tfA
A-port rise and fall times
4.1
4.4
4.1
3.9
ns
trB, tfB
B-port rise and fall times
5
5
5.1
5.1
ns
tSK(O)
Channel-to-channel skew
2.4
1.7
1.9
7
ns
20
20
20
20
Mbps
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
PARAMETER
tpd
ten
tdis
(1)
OE
OE
Max. data rate
(1)
UNIT
ns
μs
ns
Test procedure uses a 25-MHz sine wave on the input.
6.12 Switching Characteristics – VCCA = 1.5 V ± 0.1 V
over recommended operating ambient temperature range (unless otherwise noted)
PARAMETER
tpd
ten
FROM
(INPUT)
TO
(OUTPUT)
A
B
OE
VCCB = 2.5 V
± 0.2 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
B
1.4
13.5
1.2
10.5
1.1
10.5
0.8
10.1
A
0.9
15.2
0.7
13.8
0.4
13.8
0.3
13.7
A
1
1
1
1
B
1
1
1
1
ns
μs
A
6.6
33
6.4
25.3
6.1
23.1
5.9
24.6
B
6.6
35.6
5.8
25.6
5.5
22.1
5.6
20.6
trA, tfA
A-port rise and fall times
0.8
6.5
0.8
6.3
0.8
6.3
0.8
6.3
ns
trB, tfB
B-port rise and fall times
1
7.3
0.7
4.9
0.7
4.6
0.6
4.6
ns
tSK(O)
Channel-to-channel skew
1.3
ns
tdis
(1)
OE
Max data rate
(1)
VCCB = 1.8 V
± 0.15 V
2.6
50
1.9
50
1.6
50
50
ns
Mbps
Test procedure uses a 25-MHz sine wave on the input.
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6.13 Switching Characteristics – VCCA = 1.8 V ± 0.15 V
over recommended operating ambient temperature range (unless otherwise noted)
PARAMETER
tpd
ten
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
OE
MIN
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
UNIT
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1.6
12
1.4
7.7
1.3
6.8
1.2
6.5
1.5
13.5
1.2
10
0.8
8.2
0.5
8
A
1
1
1
1
B
1
1
1
1
ns
μs
A
5.9
26.7
5.6
21.6
5.4
18.9
4.8
18.7
B
6.1
33.9
5.2
23.7
5
19.9
5
17.6
trA, tfA
A-port rise and fall times
0.7
5.1
0.7
5
1
5
0.7
5
ns
trB, tfB
B-port rise and fall times
1
7.3
0.7
5
0.7
3.9
0.6
3.8
ns
tSK(O)
Channel-to-channel skew
0.6
ns
tdis
(1)
OE
Max data rate
(1)
VCCB = 1.8 V
± 0.15 V
0.8
0.7
52
60
0.6
60
60
ns
Mbps
Test procedure uses a 25-MHz sine wave on the input.
6.14 Switching Characteristics – VCCA = 2.5 V ± 0.2 V
over recommended operating ambient temperature range (unless otherwise noted)
PARAMETER
tpd
ten
FROM
(INPUT)
TO
(OUTPUT)
A
B
OE
MIN
MAX
B
1.1
A
1
VCCB = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
6.7
1
5.7
0.9
5
8.5
0.6
7
0.3
7
A
1
1
1
B
1
1
1
ns
μs
5
16.9
4.9
15
4.5
13.8
B
4.8
21.8
4.5
17.9
4.4
15.2
trA, tfA
A-port rise and fall times
0.8
3.6
0.6
3.6
0.5
3.5
ns
trB, tfB
B-port rise and fall times
0.6
4.9
0.7
3.9
0.6
3.2
ns
tSK(O)
Channel-to-channel skew
0.3
ns
(1)
OE
Max data rate
8
VCCB = 3.3 V
± 0.3 V
A
tdis
(1)
VCCB = 2.5 V
± 0.2 V
0.4
70
0.3
100
100
ns
Mbps
Test procedure uses a 25-MHz sine wave on the input.
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6.15 Switching Characteristics – VCCA = 3.3 V ± 0.3 V
over recommended operating ambient temperature range (unless otherwise noted)
PARAMETER
tpd
ten
FROM
(INPUT)
TO
(OUTPUT)
A
B
OE
VCCB = 3.3 V
± 0.3 V
UNIT
MIN
MAX
MIN
MAX
B
0.9
5.5
0.8
4.5
A
0.5
6.5
0.2
6
A
1
1
B
1
1
ns
μs
A
4.5
13.9
4.1
12.4
B
4.1
17.3
4
14.4
trA, tfA
A-port rise and fall times
0.5
3
0.5
3
ns
trB, tfB
B-port rise and fall times
0.7
3.9
0.6
3.2
ns
tSK(O)
Channel-to-channel skew
0.3
ns
tdis
(1)
OE
0.4
Max data rate
(1)
VCCB = 5 V
± 0.5 V
100
ns
100
Mbps
Test procedure uses a 25-MHz sine wave on the input.
6.16 Operating Characteristics
TA = 25°C
VCCA
1.2 V
1.2 V
1.5 V
1.8 V
2.5 V
2.5 V
3.3 V
2.5 V
5V
3.3 V
to
5V
VCCB
PARAMETER
TEST CONDITIONS
5V
CpdA
CpdB
CpdA
CpdB
A-port input, B-port output
B-port input, A-port output
A-port input, B-port output
B-port input, A-port output
A-port input, B-port output
B-port input, A-port output
A-port input, B-port output
B-port input, A-port output
CL = 0, f = 10 MHz,
tr = tf = 1 ns,
OE = VCCA
(outputs enabled)
CL = 0, f = 10 MHz,
tr = tf = 1 ns,
OE = GND
(outputs disabled)
1.8 V
1.8 V
1.8 V
UNIT
TYP
TYP
TYP
TYP
TYP
TYP
9
8
7
7
7
7
TYP
8
12
11
11
11
11
11
11
35
26
27
27
27
27
28
26
19
18
18
18
20
21
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.03
0.01
0.01
0.01
0.01
0.01
0.01
0.03
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pF
pF
pF
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6.17 Typical Characteristics
6
40
25qC (Room Temperature)
85qC
5
A Port I/O Capacitance (pF)
OE Pin Input Capacitance (pF)
6
4
3
2
1
0
5
4
3
2
40
25qC (Room Temperature)
85qC
1
0
0
0.5
1
1.5
2
2.5
3
3.5
4
VCCA (V)
0
0.5
1
1.5
D001
VCCB= 3.3 V
2
2.5
VCCA (V)
3
3.5
4
D002
VCCB= 3.3 V
Figure 1. Input capacitance for OE pin (CI) vs
Power Supply (VCCA)
Figure 2. Capacitance for A port I/O pins (CiO) vs Power
Supply (VCCA)
B Port I/O Capacitance (pF)
12
10
8
6
4
40
25qC (Room Temperature)
85qC
2
0
0
0.5
1
1.5
2
2.5 3
VCCB (V)
3.5
4
4.5
5
5.5
D003
VCCA= 1.8 V
Figure 3. Capacitance for B port I/O pins (CiO) vs Power Supply (VCCB)
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7 Parameter Measurement Information
From Output
Under Test
From Output
Under Test
15 pF
15 pF
1 MW
2 × VCCO
Open
50 kW
LOAD CIRCUIT FOR
ENABLE OR DISABLE
TIME MEASUREMENT
LOAD CIRCUIT FOR MAX. DATA RATE,
PULSE DURATION, PROPAGATION
DELAY, AND OUTPUT RISE AND
FALL TIME MEASUREMENT
S1
50 kW
TEST
S1
tPZL or tPLZ
tPHZ or tPZH
2 × VCCO
Open
VCCI
Input
VCCI / 2
VCCI / 2
0V
tPHL
tPLH
tw
Output
VCCO / 2
0.9 ´ VCCO
0.1 ´ VCCO
tr
VOH
VCCO / 2
VOL
tf
VCCI
Input
VCCI / 2
0V
VOLTAGE WAVEFORMS
FOR PULSE DURATION
VOLTAGE WAVEFORMS FOR
PROPAGATION DELAY TIMES
A.
B.
C.
D.
E.
F.
G.
VCCI / 2
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W, dv/dt ≥ 1 V/ns.
The outputs are measured one at a time, with one transition per measurement.
tPLH and tPHL are the same as tpd.
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuits and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The TXB0106-Q1 device is a 6-bit, directionless voltage-level translator specifically designed for translating logic
voltage levels. The A port is able to accept I/O voltages ranging from 1.2 V to 3.6 V, while the B port can accept
I/O voltages from 1.65 V to 5.5 V. The device is a buffered architecture with edge-rate accelerators (one-shots)
to improve the overall data rate. This device can only translate push-pull CMOS logic outputs. For open-drain
signal translation, see TI’s TXS family of products.
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8.2 Functional Block Diagram
VCCB
VCCA
OE
One-Shot
4 kΩ
A1
B1
One-Shot
4 kΩ
One-Shot
4 kΩ
A2
B2
One-Shot
4 kΩ
One-Shot
4 kΩ
A3
B3
One-Shot
4 kΩ
One-Shot
4 kΩ
A4
B4
One-Shot
4 kΩ
One-Shot
4 kΩ
A5
B5
One-Shot
4 kΩ
One-Shot
4 kΩ
A6
B6
One-Shot
4 kΩ
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8.3 Feature Description
8.3.1 Architecture
The TXB0106-Q1 architecture (see Figure 5) does not require a direction-control signal to control the direction of
data flow from A to B or from B to A. In a dc state, the output drivers of the TXB0106-Q1 device can maintain a
high or low, but are designed to be weak, so that they can be overdriven by an external driver when data on the
bus starts flowing in the opposite direction.
The output one-shots detect rising or falling edges on the A or B ports. During a rising edge, the one-shot turns
on the PMOS transistors (T1, T3) for a short duration, which speeds up the low-to-high transition. Similarly,
during a falling edge, the one-shot turns on the NMOS transistors (T2, T4) for a short duration, which speeds up
the high-to-low transition. The typical output impedance during output transition is 70 Ω at VCCO = 1.2 V to 1.8 V,
50 Ω at VCCO = 1.8 V to 3.3 V, and 40 Ω at VCCO = 3.3 V to 5 V.
VCCA
VCCB
One
Shot
T1
4 kΩ
One
Shot
T2
A
B
One
Shot
T3
4 kΩ
T4
One
Shot
Figure 5. Architecture of the TXB0106-Q1 I/O Cell
8.3.2 Input Driver Requirements
Typical IIN vs VIN characteristics of the TXB0106-Q1 device are shown in Figure 6. For proper operation, the
device driving the data I/Os of the TXB0106-Q1 device must have drive strength of at least ±2 mA.
14
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Feature Description (continued)
IIN
VT/4 kΩ
VIN
–(VD –V T)/4 kΩ
A.
VT is the input threshold voltage of the TXB0106-Q1 device (typically VCCI / 2).
B.
VD is the supply voltage of the external driver.
Figure 6. Typical IIN vs VIN Curve
8.3.3 Power Up
During operation, ensure that VCCA ≤ VCCB at all times. During power-up sequencing, VCCA ≥ VCCB does not
damage the device, so any power supply can be ramped up first. The TXB0106-Q1 device has circuitry that
disables all output ports when either VCC is switched off (VCCA/B = 0 V).
8.3.4 Output Load Considerations
TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading
and to ensure that proper one-shot (O.S.) triggering takes place. PCB signal trace-lengths should be kept short
enough such that the round trip delay of any reflection is less than the O.S. duration. This improves signal
integrity by ensuring that any reflection sees a low impedance at the driver. The O.S. circuits have been
designed to stay on for approximately 10 ns. The maximum capacitance of the lumped load that can be driven
also depends directly on the O.S. duration. With very heavy capacitive loads, the O.S. can time out before the
signal is driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between
dynamic ICC, load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors
add to the capacitance that the TXB0106-Q1 output sees, so it is recommended that this lumped-load
capacitance be considered to avoid O.S. retriggering, bus contention, output signal oscillations, or other adverse
system-level affects.
8.3.5 Enable and Disable
The TXB0106-Q1 device has an OE input that is used to disable the device by setting OE = low, which places all
I/Os in the high-impedance (Hi-Z) state. The disable time (tdis) indicates the delay between when OE goes low
and when the outputs actually get disabled (Hi-Z). The enable time (ten) indicates the amount of time the user
must allow for the O.S. circuitry to become operational after OE is taken high.
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Feature Description (continued)
8.3.6 Pullup or Pulldown Resistors on I/O Lines
The TXB0106-Q1 device is designed to drive capacitive loads of up to 70 pF. The output drivers of the TXB0106Q1 device have low dc drive strength. If pullup or pulldown resistors are connected externally to the data I/Os,
their values must be kept higher than 50 kΩ to ensure that they do not contend with the output drivers of the
TXB0106-Q1 device.
For the same reason, the TXB0106-Q1 device should not be used in applications such as I2C or 1-Wire where an
open-drain driver is connected on the bidirectional data I/O. For these applications, use a device from TI's TXS
family of level translators.
8.4 Device Functional Modes
The TXB0106-Q1 device has two functional modes, enabled and disabled. To disable the device, set the OE
input to low, which places all I/Os in a high-impedance state. Setting the OE input to high will enable the device.
16
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TXB0106-Q1 device can be used in level-translation applications for interfacing devices or systems
operating at different interface voltages with one another. It can only translate push-pull CMOS logic outputs. For
open-drain signal translation, see TI's TXS products. Any external pulldown or pullup resistors are recommended
to be larger than 50 kΩ.
9.2 Typical Application
1.8 V
3.3 V
VCCA
VCCB
OE
1.8-V
System
Controller
Data
3.3-V
System
TXB0106
A1
A2
B1
B2
A3
A4
A5
A6
B3
B4
B5
B6
Data
Figure 7. Typical Operating Circuit
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 1. And make sure that VCCA ≤ VCCB.
Table 1. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUE
Input voltage range
1.2 V to 3.6 V
Output voltage range
1.65 V to 5.5 V
9.2.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
- Use the supply voltage of the device that is driving the TXB0106-Q1 device to determine the input
voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low
the value must be less than the VIL of the input port.
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• Output voltage range
- Use the supply voltage of the device that the TXB0106-Q1 device is driving to determine the output
voltage range.
- Avoid the use of external pullup or pulldown resistors, if possible. If not possible, it is recommended the
value should be larger than 50 kΩ.
• An external pulldown or pullup resistor decreases the output VOH and VOL. Use the following equations to
estimate the VOH and VOL as a result of an external pulldown and pullup resistor. See Effects of External
Pullup and Pulldown Resistors on TXS and TXB Devices and Factors Affecting VOL for TXS and LSF Autobidirectional Translation Devices.
VOH = VCCx × RPD / (RPD + 4.5 kΩ)
VOL = VCCx × 4.5 kΩ / (RPU + 4.5 kΩ)
Where
• VCCx is the output port supply voltage on either VCCA or VCCB
• RPD is the value of the external pulldown resistor
• RPU is the value of the external pullup resistor
• 4.5 kΩ accounts for the tolerance of the serial 4-kΩ resistor in the I/O line.
9.2.3 Application Curve
Figure 8. Level Translation of a 2.5-MHz Signal
10 Power Supply Recommendations
During operation, ensure that VCCA ≤ VCCB at all times. During power-up sequencing, VCCA ≥ VCCB does not
damage the device, so any power supply can be ramped up first. The TXB0106-Q1 device has circuitry that
disables all output ports when either VCC is switched off (VCCA or VCCB= 0 V). The output-enable (OE) input circuit
is designed so that it is supplied by VCCA, and when the (OE) input is low, all outputs are placed in the highimpedance state. To ensure the high-impedance state of the outputs during power up or power down, the OE
input pin must be tied to GND through a pulldown resistor and must not be enabled until VCCA and VCCB are fully
ramped and stable. The minimum value of the pulldown resistor to ground is determined by the current-sourcing
capability of the driver.
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11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, following common printed-circuit board layout guidelines are recommended.
• Bypass capacitors should be used on power supplies, and should be placed as close as possible to the VCCA
and VCCB pins and the GND pin
• Short trace-lengths should be used to avoid excessive loading.
• PCB signal trace-lengths must be kept short enough so that the round-trip delay of any reflection is less than
the O.S. duration, approximately 10 ns, ensuring that any reflection encounters low impedance at the source
driver.
11.2 Layout Example
LEGEND
VIA to Power Plane
Polygonal Copper Pour
VIA to GND Plane (Inner Layer)
To
Controller
1
A1
2
VCCA
B1
16
VCCB
15
To
System
Bypass Capacitor 0.1 µF
Bypass Capacitor 0.1 µF
To
Controller
3
A2
B2
14
To
System
To
Controller
4
A3
B3
13
To
System
To
Controller
5
A4
B4
12
To
System
To
Controller
6
A5
B5
11
To
System
To
Controller
7
A6
B6
10
To
System
8
OE
GND
9
Keep OE Low Until VCCA and
VCCB Are Powered Up
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
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14-Apr-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
TXB0106IPWRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
TSSOP
PW
16
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
YE06Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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14-Apr-2014
OTHER QUALIFIED VERSIONS OF TXB0106-Q1 :
• Catalog: TXB0106
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Apr-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TXB0106IPWRQ1
Package Package Pins
Type Drawing
TSSOP
PW
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
12.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Apr-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TXB0106IPWRQ1
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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