Texas Instruments | SN74AUP1G06 Low-Power Single Inverter With Open-Drain Outputs (Rev. E) | Datasheet | Texas Instruments SN74AUP1G06 Low-Power Single Inverter With Open-Drain Outputs (Rev. E) Datasheet

Texas Instruments SN74AUP1G06 Low-Power Single Inverter With Open-Drain Outputs (Rev. E) Datasheet
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SN74AUP1G06
SCES590E – JULY 2004 – REVISED MARCH 2018
SN74AUP1G06 Low-Power Single Inverter With Open-Drain Outputs
1 Features
2 Applications
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Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
Available in the Texas Instruments NanoStar™
Package
Low Static-Power Consumption
(ICC = 0.9 µA Maximum)
Low Dynamic-Power Consumption
(Cpd = 1 pF Typical at 3.3 V)
Low Input Capacitance (Ci = 1.5 pF Typical)
Low Noise – Overshoot and Undershoot <10% of
VCC
Ioff Supports Partial Power-Down-Mode Operation
Input Hysteresis Allows Slow Input Transition and
Better Switching Noise Immunity at the Input (Vhys
= 250 mV Typical at 3.3 V)
Wide Operating VCC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode Signal
Operation
tpd = 3.6 ns Maximum at 3.3 V
Suitable for Point-to-Point Applications
AV Receivers
Smartphones
Blu-ray Players and Home Theaters
Desktop or Notebook PCs
Embedded PCs
GPS: Personal Navigation Devices
Mobile Internet Devices
Network Projector Front-Ends
Portable Media Players
Smoke Detectors
Solid State Drive (SSD): Enterprise
High-Definition (HDTV)
Tablets: Enterprise
Audio Docks: Portable
3 Description
The AUP family is TI's premier solution to the
industry's low-power needs in battery-powered
portable applications. This family ensures a very low
static and dynamic power consumption across the
entire VCC range of 0.8 V to 3.6 V, resulting in an
increased battery life. This product also maintains
excellent signal integrity (see
AUP – The Lowest-Power Family and Excellent
Signal Integrity).
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74AUP1G06DBV
SOT-23 (5)
2.90 mm × 1.60 mm
SN74AUP1G06DCK
SC70 (5)
2.00 mm × 1.25 mm
SN74AUP1G06DRL
SOT-5X3 (5)
1.60 mm × 1.20 mm
SN74AUP1G06DRY
SON (6)
1.45 mm × 1.00 mm
SN74AUP1G06DSF
SON (6)
1.00 mm x 1.00 mm
SN74AUP1G06YFP
DSBGA (4)
0.76 mm × 0.76 mm
SN74AUP1G06DPW
X2SON (5)
0.80 mm x 0.80 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram
A
2
4
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AUP1G06
SCES590E – JULY 2004 – REVISED MARCH 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Functions and Configurations .......................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
4
4
4
5
5
6
6
6
7
7
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, CL = 5 pF ........................
Switching Characteristics, CL = 10 pF ......................
Switching Characteristics, CL = 15 pF ......................
Switching Characteristics ..........................................
Operating Characteristics........................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 8
Detailed Description ............................................ 10
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
11
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 14
12 Device and Documentation Support ................. 15
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
15
15
13 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (May 2010) to Revision E
Page
•
Added Device Information table, Pin Configuration and Functions section, ESD Ratings table, Thermal Information
table, Feature Description section, Application and Implementation section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1
•
Deleted Ordering Information table, see Mechanical, Packaging, and Orderable Information at the end of the data
sheet ...................................................................................................................................................................................... 1
2
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SCES590E – JULY 2004 – REVISED MARCH 2018
5 Pin Functions and Configurations
NC – No internal connection
DBV Package
5-Pin SOT-23
Top View
NC
1
A
2
GND
3
DCK Package
5-Pin SC70
Top View
VCC
5
NC
1
A
2
GND
3
5
VCC
4
Y
Y
4
See mechanical drawings for dimensions.
DRL Package
5-Pin SOT-5X3
Top View
NC
1
A
2
GND
3
YFP Package
4-Pin DSBGA
Bottom View
1
2
B
GND
Y
A
A
VCC
VCC
5
Y
4
Not to scale
DRY Package
6-Pin SON
Top View
DSF Package
6-Pin SON
Top View
NC
1
6
VCC
A
2
5
NC
GND
3
4
Y
NC
1
6
VCC
A
2
5
NC
GND
3
4
Y
DPW Package(1)
5-Pin X2SON
Top View
GND
NC
A
VCC
Y
Pin Functions
PIN (1)
I/O
DESCRIPTION
DBV, DCK,
DRL, DPW
DRY,
DSF
YFP
A
2
2
A1
I
GND
3
3
B1
—
Ground
NAME
NC
(2)
Input
1
1, 5
—
—
Not connected
VCC
5
6
A2
—
Positive supply
Y
4
4
B2
O
Output
(1)
(2)
See mechanical drawings for dimensions
NC – No internal connection
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage, VCC
Input voltage
(2)
, VI
MIN
MAX
UNIT
–0.5
4.6
V
–0.5
4.6
V
Voltage range applied to any output in the high-impedance or power-off state (2), VO
–0.5
4.6
V
Output voltage range in the high or low state (2), VO
–0.5
VCC + 0.5
V
Input clamp current, IIK
VI < 0
–50
mA
Output clamp current, IOK
VO < 0
–50
mA
Continuous output current, IO
±20
mA
Continuous current through VCC or GND
±50
mA
Junction temperature, Tj
150
°C
150
°C
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
See (1)
VCC
Supply voltage
VCC = 0.8 V
VIH
High-level input voltage
MIN
MAX
UNIT
0.8
3.6
V
VCC
VCC = 1.1 V to 1.95 V
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.6
VCC = 3 V to 3.6 V
2
VCC = 0.8 V
VIL
Low-level input voltage
V
0
VCC = 1.1 V to 1.95 V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.9
V
VI
Input voltage
0
3.6
VO
Output voltage
0
3.6
V
VCC = 0.8 V
20
µA
VCC = 1.1 V
1.1
VCC = 1.4 V
1.7
VCC = 1.65 V
1.9
VCC = 2.3 V
3.1
IOL
Low-level output current
VCC = 3 V
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
4
V
mA
4
VCC = 0.8 V to 3.6 V
–40
200
ns/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
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6.4 Thermal Information
SN74AUP1G06
DBV
(SOT-23)
DCK
(SC70)
DRL
(SOT-5X3)
DRY
(SON)
DPW
(X2SON)
DSF
(SON)
YFP
(DSBGA)
5 PINS
5 PINS
5 PINS
6 PINS
5 PINS
6 PINS
4 PINS
230.5
303.6
295.1
342.1
504.3
377.1
179.3
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
172.7
203.8
131.0
233.1
234.9
187.7
2.8
°C/W
RθJB
Junction-to-board thermal resistance
62.2
100.9
143.9
206.7
370.3
236.6
58.3
°C/W
ψJT
Junction-to-top characterization parameter
49.3
76.1
14.7
63.4
44.5
29.0
1.1
°C/W
ψJB
Junction-to-board characterization parameter
61.6
99.3
144.4
206.7
369.7
236.3
58.6
°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
N/A
165.2
N/A
N/A
°C/W
THERMAL METRIC (1)
RθJA
(1)
Junction-to-ambient thermal resistance
UNIT
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOL = 20 µA
IOL = 1.1 mA
IOL = 1.7 mA
IOL = 1.9 mA
VOL
Low-level output
voltage
IOL = 2.3 mA
IOL = 3.1 mA
IOL = 2.7 mA
IOL = 4 mA
II
Inflection point
current
A input:
VI = GND to 3.6 V
Ioff
Off-state current VI or VO = 0 V to 3.6 V
ΔIof Off-state current
VI or VO = 0 V to 3.6 V
change
f
TA = 25°C
TA = –40°C to +85°C
TA = 25°C
TA = –40°C to +85°C
TA = 25°C
TA = –40°C to +85°C
TA = 25°C
TA = –40°C to +85°C
MIN
TYP
TA = –40°C to +85°C
TA = 25°C
MAX
0.8 V to 3.6 V
0.1
0.3 × VCC
1.1 V
0.3 × VCC
0.31
1.4 V
0.37
0.31
1.65 V
0.35
0.31
0.44
0.45
TA = 25°C
0.31
TA = 25°C
0.33
3V
0.44
TA = –40°C to +85°C
TA = 25°C
TA = –40°C to +85°C
TA = 25°C
TA = –40°C to +85°C
TA = 25°C
TA = –40°C to +85°C
Supply current
VI = GND or VCC to 3.6 V
IO = 0
TA = 25°C
ΔIC
Supply current
change
VI = VCC – 0.6 V
IO = 0
TA = 25°C
Ci
Input
capacitance
VI = VCC or GND, TA = 25°C
Co
Output
capacitance
VO = GND, TA = 25°C
TA = –40°C to +85°C
TA = –40°C to +85°C
V
0.33
2.3 V
TA = –40°C to +85°C
TA = –40°C to +85°C
UNIT
0.1
TA = 25°C
ICC
C
VCC
0.45
0.1
0 V to 3.6 V
0.5
0.2
0V
0.6
0.2
0 V to 0.2 V
0.6
0.5
0.8 V to 3.6 V
0.9
40
3.3 V
50
0V
1.5
3.6 V
1.7
0V
1.7
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µA
µA
µA
µA
µA
pF
pF
5
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6.6 Switching Characteristics, CL = 5 pF
over recommended operating free-air temperature range, CL = 5 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
VCC = 0.8 V
VCC = 1.2 V ± 0.1 V
VCC = 1.5 V ± 0.1 V
tpd
Propagation
delay time
A
Y
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
MIN
TA = 25°C
TA = 25°C
TA = –40°C to +85°C
MAX UNIT
12.4
2.7
12
2
TA = 25°C
2.1
TA = –40°C to +85°C
1.5
TA = 25°C
2.1
TA = –40°C to +85°C
1.2
TA = 25°C
1.4
TA = –40°C to +85°C
TYP
3.5
1.3
TA = –40°C to +85°C
0.8
6.2
7.6
3.1
4.7
ns
5.9
2.2
1
TA = 25°C
9.9
12.8
3.2
3.9
2.2
3.3
3.6
6.7 Switching Characteristics, CL = 10 pF
over recommended operating free-air temperature range, CL = 10 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
VCC = 0.8 V
VCC = 1.2 V ± 0.1 V
VCC = 1.5 V ± 0.1 V
tpd
Propagation
delay time
A
Y
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
MIN
TA = 25°C
TYP
MAX
UNIT
15.1
TA = 25°C
3.6
TA = –40°C to +85°C
2.7
TA = 25°C
2.9
TA = –40°C to +85°C
2.2
TA = 25°C
2.7
TA = –40°C to +85°C
1.8
TA = 25°C
2.1
TA = –40°C to +85°C
1.4
TA = 25°C
1.7
TA = –40°C to +85°C
1.2
12
11.2
14.1
4.3
7
8.6
3.9
5.4
ns
6.7
2.9
3.8
4.5
3
4.5
4.9
6.8 Switching Characteristics, CL = 15 pF
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
VCC = 0.8 V
VCC = 1.2 V ± 0.1 V
VCC = 1.5 V ± 0.1 V
tpd
Propagation
delay time
A
Y
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
6
MIN
TA = 25°C
4.9
TA = –40°C to +85°C
3.4
TA = 25°C
3.5
TA = –40°C to +85°C
2.7
TA = 25°C
3.2
TA = –40°C to +85°C
2.2
TA = 25°C
2.5
TA = –40°C to +85°C
1.7
TA = –40°C to +85°C
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MAX
UNIT
17.4
TA = 25°C
TA = 25°C
TYP
2
1.5
12
12.2
15.2
5
7.7
9.4
4.8
6.6
ns
7.3
3.5
4.5
5.1
3.8
6
6.5
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6.9 Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 3 and Figure 4)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
TEST CONDITIONS
VCC = 0.8 V
VCC = 1.2 V ± 0.1 V
VCC = 1.5 V ± 0.1 V
tpd
Propagation
delay time
A
Y
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
MIN
TA = 25°C
TYP
MAX
UNIT
25.3
TA = 25°C
7.6
TA = –40°C to +85°C
5.6
TA = 25°C
5.9
TA = –40°C to +85°C
4.3
TA = 25°C
4.8
TA = –40°C to +85°C
3.6
TA = 25°C
3.7
TA = –40°C to +85°C
2.8
TA = 25°C
3.2
TA = –40°C to +85°C
2.5
12
16
19.3
7.6
10.1
7.4
10.7
5.4
7.1
6.5
10.5
12
ns
11
7.8
10.8
6.10 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
f = 10 MHz
VCC
TYP
0.8 V
1
1.2 V ± 0.1 V
1
1.5 V ± 0.1 V
1
1.8 V ± 0.15 V
1
2.5 V ± 0.2 V
1
3.3 V ± 0.3 V
1
UNIT
pF
6.11 Typical Characteristics
Static-Power Consumption
(mA)
Dynamic-Power Consumption
(pF)
100%
100%
80%
80%
Switching Characteristics
at 25 MHz
†
3.5
60%
60%
3.3-V
†
Logic
40%
40%
Voltage - V
3
3.3-V
LVC †
Logic
AUP
0%
†
0%
Input
2
1.5
1
Output
0.5
20%
20%
2.5
AUP
0
-0.5
0
Single, dual, and triple gates
5
†
Figure 1. AUP – The Lowest-Power Family
10
15
20 25 30
Time - ns
35
40
45
AUP1G08 data at CL = 15 pF
Figure 2. Excellent Signal Integrity
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7 Parameter Measurement Information
From Output
Under Test
CL
(see Note A)
1MW
LOAD CIRCUIT
CL
VM
VI
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
tw
VCC
Input
VCC/2
VCC/2
VI
VM
Input
0V
VM
VOLTAGE WAVEFORMS
PULSE DURATION
0V
tPHL
tPLH
VOH
VM
Output
VM
VOL
tPHL
VCC
Timing Input
0V
tPLH
tsu
VOH
VM
Output
th
VCC
VM
VOL
Data Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A .
B.
C.
D.
E.
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W, tr/tf = 3 ns.
The outputs are measured one at a time, with one transition per measurement.
tPLH and tPHL are the same as tpd.
All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit And Voltage Waveforms - Propagation Delays, Setup And Hold Times, And Pulse
Width
8
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Parameter Measurement Information (continued)
2 ´ VCC
5 kW
From Output
Under Test
S1
GND
CL
(see Note A)
5 kW
TEST
S1
tPLZ/tPZL
tPHZ/tPZH
2 ´ VCC
GND
LOAD CIRCUIT
CL
VM
VI
VD
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
VCC
Output
Control
Output
Waveform 1
S1 at 2 ´ VCC
(see Note B)
VCC/2
0V
tPZL
tPLZ
VCC
VCC/2
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL + VD
VOL
tPHZ
VCC/2
VOH - VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W, tr/tf = 3 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit And Voltage Waveforms - Enable And Disable Times
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8 Detailed Description
8.1 Overview
The output of this single inverter buffer/driver is open drain, and can be connected to other open-drain outputs to
implement active-low wired-OR or active-high wired-AND functions.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs
when the device is powered down. This inhibits current backflow into the device which prevents damage to the
device.
8.2 Functional Block Diagram
A
2
4
Y
Figure 5. Logic Diagram (Positive Logic)
8.3 Feature Description
8.3.1 CMOS Open-Drain Outputs
The open-drain output allows the device to sink current to GND but not to source current from VCC. When the
output is not actively pulling the line low, it will go into a high impedance state (3-state). This allows the device to
be used for a wide variety of applications, including up-translation and down-translation, as the output voltage
can be determined by an external pullup.
The drive capability of this device creates fast edges into light loads so routing and load conditions should be
considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than
the device can sustain without being damaged. It is important for the power output of the device to be limited to
avoid thermal runaway and damage due to over-current. The electrical and thermal limits defined the in the
Absolute Maximum Ratings must be followed at all times.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modelled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating
Conditions to avoid excessive currents and oscillations. If a slow or noisy input signal is required, a device with a
Schmitt-trigger input should be utilized to condition the input signal prior to the standard CMOS input.
10
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Feature Description (continued)
8.3.3 Clamp Diodes
The inputs and outputs to this device have negative clamping diodes.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
Device
VCC
Logic
Input
-IIK
Output
-IOK
GND
Figure 6. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.4 Partial Power Down (Ioff)
The inputs and outputs for this device enter a high impedance state when the supply voltage is 0 V. The
maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical
Characteristics.
8.3.5 Over-voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Absolute Maximum Ratings.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74AUP1G06 device.
Table 1. Function Table
INPUT
A
OUTPUT
Y
H
L
L
Hi-Z
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Open-drain devices are very commonly used for voltage level translation. In this application, the SN74AUP1G06
is used to translate a 1.8-V output from device A to a 3.3-V input on device B.
9.2 Typical Application
The application schematic shown in Figure 7 includes two generic devices, labeled as "Device A" and "Device
B."
VA
VB
Device A
AUP1G06
A
Y
RPU
CP
Device B
II
CI
Figure 7. Application schematic for voltage translation with SN74AUP1G06
9.2.1 Design Requirements
This device has a standard CMOS input, so be careful to avoid slow or floating inputs that might cause oscillation
or excessive current. Please see the Implications of Slow or FLoating CMOS Inputs Application Report.
This device has an open-drain output, which means that the output enters a high-impedance state when a
normal CMOS device would drive the output high. A pull-up resistor must be added to the output for an opendrain device to have a high output. The selection of this pull-up resistor is detailed in the next section.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– For specified high and low levels, see VIH and VIL in the Electrical Characteristics table.
– Inputs are overvoltage tolerant allowing them to go as high as VI(max) in the Absolute Maximum Ratings
table at any valid VCC.
2. Recommended Output Conditions
– Output voltage must not exceed VO(max) as specified in the Absolute Maximum Ratings table.
– Pull-up resistor (R) selection depends on three primary factors: desired output high voltage (VOH), which
is directly related to total leakage current into the SN74AUP1G240 and the peripheral device's input (IL),
desired 0 to 90% rising edge time (tr), which is directly related to the parasitic line capacitance (CP), and
the maximum current during low output (IOL), which is directly related to the supply value. These three
equations govern pull-up resistor selection:
– R ≤ ( VCC – VOH ) / IL
– R ≤ tr / ( 2.3 * CP)
– R ≥ VCC / IOL(max)
12
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Typical Application (continued)
9.2.3 Application Curve
3.3
Vin
Vout
3
2.7
2.4
Voltage (V)
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
-0.3
0
20
40
60
80
100 120
Time (Ps)
140
160
180
200
Figure 8. Simulated up-translation with the SN74AUP1G06
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-µF capacitor is recommended and if there are multiple VCC pins then a 0.01-µF or 0.022-µF
capacitor is recommended for each power pin. It is ok to parallel multiple bypass caps to reject different
frequencies of noise. 0.1-µF and 1-µF capacitors are commonly used in parallel. The bypass capacitor should be
installed as close to the power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
Even low data rate digital signals can contain high-frequency signal components due to fast edge rates. When a
printed-circuit board (PCB) trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs
primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414
times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance
and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore
some traces must turn corners. Figure 9 shows progressively better techniques of rounding corners. Only the last
example (BEST) maintains constant trace width and minimizes reflections.
An example layout is given in Figure 10 for the DPW (X2SON-5) package. This example layout includes a 0402
(metric) capacitor and uses the measurements found in the example board layout appended to this end of this
datasheet. A via of diameter 0.1 mm (3.973 mil) is placed directly in the center of the device. This via can be
used to trace out the center pin connection through another board layer, or it can be left out of the layout
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11.2 Layout Example
WORST
BETTER
BEST
Figure 9. Trace Example
4 mil
0402
0.1 …F
Bypass
Capacitor
8 mil
8 mil
8 mil
SOLDER MASK
OPENING, TYP
METAL UNDER
SOLDER MASK,
TYP
Figure 10. Example Layout With DPW (X2SON-5) Package
14
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Implications of Slow or Floating CMOS Inputs application note
• Texas Instruments, Designing and Manufacturing with TI's X2SON Packages application note
• Texas Instruments, How to Select Little Logic application note
• Texas Instruments, Introduction to Logic application note
• Texas Instruments, Understanding Schmitt Triggers application note
• Texas Instruments, Semiconductor Packing Material Electrostatic Discharge (ESD) Protection application
note
• Texas Instruments, Logic Guide selection & solution suides
• Texas Instruments, Little Logic Guide 2014 selection & solution guides
• Texas Instruments, Little Logic Guide 2012 selection & solution guides
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
NanoStar, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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PACKAGE OUTLINE
DPW0005A
X2SON - 0.4 mm max height
SCALE 12.000
PLASTIC SMALL OUTLINE - NO LEAD
0.85
0.75
B
A
0.85
0.75
PIN 1 INDEX AREA
0.4 MAX
C
SEATING PLANE
NOTE 3
(0.1)
0.05
0.00
(0.25)
4X (0.05)
0.25 0.1
2
4
2X
0.48
3
NOTE 3
2X (0.26)
5
1
4X
0.27
0.17
(0.06)
3X
0.27
0.17
0.1 C A B
0.05 C
0.32
0.23
4223102/B 09/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The size and shape of this feature may vary.
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EXAMPLE BOARD LAYOUT
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.78)
SYMM
4X (0.42)
( 0.1)
VIA
0.05 MIN
ALL AROUND
TYP
1
5
4X (0.22)
SYMM
4X (0.26)
(0.48)
3
2
4
(R0.05) TYP
( 0.25)
4X (0.06)
(0.21) TYP
EXPOSED METAL
CLEARANCE
SOLDER MASK
OPENING, TYP
METAL UNDER
SOLDER MASK
TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:60X
4223102/B 09/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.42)
4X (0.22)
4X (0.06)
5
1
( 0.24)
4X (0.26)
SYMM
(0.21)
TYP
SOLDER MASK
EDGE
3
2
(R0.05) TYP
(0.48)
4
SYMM
(0.78)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
92% PRINTED SOLDER COVERAGE BY AREA
SCALE:100X
4223102/B 09/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Nov-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74AUP1G06DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
H06R
SN74AUP1G06DBVRE4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
H06R
SN74AUP1G06DBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
H06R
SN74AUP1G06DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
H06R
SN74AUP1G06DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(HT5, HTF, HTK, HT
R)
SN74AUP1G06DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(HT5, HTR)
SN74AUP1G06DPWR
ACTIVE
X2SON
DPW
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CH
SN74AUP1G06DRLR
ACTIVE
SOT-5X3
DRL
5
4000
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
(HT7, HTR)
SN74AUP1G06DRYR
ACTIVE
SON
DRY
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT
SN74AUP1G06DSF2
ACTIVE
SON
DSF
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
HT
SN74AUP1G06DSFR
ACTIVE
SON
DSF
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
HT
SN74AUP1G06YFPR
ACTIVE
DSBGA
YFP
4
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
HT
N
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-Nov-2018
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
SN74AUP1G06DBVR
SOT-23
3000
180.0
8.4
DBV
5
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.23
3.17
1.37
4.0
8.0
Q3
SN74AUP1G06DBVT
SOT-23
DBV
5
250
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
SN74AUP1G06DCKR
SC70
DCK
5
3000
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74AUP1G06DCKR
SC70
DCK
5
3000
180.0
8.4
2.47
2.3
1.25
4.0
8.0
Q3
SN74AUP1G06DCKT
SC70
DCK
5
250
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74AUP1G06DPWR
X2SON
DPW
5
3000
178.0
8.4
0.91
0.91
0.5
2.0
8.0
Q3
SN74AUP1G06DRLR
SOT-5X3
DRL
5
4000
180.0
8.4
1.98
1.78
0.69
4.0
8.0
Q3
SN74AUP1G06DRLR
SOT-5X3
DRL
5
4000
180.0
9.5
1.78
1.78
0.69
4.0
8.0
Q3
SN74AUP1G06DRYR
SON
DRY
6
5000
180.0
9.5
1.15
1.6
0.75
4.0
8.0
Q1
SN74AUP1G06DSF2
SON
DSF
6
5000
180.0
9.5
1.16
1.16
0.5
4.0
8.0
Q3
SN74AUP1G06DSF2
SON
DSF
6
5000
180.0
8.4
1.16
1.16
0.63
4.0
8.0
Q3
SN74AUP1G06DSFR
SON
DSF
6
5000
180.0
9.5
1.16
1.16
0.5
4.0
8.0
Q2
SN74AUP1G06YFPR
DSBGA
YFP
4
3000
178.0
9.2
0.89
0.89
0.58
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AUP1G06DBVR
SOT-23
DBV
5
3000
202.0
201.0
28.0
SN74AUP1G06DBVT
SOT-23
DBV
5
250
202.0
201.0
28.0
SN74AUP1G06DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
SN74AUP1G06DCKR
SC70
DCK
5
3000
202.0
201.0
28.0
SN74AUP1G06DCKT
SC70
DCK
5
250
180.0
180.0
18.0
SN74AUP1G06DPWR
X2SON
DPW
5
3000
205.0
200.0
33.0
SN74AUP1G06DRLR
SOT-5X3
DRL
5
4000
202.0
201.0
28.0
SN74AUP1G06DRLR
SOT-5X3
DRL
5
4000
184.0
184.0
19.0
SN74AUP1G06DRYR
SON
DRY
6
5000
184.0
184.0
19.0
SN74AUP1G06DSF2
SON
DSF
6
5000
184.0
184.0
19.0
SN74AUP1G06DSF2
SON
DSF
6
5000
202.0
201.0
28.0
SN74AUP1G06DSFR
SON
DSF
6
5000
184.0
184.0
19.0
SN74AUP1G06YFPR
DSBGA
YFP
4
3000
270.0
225.0
227.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRY 6
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4207181/G
PACKAGE OUTLINE
DRY0006A
USON - 0.6 mm max height
SCALE 8.500
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
B
A
PIN 1 INDEX AREA
1.5
1.4
C
0.6 MAX
SEATING PLANE
0.05
0.00
0.08 C
3X 0.6
SYMM
(0.127) TYP
(0.05) TYP
3
4
4X
0.5
SYMM
2X
1
1
6
6X
0.4
0.3
PIN 1 ID
(OPTIONAL)
5X
0.25
0.15
0.1
0.05
0.35
0.25
C A B
C
4222894/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DRY0006A
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
6
1
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
LAND PATTERN EXAMPLE
1:1 RATIO WITH PKG SOLDER PADS
EXPOSED METAL SHOWN
SCALE:40X
0.05 MAX
ALL AROUND
EXPOSED
METAL
0.05 MIN
ALL AROUND
EXPOSED
METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222894/A 01/2018
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DRY0006A
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
1
6
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X
4222894/A 01/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DTB0006A
X2SON - 0.35 mm max height
SCALE 12.000
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
B
A
PIN 1 INDEX AREA
0.85
0.75
0.35 MAX
C
SEATING PLANE
(0.1) TYP
0.05 C
2X 0.6
0.4
3
(0.027) TYP
4
0.05
0.00
(0.1)
2X EQUILATERAL
TRIANGLES
0.25
+0.05
TYP
-0.03
PKG
2
5
(0.08)
4X
PIN 1 ID
(OPTIONAL)
NOTE 5
1
PKG
6
4X
0.25
0.17
0.30
0.22
0.1
0.05
C A B
C
4223406/C 02/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pads must be soldered to the printed circuit board for optimal thermal and mechanical performance.
4. The size and shape of this feature may vary.
5. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
www.ti.com
EXAMPLE BOARD LAYOUT
DTB0006A
X2SON - 0.35 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SOLDER MASK OPEING
TYP
4X (0.25)
SYMM
0.05 MIN
ALL AROUND
TYP
6
1
(0.25)
TYP
4X (0.4)
SYMM
5
2
(0.8)
(0.2) TYP
EXPOSED METAL
CLEARANCE
METAL UNDER
SOLDER MASK
TYP
(0.027) TYP
3
4
(0.4)
(0.2)
TYP
(R0.05) TYP
(0.6)
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:50X
4223406/C 02/2019
NOTES: (continued)
6. This package is designed to be soldered to a thermal pads on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
7. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DTB0006A
X2SON - 0.35 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.25)
SYMM
(0.03) TYP
(0.28)
TYP
6
1
4X (0.4)
SYMM
5
2
(0.20) TYP
(0.80)
SOLDER MASK
EDGE, 2X
METAL UNDER
SOLDER MASK
TYP
(R0.05) TYP
3
4
(0.20)
TYP
(0.21)
(0.37)
4X (0.60)
SOLDER PASTE EXAMPLE
BASED ON 0.07 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:50X
4223406/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
YZP0005
DSBGA - 0.5 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.19
0.15
0.05 C
BALL TYP
0.5 TYP
C
SYMM
1
TYP
B
0.5
TYP
A
5X
0.015
0.25
0.21
C A B
1
2
SYMM
4219492/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YZP0005
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
5X ( 0.23)
2
1
A
(0.5) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
SOLDER MASK
OPENING
0.05 MAX
( 0.23)
SOLDER MASK
OPENING
0.05 MIN
( 0.23)
METAL
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4219492/A 05/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YZP0005
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
5X ( 0.25)
(R0.05) TYP
1
2
A
(0.5)
TYP
SYMM
B
C
METAL
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4219492/A 05/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
YFP0004
DSBGA - 0.5 mm max height
SCALE 10.000
DIE SIZE BALL GRID ARRAY
B
E
A
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.19
0.13
BALL TYP
0.05 C
0.4
TYP
B
D: Max = 0.79 mm, Min = 0.73 mm
SYMM
0.4
TYP
E: Max = 0.79 mm, Min = 0.73 mm
A
4X
0.015
0.25
0.21
C A B
1
2
SYMM
4223507/A 01/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFP0004
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
4X ( 0.23)
2
1
A
SYMM
(0.4) TYP
B
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:50X
( 0.23)
METAL
SOLDER MASK
OPENING
0.05 MAX
EXPOSED
METAL
0.05 MIN
METAL UNDER
SOLDER MASK
EXPOSED
METAL
( 0.23)
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4223507/A 01/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFP0004
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
4X ( 0.25)
1
2
A
SYMM
(0.4) TYP
B
METAL
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:50X
4223507/A 01/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
DSF0006A
X2SON - 0.4 mm max height
SCALE 10.000
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
B
A
PIN 1 INDEX AREA
1.05
0.95
0.4 MAX
C
SEATING PLANE
0.05 C
(0.11) TYP
SYMM
0.05
0.00
3
4
SYMM
2X
0.7
4X
0.35
6
1
6X
(0.1)
PIN 1 ID
6X
0.45
0.35
0.22
0.12
0.07
0.05
C B A
C
4220597/A 06/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MO-287, variation X2AAF.
www.ti.com
EXAMPLE BOARD LAYOUT
DSF0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.6)
(R0.05) TYP
1
6X (0.17)
6
SYMM
4X (0.35)
4
3
SYMM
(0.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:40X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220597/A 06/2017
NOTES: (continued)
4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DSF0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.6)
(R0.05) TYP
1
6
6X (0.17)
SYMM
4X (0.35)
4
3
SYMM
(0.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:40X
4220597/A 06/2017
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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