Texas Instruments | SN74AUC1G126 Single Bus Buffer Gate With Tri-state Output (Rev. L) | Datasheet | Texas Instruments SN74AUC1G126 Single Bus Buffer Gate With Tri-state Output (Rev. L) Datasheet

Texas Instruments SN74AUC1G126 Single Bus Buffer Gate With Tri-state Output (Rev. L) Datasheet
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SN74AUC1G126
SCES383L – MARCH 2002 – REVISED JANUARY 2018
SN74AUC1G126 Single Bus Buffer Gate With Tri-state Output
1 Features
3 Description
•
The SN74AUC1G126 bus buffer gate is operational
at 0.8-V to 2.7-V VCC, but is designed specifically for
1.65-V to 1.95-V VCC operation.
1
•
•
•
•
•
•
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Available in TI's NanoFree™ Package
Optimized for 1.8-V Operation and is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal Operation
Ioff Supports Partial Power Down Mode and Back
Drive Protection
Sub-1 V Operable
Maximum tpd of 2.5 ns at 1.8 V
Low Power Consumption, 10-µA Maximum ICC
±8-mA Output Drive at 1.8 V
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
AV Receiver
Audio Dock: Portable
Blu-ray™ Player and Home Theater
Embedded PC
MP3 Player/Recorder (Portable Audio)
Personal Digital Assistant (PDA)
Power: AC/DC Supply, Single Controller
Solid State Drive (SSD): Client and Enterprise
TV: LCD, Digital, and High-Definition (HD)
Tablet: Enterprise
Video Analytics: Server
Wireless Headset, Keyboard, and Mouse
The SN74AUC1G126 device is a single line driver
with a tri-state output. The output is disabled when
the output-enable (OE) input is low.
To ensure the high-impedance state during power up
or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
NanoFree™ package technology is a major
breakthrough in device packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, which prevents damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74AUC1G126DBV SOT-23 (5)
2.90 mm × 1.60 mm
SN74AUC1G126DCK SC70 (5)
2.00 mm × 1.25 mm
SN74AUC1G126YZP DSBGA (5)
1.388 mm × 0.888 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
1
OE
A
2
4
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
SN74AUC1G126
SCES383L – MARCH 2002 – REVISED JANUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
5
5
6
7
7
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics: CL = 15 pF ......................
Switching Characteristics: CL = 30 pF ......................
Operating Characteristics..........................................
Typical Characteristics.......................................... 8
Parameter Measurement Information ................ 10
Detailed Description ............................................ 12
9.1 Overview ................................................................. 12
9.2 Functional Block Diagram ....................................... 12
9.3 Feature Description................................................. 12
9.4 Device Functional Modes........................................ 13
10 Application and Implementation........................ 14
10.1 Application Information.......................................... 14
10.2 Typical Application ................................................ 14
11 Power Supply Recommendations ..................... 15
12 Layout................................................................... 16
12.1 Layout Guidelines ................................................. 16
12.2 Layout Example .................................................... 16
13 Device and Documentation Support ................. 17
13.1
13.2
13.3
13.4
13.5
13.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
17
14 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (June 2017) to Revision L
Page
•
Updated body size of YZP package. ..................................................................................................................................... 1
•
Added junction temperature to Absolute Maximum Ratings .................................................................................................. 4
•
Add Detailed Description, Application and Implementation, Power Supply Recommendations, and Layout sections ........ 12
Changes from Revision J (July 2007) to Revision K
Page
•
Deleted DRY package throughout data sheet........................................................................................................................ 1
•
Added Applications, Device Information table, ESD Ratings table, Thermal Information table, Feature Description
section, Device Functional Modes, Device and Documentation Support section, and Mechanical, Packaging, and
Orderable Information section ................................................................................................................................................ 1
•
Deleted Ordering Information table, see Mechanical, Packaging, and Orderable Information at the end of the data
sheet ...................................................................................................................................................................................... 1
2
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5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
OE
1
A
2
GND
3
5
4
DCK Package
5-Pin SC70
Top View
VCC
Y
OE
1
A
2
GND
3
5
VCC
4
Y
YZP Package
5-Pin DSBGA
Bottom View
1
2
C
GND
Y
B
A
A
OE
VCC
Not to scale
Pin Functions
PIN
NAME
DBV, DCK
YZP
I/O
DESCRIPTION
A
2
B1
I
GND
3
C1
—
Logic input
OE
1
A1
I
Output enable
VCC
5
A2
—
Positive supply
Y
4
C2
O
Output
Ground
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6 Specifications
6.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage, VCC
Input voltage, VI
(2)
MIN
MAX
UNIT
–0.5
3.6
V
–0.5
3.6
V
Voltage applied to any output in the high-impedance or power-off state, VO (2)
–0.5
3.6
V
Output voltage, VO (2)
–0.5
VCC + 0.5
V
Input clamp current, IIK
VI < 0
–50
mA
Output clamp current, IOK
VO < 0
–50
mA
Continuous output current, IO
±20
mA
Continuous current through VCC or GND
±100
mA
Junction temperature, TJ
150
°C
150
°C
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating
Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Machine Model (A115-A)
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
VCC = 0.8 V
VIH
High-level input voltage
MIN
MAX
UNIT
0.8
2.7
V
VCC
VCC = 1.1 V to 1.95 V
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
V
VCC = 0.8 V
VIL
Low-level input voltage
0
VCC = 1.1 V to 1.95 V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
V
VI
Input voltage
0
3.6
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
IOL
Low-level output current
Δt/Δv
TA
(1)
Input transition rise or fall rate
VCC = 0.8 V
–0.7
VCC = 1.1 V
–3
VCC = 1.4 V
–5
VCC = 1.65 V
–8
VCC = 2.3 V
–9
VCC = 0.8 V
0.7
VCC = 1.1 V
3
VCC = 1.4 V
5
VCC = 1.65 V
8
VCC = 2.3 V
9
VCC = 0.8 V to 1.6 V
20
VCC = 1.65 V to 1.95 V
10
VCC = 2.3 V to 2.7 V
3
Operating free-air temperature
–40
mA
mA
ns/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs application report.
6.4 Thermal Information
SN74AUC1G126
THERMAL METRIC (1)
RθJA
(1)
Junction-to-ambient thermal resistance
DBV (SOT-23)
DCK (SC70)
YZP (DSBGA)
5 PINS
5 PINS
5 PINS
206
252
132
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA, VCC = 0.8 V to 2.7 V
MIN
High-level output
voltage
UNIT
0.55
IOH = –3 mA, VCC = 1.1 V
0.8
IOH = –5 mA, VCC = 1.4 V
1
IOH = –8 mA, VCC = 1.65 V
1.2
IOH = –9 mA, VCC = 2.3 V
1.8
V
IOL = 100 µA, VCC = 0.8 V to 2.7 V
IOL = 0.7 mA, VCC = 0.8 V
MAX
VCC – 0.1
IOH = –0.7 mA, VCC = 0.8 V
VOH
TYP (1)
0.2
0.25
IOL = 3 mA, VCC = 1.1 V
0.3
IOL = 5 mA, VCC = 1.4 V
0.4
IOL = 8 mA, VCC = 1.65 V
0.45
IOL = 9 mA, VCC = 2.3 V
0.6
II
Inflection-point
current
A or OE input:
VI = VCC or GND, VCC = 0 to 2.7 V
±5
µA
Ioff
Off-state current
VI or VO = 2.7 V, VCC = 0
±10
µA
IOZ
High-impedance-state
VO = VCC or GND, VCC = 2.7 V
output current
±10
µA
ICC
Supply current
VI = VCC or GND, VCC = 0.8 V to 2.7 V IO = 0
10
µA
Ci
Input capacitance
VI = VCC or GND, VCC = 2.5 V
2.5
pF
Co
Output capacitance
VO = VCC or GND, VCC = 2.5 V
5.5
pF
VOL
(1)
6
Low-level output
voltage
V
All typical values are at TA = 25°C.
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6.6 Switching Characteristics: CL = 15 pF
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Table 2)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCC = 0.8 V
tpd
Propagation
delay time
A-to-Y
Enable time
0.8
VCC = 1.5 V ± 0.1 V
0.6
VCC = 1.8 V ± 0.15 V
0.6
VCC = 2.5 V ± 0.2 V
0.5
3.6
2.3
1
Disable time
ns
1.6
1.4
4.9
VCC = 1.2 V ± 0.1 V
0.7
OE-to-Y VCC = 1.5 V ± 0.1 V
0.7
VCC = 1.8 V ± 0.15 V
0.3
VCC = 2.5 V ± 0.2 V
0.3
3.8
2.5
0.9
ns
1.9
1.5
VCC = 0.8 V
tdis
UNIT
4.5
VCC = 1.2 V ± 0.1 V
VCC = 0.8 V
ten
MAX
4.9
VCC = 1.2 V ± 0.1 V
2.2
OE-to-Y VCC = 1.5 V ± 0.1 V
1.8
VCC = 1.8 V ± 0.15 V
1.6
VCC = 2.5 V ± 0.2 V
1
4.7
4.1
2.4
ns
3.5
2.7
6.7 Switching Characteristics: CL = 30 pF
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Table 2)
PARAMETER
TEST CONDITIONS
tpd
Propagation
delay time
A-to-Y
ten
Enable time
OE-to-Y
tdis
Disable time
OE-to-Y
MIN
TYP
MAX
VCC = 1.8 V ± 0.15 V
1
1.5
2.5
VCC = 2.5 V ± 0.2 V
0.9
VCC = 1.8 V ± 0.15 V
1.1
VCC = 2.5 V ± 0.2 V
0.9
VCC = 1.8 V ± 0.15 V
1.3
VCC = 2.5 V ± 0.2 V
1
UNIT
ns
1.7
1.6
2.5
ns
1.9
2.6
3.1
ns
2.1
6.8 Operating Characteristics
TA = 25°C
PARAMETER
TEST CONDITIONS
Inputs
disabled
Cpd
Power dissipation
capacitance
f = 10 MHz
Outputs
disabled
MIN
TYP
VCC = 0.8 V
14
VCC = 1.2 V
14
VCC = 1.5 V
14
VCC = 1.8 V
15
VCC = 2.5 V
16
VCC = 0.8 V
1.5
VCC = 1.2 V
1.5
VCC = 1.5 V
1.5
VCC = 1.8 V
2
VCC = 2.5 V
2.5
MAX
UNIT
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pF
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7 Typical Characteristics
0.07
0.22
Output Low Voltage (VOL) [V]
Output Low Voltage (VOL) [V]
0.2
0.06
0.05
0.04
0.03
0.02
0.01
0.18
0.16
0.14
0.12
0.1
0.08
0.06
0.04
0.02
0
0
0
0.1
0.2
0.3
0.4
0.5
Output Low Current (IOL) [mA]
0.6
0.7
0
1.5
2
2.5
3
3.5
Output Low Current (IOL) [mA]
4
4.5
5
1.5V
0.35
0.32
0.3
0.28
0.26
0.24
0.22
0.2
0.18
0.16
0.14
0.12
0.1
0.08
0.06
0.04
0.02
0
0.3
0.25
0.2
0.15
0.1
0.05
0
0
1
2
3
4
5
6
Output Low Current (IOL) [mA]
7
8
0
2
3
4
5
6
7
Output Low Current (IOL) [mA]
8
9
2.5V
Figure 4. Typical Output Low Voltage of 2.5 V (25°C)
0.85
1.55
1.525
Output High Voltage (V OH) [V]
0.825
0.8
0.775
0.75
0.725
0.7
0.675
-0.7
1
1.8V
Figure 3. Typical Output Low Voltage of 1.8 V (25°C)
Output High Voltage (V OH) [V]
1
Figure 2. Typical Output Low Voltage of 1.5 V (25°C)
Output Low Voltage (VOL) [V]
Output Low Voltage (VOL) [V]
Figure 1. Typical Output Low Voltage of 0.8 V (25°C)
1.5
1.475
1.45
1.425
1.4
1.375
1.35
1.325
-0.6
-0.5
-0.4
-0.3
-0.2
Output High Current (IOH) [mA]
-0.1
0
1.3
-5
-4.5
0.8V
Figure 5. Typical Output High Voltage of 0.8 V (25°C)
8
0.5
0.8V
-4
-3.5 -3 -2.5 -2 -1.5 -1
Output High Current (IOH) [mA]
-0.5
0
1.5V
Figure 6. Typical Output High Voltage of 1.5 V (25°C)
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2.55
1.8
2.5
Output High Voltage (VOH) [V]
Output High Voltage (VOH) [V]
Typical Characteristics (continued)
1.85
1.75
1.7
1.65
1.6
1.55
1.5
-8
-7
-6
-5
-4
-3
-2
Output High Current (IOH) [mA]
-1
0
2.45
2.4
2.35
2.3
2.25
-9
-8
1.8V
Figure 7. Typical Output High Voltage of 1.8 V (25°C)
-7
-6
-5
-4
-3
-2
Output High Current (IOH) [mA]
-1
0
2.5V
Figure 8. Typical Output High Voltage of 2.5 V (25°C)
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8 Parameter Measurement Information
Unless otherwise noted, all input pulses are supplied by generators that have the following characteristics:
• PRR ≤ 10 MHz
• ZO = 50 Ω
2 X VCCO
S1
RL
Open
Output Pin
Under Test
GND
CL(1)
(1)
RL
CL includes probe and jig capacitance.
Figure 9. Load Circuit
Table 1. Loading Conditions for Parameter
TEST
S1
tPLH
(1)
(1)
Open
tPLZ
(2)
(3)
2 × VCC
tPHZ
(2)
(3)
GND
, tPHL
, tPZL
, tPZH
Table 2. Loading Conditions for VCC
VCC
CL
RL
VΔ
0.8 V
15 pF
2 kΩ
0.1 V
1.2 V ± 0.1 V
15 pF
2 kΩ
0.1 V
1.5 V ± 0.1 V
15 pF
2 kΩ
0.1 V
1.8 V ± 0.15 V
15 pF
2 kΩ
0.15 V
2.5 V ± 0.2 V
15 pF
2 kΩ
0.15 V
1.8 V ± 0.15 V
30 pF
1 kΩ
0.15 V
2.5 V ± 0.2 V
30 pF
500 kΩ
0.15 V
tw
VCC
Input
VCC / 2
VCC / 2
0V
Figure 10. Voltage Waveforms: Pulse Duration
10
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VCC
VCC / 2
Input
VCC / 2
0V
tPHL
tPLH
VOH
VCC / 2
Output
VCC / 2
VOL
tPLH
tPHL
VOH
VCC / 2
Output
VCC / 2
VOL
(1)
All outputs are measured one at a time, with one transition per measurement.
Figure 11. Voltage Waveforms: Propagation Delay Times, Inverting and Noninverting Outputs
VCC
VCC / 2
Timing Input
0V
tsu
th
VCC
Data Input
VCC / 2
VCC / 2
0V
Figure 12. Voltage Waveforms: Setup and Hold Times
VCC
Output
Control
VCC / 2
VCC / 2
0V
tPLZ
tPZL
VCC
(1)
Output Waveform 1
S1 at 2 x VCC
VCC / 2
VOL + V
tPHZ
tPZH
Output Waveform 2(2)
S1 at GND
VOL
VOH
VOH
VCC / 2
0V
(1)
Waveform 1 is for an output with internal conditions such as the output is low, except when disabled by the output
control.
(2)
Waveform 2 is for an output with internal conditions such as the output is high, except when disabled by the output
control.
(3)
All outputs are measured one at a time, with one transition per measurement.
Figure 13. Voltage Waveforms: Enable and Disable Times, Low- and High-Level Enabling
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9 Detailed Description
9.1 Overview
The SN74AUC1G126 device contains one buffer gate device with output enable control, and performs the
Boolean function Y = A. This device is specified for partial-power-down applications using Ioff. The Ioff circuitry
disables the outputs when the device is powered down. This inhibits current backflow, preventing damage to the
device.
To ensure the high-impedance state during power up or power down, OE must be tied to GND through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
9.2 Functional Block Diagram
1
OE
A
2
4
Y
Figure 14. Logic Diagram (Positive Logic)
9.3 Feature Description
9.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device may
create fast edges into light loads, so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined the in Absolute Maximum Ratings must be followed at all times.
9.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in Absolute Maximum Ratings, and the maximum input leakage current, given in Electrical
Characteristics, using Ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating
Conditions to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a
device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.
12
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Feature Description (continued)
9.3.3 Negative Clamping Diodes
The inputs and outputs to this device have negative clamping diodes as shown in Figure 15.
CAUTION
Voltages beyond the values specified in Absolute Maximum Ratings table can cause
damage to the device. The input negative-voltage and output voltage ratings may be
exceeded if the input and output clamp-current ratings are observed.
Device
VCC
Logic
Input
Output
-IIK
-IOK
GND
Figure 15. Electrical Placement of Clamping Diodes for Each Input and Output
9.3.4 Special Features
9.3.4.1 Partial Power Down (Ioff)
The inputs and outputs for this device enter a high-impedance state when the supply voltage is 0 V. The
maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical
Characteristics.
9.3.4.2 Overvoltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as the input signals remain below the
maximum input voltage value specified in Recommended Operating Conditions.
9.3.4.3 Output Enable
This device has an output enable (OE) pin that functions according to Table 3. When the outputs of the device
are disabled, the outputs are placed into a high impedance state where the output will neither source nor sink
current. High-impedance outputs are also commonly referred to as three-state or tri-state outputs. The maximum
leakage for the output in this state is defined by IOZ in the Electrical Characteristics table.
9.4 Device Functional Modes
Table 3 lists the functional modes of the SN74AUC1G126 device.
Table 3. Function Table
INPUTS
OE
A
OUTPUT
Y
H
H
H
H
L
L
L
X
Z
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Product Folder Links: SN74AUC1G126
13
SN74AUC1G126
SCES383L – MARCH 2002 – REVISED JANUARY 2018
www.ti.com
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN74AUC1G126 device is an output enabled CMOS buffer that can be used in LED indicator applications
that require less than 9 mA. The device can produce up to 9 mA of drive current at 2.5 V. The inputs to the
device are also overvoltage tolerant up to 3.6 V, allowing the inputs to translate down to any valid VCC.
10.2 Typical Application
VCC
Override
MCU Input
OE
A
VCC
Y
Output
LED
Indicator
Figure 16. Application Schematic with MCU driving an LED Indicator
10.2.1 Design Requirements
This device uses CMOS technology, and has a balanced output drive. The output drive strength of this device
creates fast edges into light loads, so routing and load conditions should be considered to prevent ringing.
NOTE
Take care of the output drive to avoid bus contention, because the output can drive
currents that exceed maximum limits.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– Rise time and fall time specifications (Δt/ΔV) are shown in the Recommended Operating Conditions table.
– Specified high (VIH) and low voltage (VIL) levels are shown in the Recommended Operating Conditions
table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI maximum) in the Recommended
Operating Conditions table at any valid VCC.
2. Recommended Output Conditions:
– Load currents must not exceed (IO max) per output and must not exceed (continuous current through VCC
or GND) total current for the part. These limits are located in the Absolute Maximum Ratings table.
– Outputs should not be pulled above VCC.
14
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SN74AUC1G126
www.ti.com
SCES383L – MARCH 2002 – REVISED JANUARY 2018
Typical Application (continued)
10.2.3 Application Curve
Input
Output
Figure 17. Example Oscilloscope Waveform
11 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the
Recommended Operating Conditions table.
The VCC pin must have a good bypass capacitor to prevent power disturbance. A 0.1-µF capacitor is
recommended, and it is ok to parallel multiple bypass caps to reject different frequencies of noise. 0.1-µF and
1-µF capacitors are commonly used in parallel. The bypass capacitor must be installed as close as possible to
the power pin for best results.
Submit Documentation Feedback
Copyright © 2002–2018, Texas Instruments Incorporated
Product Folder Links: SN74AUC1G126
15
SN74AUC1G126
SCES383L – MARCH 2002 – REVISED JANUARY 2018
www.ti.com
12 Layout
12.1 Layout Guidelines
Even low data rate digital signals can contain high-frequency signal components due to fast edge rates. When a
printed-circuit board (PCB) trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs
primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414
times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance
and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore
some traces must turn corners. Figure 18 shows progressively better techniques of rounding corners. Only the
last example (BEST) maintains constant trace width and minimizes reflections.
12.2 Layout Example
WORST
BETTER
BEST
Figure 18. Trace Example
16
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Copyright © 2002–2018, Texas Instruments Incorporated
Product Folder Links: SN74AUC1G126
SN74AUC1G126
www.ti.com
SCES383L – MARCH 2002 – REVISED JANUARY 2018
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
is a trademark of ~Blue-ray Disc Association.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2002–2018, Texas Instruments Incorporated
Product Folder Links: SN74AUC1G126
17
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jan-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
74AUC1G126DCKRG4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
UNR
SN74AUC1G126DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
U26R
SN74AUC1G126DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
UNR
SN74AUC1G126YZPR
ACTIVE
DSBGA
YZP
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(UN, UNN)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jan-2018
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
SOT-23
DBV
5
3000
180.0
8.4
3.23
SN74AUC1G126DCKR
SC70
DCK
5
3000
180.0
8.4
SN74AUC1G126YZPR
DSBGA
YZP
5
3000
178.0
9.2
SN74AUC1G126DBVR
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.17
1.37
4.0
8.0
Q3
2.47
2.3
1.25
4.0
8.0
Q3
1.02
1.52
0.63
4.0
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AUC1G126DBVR
SOT-23
DBV
5
3000
202.0
201.0
28.0
SN74AUC1G126DCKR
SC70
DCK
5
3000
202.0
201.0
28.0
SN74AUC1G126YZPR
DSBGA
YZP
5
3000
220.0
220.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
YZP0005
DSBGA - 0.5 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.19
0.15
0.05 C
BALL TYP
0.5 TYP
C
SYMM
1
TYP
D: Max = 1.418 mm, Min =1.358 mm
B
0.5
TYP
E: Max = 0.918 mm, Min =0.858 mm
A
5X
0.015
0.25
0.21
C A B
1
2
SYMM
4219492/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YZP0005
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
5X ( 0.23)
2
1
A
(0.5) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
SOLDER MASK
OPENING
0.05 MAX
( 0.23)
SOLDER MASK
OPENING
0.05 MIN
( 0.23)
METAL
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4219492/A 05/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YZP0005
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
5X ( 0.25)
(R0.05) TYP
1
2
A
(0.5)
TYP
SYMM
B
C
METAL
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4219492/A 05/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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