Texas Instruments | SN74LVC1G38 Single 2-Input NAND Gate With Open-Drain Output (Rev. F) | Datasheet | Texas Instruments SN74LVC1G38 Single 2-Input NAND Gate With Open-Drain Output (Rev. F) Datasheet

Texas Instruments SN74LVC1G38 Single 2-Input NAND Gate With Open-Drain Output (Rev. F) Datasheet
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SN74LVC1G38
SCES538F – JANUARY 2004 – REVISED OCTOBER 2017
SN74LVC1G38 Single 2-Input NAND Gate With Open-Drain Output
1 Features
3 Description
•
The SN74LVC1G38 device is designed for 1.65-V to
5.5-V VCC operation.
1
•
•
•
•
•
•
•
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Supports Down Translation to VCC
Maximum tpd of 4.5 ns at 3.3 V
Low Power Consumption, 10-µA Maximum ICC
±24-mA Output Drive at 3.3 V
Ioff Supports Partial-Power-Down Mode and BackDrive Protection
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
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AV Receivers
Blu-ray Players and Home Theaters
DVD Recorders and Players
Desktop or Notebook PCs
Digital Radio or Internet Radio Players
Digital Video Cameras (DVC)
Embedded PCs
GPS: Personal Navigation Devices
Mobile Internet Devices
Network Projector Front-Ends
Portable Media Players
Pro Audio Mixers
Smoke Detectors
Solid State Drive (SSD): Enterprise
High-Definition (HDTV)
Tablets: Enterprise
Audio Docks: Portable
DLP Front Projection Systems
DVR and DVS
Digital Picture Frame (DPF)
Digital Still Cameras
This device is a single two-input NAND buffer gate
with open-drain output. It performs the Boolean
function Y = A × B or Y = A + B in positive logic.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs when the device is powered down. This
inhibits current backflow into the device which
prevents damage to the device.
NanoStar™ and NanoFree™ package technology is
a major breakthrough in IC packaging concepts,
using the die as the package.
Device Information(1)
DEVICE NAME
PACKAGE
BODY SIZE (NOM)
SN74LVC1G38DBV
SOT-23 (5)
2.90 mm × 1.60 mm
SN74LVC1G38DCK
SC70 (5)
2.00 mm × 1.25 mm
SN74LVC1G38DRY
SON (6)
1.45 mm × 1.00 mm
SN74LVC1G38DSF
SON (6)
1.00 mm × 1.00 mm
SN74LVC1G38YZP
DSBGA (5)
0.89 mm × 1.39 mm
SN74LVC1G38DPW
X2SON (5)
0.80 mm × 0.80 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
A
1
4
B
Y
2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G38
SCES538F – JANUARY 2004 – REVISED OCTOBER 2017
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
5
5
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, CL = 15 pF ......................
Switching Characteristics, CL = 30 pF or 50 pF,
–40°C to +85°C..........................................................
6.8 Switching Characteristics, CL = 30 pF or 50 pF,
–40°C to +125°C........................................................
6.9 Operating Characteristics..........................................
6.10 Typical Characteristics ............................................
7
8
6
7
7
7
Parameter Measurement Information .................. 8
Detailed Description ............................................ 10
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
11
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
14
14
13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (August 2017) to Revision F
•
Page
Added values for DPW (X2SON) package in Thermal Information table. ............................................................................. 5
Changes from Revision D (December 2013) to Revision E
Page
•
Added DPW (X2SON) package.............................................................................................................................................. 1
•
Added Applications, Device Information table, Pin Configuration and Functions section, ESD Ratings table, Thermal
Information table, Typical Characteristics, Detailed Description section, Application and Implementation section,
Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section .................................................................................................................................................................................... 1
•
Added Maximum junction temperature, TJ ............................................................................................................................. 4
•
Changed values in the Thermal Information table to align with JEDEC standards................................................................ 5
Changes from Revision C (March 2011) to Revision D
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Updated Ioff in Features. ......................................................................................................................................................... 1
•
Added ESD warning. .............................................................................................................................................................. 1
•
Updated operating temperature range. .................................................................................................................................. 5
2
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SCES538F – JANUARY 2004 – REVISED OCTOBER 2017
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
A
1
B
2
VCC
5
3
GND
DCK Package
5-Pin SC70
Top View
A
1
B
2
GND
3
5
VCC
4
Y
Y
4
DRY Package
6-Pin SON
Top View
A
1
6
V CC
B
2
5
NC
GND
3
4
Y
DSF Package
6-Pin SON
Top View
A
1
6
VCC
B
GND
2
5
3
4
NC
Y
NC – No internal connection.
See mechanical drawings for dimensions
YZP Package
5-Pin DSBGA
Bottom View
C
1
2
GND
Y
DPW Package
5-Pin X2SON
Top View
GND
B
B
A
A
A
B
VCC
Y
VCC
Not to scale
Pin Functions
PIN
DBV,
DCK,
DPW
DRY,
DSF
YZP
A
1
1, 5
A1
I
Logic Input A
B
2
2
B1
I
Logic Input B
GND
3
3
C1
—
Ground
NC
—
5
—
—
No Internal Connection
Y
4
4
C2
O
Output Y
VCC
5
6
A2
—
Positive Supply
NAME
I/O
DESCRIPTION
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
6.5
V
(2)
–0.5
6.5
V
–0.5
6.5
V
VI
Input voltage
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
150
°C
150
°C
TJ
Maximum junction temperature
Tstg
Storage temperature
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
1000
Machine Model (MM), A115-A
200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
MIN
MAX
Operating
1.65
5.5
Data retention only
1.5
VCC = 1.65 V to 1.95 V
VIH
1.7
VCC = 3 V to 3.6 V
0.7 × VCC
VCC = 1.65 V to 1.95 V
Low-level input voltage
V
2
VCC = 4.5 V to 5.5 V
VIL
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
High-level input voltage
UNIT
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VCC = 4.5 V to 5.5 V
V
0.3 × VCC
VI
Input voltage
0
5.5
V
VO
Output voltage
0
5.5
V
IOL
Low-level output current
Δt/Δv
TA
(1)
VCC = 1.65 V
4
VCC = 2.3 V
8
16
VCC = 3 V
Input transition rise and fall rate
mA
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
5
Operating free-air temperature
–40
125
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs.
6.4 Thermal Information
SN74LVC1G38
THERMAL METRIC
(1)
DBV
(SOT-23)
DCK
(SC70)
DRY
(SON)
DSF
(SON)
YZP
(DSBGA)
DPW
(X2SON)
UNIT
5 PINS
5 PINS
6 PINS
6 PINS
5 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
247.2
276.1
366.9
406.2
146.2
511.0
°C/W
RθJC(top)
Junction-to-case (top) thermal
resistance
154.5
178.9
253.8
201.0
1.4
241.9
°C/W
RθJB
Junction-to-board thermal resistance
86.8
70.9
227.5
256.9
39.3
374.2
°C/W
ψJT
Junction-to-top characterization
parameter
58.0
47.0
75.8
35.2
0.7
45.0
°C/W
ψJB
Junction-to-board characterization
parameter
86.4
69.3
227.7
256.6
39.8
373.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
N/A
N/A
N/A
N/A
N/A
168.0
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = –40°C to +85°C
IOL = 100 µA
TA = –40°C to +1255°C
TA = –40°C to +85°C
IOL = 4 mA
TA = –40°C to +1255°C
TA = –40°C to +85°C
IOL = 8 mA
TA = –40°C to +1255°C
VOL
TYP (1)
MAX
1.65 V to
5.5 V
0.1
1.65 V
0.45
2.3 V
0.3
V
3V
TA = –40°C to +85°C
0.55
TA = –40°C to +1255°C
TA = –40°C to +85°C
IOL = 32 mA
4.5 V
TA = –40°C to +1255°C
TA = –40°C to +85°C
VI = 5.5 V or GND
UNIT
0.4
TA = –40°C to +1255°C
IOL = 24 mA
A or B inputs
MIN
TA = –40°C to +85°C
IOL = 16 mA
II
VCC
TA = –40°C to +1255°C
TA = –40°C to +85°C
0.55
1.65 V to
5.5 V
±1
µA
0
±10
µA
1.65 V to
5.5 V
10
µA
3 V to 5.5 V
500
µA
Ioff
VI or VO = 5.5 V
ICC
VI = 5.5 V or GND, IO = 0
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
3.3 V
3.5
pF
Co
VO = VCC or GND
3.3 V
4.5
pF
(1)
TA = –40°C to +1255°C
TA = –40°C to +85°C
TA = –40°C to +1255°C
TA = –40°C to +85°C
TA = –40°C to +1255°C
All typical values are at VCC = 3.3 V, TA = 25°C.
6.6 Switching Characteristics, CL = 15 pF
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 2)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
TEST CONDITIONS
TA = –40°C to +85°C
MIN
MAX
VCC = 1.8 V ± 0.15 V
2.9
7.4
VCC = 2.5 V ± 0.2 V
1.7
3.8
VCC = 3.3 V ± 0.3 V
1.5
4.9
VCC = 5 V ± 0.5 V
0.9
2.4
UNIT
ns
6.7 Switching Characteristics, CL = 30 pF or 50 pF, –40°C to +85°C
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
6
FROM
(INPUT)
A or B
TO
(OUTPUT)
Y
TEST CONDITIONS
TA = –40°C to +85°C
MIN
MAX
VCC = 1.8 V ± 0.15 V
2.8
10
VCC = 2.5 V ± 0.2 V
1.6
6
VCC = 3.3 V ± 0.3 V
1.4
4.5
VCC = 5 V ± 0.5 V
1
3.9
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UNIT
ns
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6.8 Switching Characteristics, CL = 30 pF or 50 pF, –40°C to +125°C
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
FROM
(INPUT)
A or B
TO
(OUTPUT)
TEST CONDITIONS
Y
MIN
MAX
VCC = 1.8 V ± 0.15 V
2.8
11
VCC = 2.5 V ± 0.2 V
1.6
6.5
VCC = 3.3 V ± 0.3 V
1.4
5
VCC = 5 V ± 0.5 V
1
4.4
TA = –40°C to +125°C
UNIT
ns
6.9 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
f = 10 MHz
TYP
VCC = 1.8 V
3
VCC = 2.5 V
3
VCC = 3.3 V
4
VCC = 5 V
6
UNIT
pF
6.10 Typical Characteristics
0.35
0.3
VOL (V)
0.25
0.2
0.15
0.1
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
0.05
0
0
5
10
15
20
IOL (mA)
25
30
35
VOL_
Figure 1. Typical IOL vs. VOL (TA = 25°C)
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7 Parameter Measurement Information
(Open Drain)
VLOAD
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
TEST
S1
tPZL (see Notes E and F)
tPLZ (see Notes E and G)
tPHZ/tPZH
VLOAD
VLOAD
VLOAD
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
15 pF
15 pF
15 pF
15 pF
1 MΩ
1 MΩ
1 MΩ
1 MΩ
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators have the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. Because this device has open-drain outputs, tPLZ and tPZL are the same as tPD.
F. tPZL is measured at VM.
G. tPLZ is measured at VOL + V∆.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
8
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Parameter Measurement Information (continued)
(Open Drain)
VLOAD
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
TEST
S1
tPZL (see Notes E and F)
tPLZ (see Notes E and G)
tPHZ/tPZH
VLOAD
VLOAD
VLOAD
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators have the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. Because this device has open-drain outputs, tPLZ and tPZL are the same as tPD.
F. tPZL is measured at VM.
G. tPLZ is measured at VOL + V∆.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74LVC1G38 device is designed for 1.65-V to 5.5-V VCC operation.
This device is a single two-input NAND buffer gate with open-drain output.
It performs the Boolean function Y = A × B or Y = A + B in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs
when the device is powered down. This inhibits current backflow into the device which prevents damage to the
device.
8.2 Functional Block Diagram
A
1
4
B
Y
2
Figure 4. Logic Diagram (Positive Logic)
8.3 Feature Description
8.3.1 High-Drive Open-Drain Output
The open-drain output allows the device to sink current when the output is LOW and maintains a high impedance
state when the output is HIGH. The high drive capability of this device creates fast edges into light loads so
routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are
capable of driving larger currents than the device can sustain without being damaged. It is important for the
power output of the device to be limited to avoid thermal runaway and damage due to over-current. The electrical
and thermal limits defined the in the Absolute Maximum Ratings must be followed at all times.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating
Conditions to avoid excessive currents and oscillations. If a slow or noisy input signal is required, a device with a
Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.
10
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SCES538F – JANUARY 2004 – REVISED OCTOBER 2017
Feature Description (continued)
8.3.3 Clamp Diodes
The inputs and outputs to this device have negative clamping diodes.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
VCC
Device
Logic
Input
-IIK
Output
-IOK
GND
Figure 5. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.4 Partial Power Down (Ioff)
The inputs and outputs for this device enter a high impedance state when the supply voltage is 0 V. The
maximum leakage into or out of any input or output pin on the device is specified by Ioff in the .
8.3.5 Over-Voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Absolute Maximum Ratings.
8.3.6 Up Translation and Down Translation Capable Outputs
Outputs of this device can be driven above the supply voltage so long as they remain below the maximum output
voltage value specified in the Absolute Maximum Ratings. When the device is not actively driving LOW, the
output is in the high impedance state. If a pull-up resistor is connected from the output to a power supply (of any
valid value), the output will be driven by this supply, and therefore can have a voltage that is either higher or
lower than the VCC supply of the device. An application of this device performing up-translation is depicted in
Application and Implementation, where additional design details are provided.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74LVC1G38 device.
Table 1. Function Table
INPUTS
A
B
OUTPUT
Y
L
L
Hi-Z
L
H
Hi-Z
H
L
Hi-Z
H
H
L
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SCES538F – JANUARY 2004 – REVISED OCTOBER 2017
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Open-drain devices are intrinsically capable of voltage translation. In this application, a 1.8-V logic signal is
inverted and up-translated to 5 V at the output when the EN signal input is driven high by a 3.3-V signal. The
output is held at 5 V in this scenario when the output of the device is in the high impedance state.
9.2 Typical Application
V1
A
EN
V2
R
Y
Figure 6. Gated Voltage Translating Inverter Schematic Using SN74LVC1G38
9.2.1 Design Requirements
The supply voltage at V1 must be set to provide input thresholds for the signals A and EN. This device uses
CMOS technology and has an open-drain output. Outputs of open-drain devices can be tied directly together to
produce a wired-OR configuration. This device has high current drive that will create fast edges into light loads
so routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC.
2. Recommended Output Conditions
– Load currents should not exceed (IO max). These limits are located in the Absolute Maximum Ratings
table.
– Outputs can be pulled above VCC for up-translation applications as long as the maximum output voltage
in the Absolute Maximum Ratings table is observed.
9.2.3 Application Curve
A
EN
Y
Figure 7. Application Timing Diagram
12
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SCES538F – JANUARY 2004 – REVISED OCTOBER 2017
10 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
The VCC pin should have a good bypass capacitor to prevent power disturbance. It is ok to parallel multiple
bypass caps to reject different frequencies of noise. 0.1-µF and 1-µF capacitors are commonly used in parallel.
The bypass capacitor should be installed as close to the power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 8 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they are tied to GND or
VCC, whichever makes more sense or is more convenient.
Even low data rate digital signals can have high frequency signal components due to fast edge rates. When a
printed-circuit board (PCB) trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs
primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414
times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance
and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore
some traces must turn corners. Figure 9 shows progressively better techniques of rounding corners. Only the last
example (BEST) maintains constant trace width and minimizes reflections.
11.2 Layout Example
VCC
Input
Unused Input
Output
Output
Unused Input
Input
Figure 8. Proper multi-gate input termination diagram
BETTER
BEST
2W
WORST
1W min.
W
Figure 9. Trace Example
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SCES538F – JANUARY 2004 – REVISED OCTOBER 2017
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Designing and Manufacturing with TI's X2SON Packages Application Note
• Texas Instruments, How to Select Little Logic Application Note
• Texas Instruments, Implications of Slow or Floating CMOS Inputs Application Note.
• Texas Instruments, Understanding and Interpreting Standard-Logic Data Sheets Application Note
• Texas Instruments, Introduction to Logic Application Note
• Texas Instruments, Signal Switch Data Book User's Guide
• Texas Instruments, LVC and LV Low-Voltage CMOS Logic Data Book User's Guide
• Texas Instruments, Low-Voltage Logic (LVC) Designer's Guide User's Guide
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
NanoStar, NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
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Product Folder Links: SN74LVC1G38
PACKAGE OPTION ADDENDUM
www.ti.com
4-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LVC1G38DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(C385, C38F, C38J,
C38R)
(C38H, C38P, C38S)
SN74LVC1G38DBVRE4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C385
C38S
SN74LVC1G38DBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C385
C38S
SN74LVC1G38DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(C385, C38J, C38R)
SN74LVC1G38DBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C385
C38S
SN74LVC1G38DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(D75, D7F, D7J, D7
R)
(D7H, D7P, D7S)
SN74LVC1G38DCKRG4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D75
D7S
SN74LVC1G38DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(D75, D7J, D7R)
(D7H, D7S)
SN74LVC1G38DPWR
ACTIVE
X2SON
DPW
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
BP
SN74LVC1G38DRYR
ACTIVE
SON
DRY
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D7
SN74LVC1G38DSFR
ACTIVE
SON
DSF
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
D7
SN74LVC1G38YZPR
ACTIVE
DSBGA
YZP
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
D7N
(C38H, C38S)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Apr-2019
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jan-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
SN74LVC1G38DBVR
SOT-23
DBV
5
3000
180.0
8.4
SN74LVC1G38DBVR
SOT-23
DBV
5
3000
178.0
SN74LVC1G38DBVR
SOT-23
DBV
5
3000
178.0
SN74LVC1G38DBVRG4
SOT-23
DBV
5
3000
SN74LVC1G38DBVT
SOT-23
DBV
5
W
Pin1
(mm) Quadrant
3.23
3.17
1.37
4.0
8.0
Q3
9.2
3.3
3.23
1.55
4.0
8.0
Q3
9.0
3.3
3.2
1.4
4.0
8.0
Q3
178.0
9.2
3.3
3.23
1.55
4.0
8.0
Q3
250
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
SN74LVC1G38DBVT
SOT-23
DBV
5
250
178.0
9.2
3.3
3.23
1.55
4.0
8.0
Q3
SN74LVC1G38DBVTG4
SOT-23
DBV
5
250
178.0
9.2
3.3
3.23
1.55
4.0
8.0
Q3
SN74LVC1G38DCKR
SC70
DCK
5
3000
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74LVC1G38DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
SN74LVC1G38DCKRG4
SC70
DCK
5
3000
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74LVC1G38DCKT
SC70
DCK
5
250
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74LVC1G38DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
SN74LVC1G38DPWR
X2SON
DPW
5
3000
178.0
8.4
0.91
0.91
0.5
2.0
8.0
Q3
SN74LVC1G38DRYR
SON
DRY
6
5000
180.0
9.5
1.15
1.6
0.75
4.0
8.0
Q1
SN74LVC1G38DSFR
SON
DSF
6
5000
180.0
9.5
1.16
1.16
0.5
4.0
8.0
Q2
SN74LVC1G38YZPR
DSBGA
YZP
5
3000
178.0
9.2
1.02
1.52
0.63
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jan-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC1G38DBVR
SOT-23
DBV
5
3000
202.0
201.0
28.0
SN74LVC1G38DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
SN74LVC1G38DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
SN74LVC1G38DBVRG4
SOT-23
DBV
5
3000
180.0
180.0
18.0
SN74LVC1G38DBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
SN74LVC1G38DBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
SN74LVC1G38DBVTG4
SOT-23
DBV
5
250
180.0
180.0
18.0
SN74LVC1G38DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
SN74LVC1G38DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
SN74LVC1G38DCKRG4
SC70
DCK
5
3000
180.0
180.0
18.0
SN74LVC1G38DCKT
SC70
DCK
5
250
180.0
180.0
18.0
SN74LVC1G38DCKT
SC70
DCK
5
250
180.0
180.0
18.0
SN74LVC1G38DPWR
X2SON
DPW
5
3000
205.0
200.0
33.0
SN74LVC1G38DRYR
SON
DRY
6
5000
184.0
184.0
19.0
SN74LVC1G38DSFR
SON
DSF
6
5000
184.0
184.0
19.0
SN74LVC1G38YZPR
DSBGA
YZP
5
3000
220.0
220.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DSF0006A
X2SON - 0.4 mm max height
SCALE 10.000
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
B
A
PIN 1 INDEX AREA
1.05
0.95
0.4 MAX
C
SEATING PLANE
0.05 C
(0.11) TYP
SYMM
0.05
0.00
3
4
SYMM
2X
0.7
4X
0.35
6
1
6X
(0.1)
PIN 1 ID
6X
0.45
0.35
0.22
0.12
0.07
0.05
C B A
C
4220597/A 06/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MO-287, variation X2AAF.
www.ti.com
EXAMPLE BOARD LAYOUT
DSF0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.6)
(R0.05) TYP
1
6X (0.17)
6
SYMM
4X (0.35)
4
3
SYMM
(0.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:40X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220597/A 06/2017
NOTES: (continued)
4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DSF0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.6)
(R0.05) TYP
1
6
6X (0.17)
SYMM
4X (0.35)
4
3
SYMM
(0.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:40X
4220597/A 06/2017
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
GENERIC PACKAGE VIEW
DRY 6
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4207181/G
PACKAGE OUTLINE
DRY0006A
USON - 0.6 mm max height
SCALE 8.500
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
B
A
PIN 1 INDEX AREA
1.5
1.4
C
0.6 MAX
SEATING PLANE
0.05
0.00
0.08 C
3X 0.6
SYMM
(0.127) TYP
(0.05) TYP
3
4
4X
0.5
SYMM
2X
1
1
6
6X
0.4
0.3
PIN 1 ID
(OPTIONAL)
5X
0.25
0.15
0.1
0.05
0.35
0.25
C A B
C
4222894/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DRY0006A
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
6
1
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
LAND PATTERN EXAMPLE
1:1 RATIO WITH PKG SOLDER PADS
EXPOSED METAL SHOWN
SCALE:40X
0.05 MAX
ALL AROUND
EXPOSED
METAL
0.05 MIN
ALL AROUND
EXPOSED
METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222894/A 01/2018
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DRY0006A
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
1
6
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X
4222894/A 01/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DPW0005A
X2SON - 0.4 mm max height
SCALE 12.000
PLASTIC SMALL OUTLINE - NO LEAD
0.85
0.75
B
A
0.85
0.75
PIN 1 INDEX AREA
0.4 MAX
C
SEATING PLANE
NOTE 3
(0.1)
0.05
0.00
(0.25)
4X (0.05)
0.25 0.1
2
4
2X
0.48
3
NOTE 3
2X (0.26)
5
1
4X
0.27
0.17
(0.06)
3X
0.27
0.17
0.1 C A B
0.05 C
0.32
0.23
4223102/B 09/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The size and shape of this feature may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.78)
SYMM
4X (0.42)
( 0.1)
VIA
0.05 MIN
ALL AROUND
TYP
1
5
4X (0.22)
SYMM
4X (0.26)
(0.48)
3
2
4
(R0.05) TYP
( 0.25)
4X (0.06)
(0.21) TYP
EXPOSED METAL
CLEARANCE
SOLDER MASK
OPENING, TYP
METAL UNDER
SOLDER MASK
TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:60X
4223102/B 09/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.42)
4X (0.22)
4X (0.06)
5
1
( 0.24)
4X (0.26)
SYMM
(0.21)
TYP
SOLDER MASK
EDGE
3
2
(R0.05) TYP
(0.48)
4
SYMM
(0.78)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
92% PRINTED SOLDER COVERAGE BY AREA
SCALE:100X
4223102/B 09/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
YZP0005
DSBGA - 0.5 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.19
0.15
0.05 C
BALL TYP
0.5 TYP
C
SYMM
1
TYP
D: Max = 1.418 mm, Min =1.358 mm
B
0.5
TYP
E: Max = 0.918 mm, Min =0.858 mm
A
5X
0.015
0.25
0.21
C A B
1
2
SYMM
4219492/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YZP0005
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
5X ( 0.23)
2
1
A
(0.5) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
SOLDER MASK
OPENING
0.05 MAX
( 0.23)
SOLDER MASK
OPENING
0.05 MIN
( 0.23)
METAL
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4219492/A 05/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YZP0005
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
5X ( 0.25)
(R0.05) TYP
1
2
A
(0.5)
TYP
SYMM
B
C
METAL
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4219492/A 05/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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