Texas Instruments | SN74AUP1G80 Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop (Rev. F) | Datasheet | Texas Instruments SN74AUP1G80 Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop (Rev. F) Datasheet

Texas Instruments SN74AUP1G80 Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop (Rev. F) Datasheet
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SN74AUP1G80
SCES593F – JULY 2004 – REVISED JULY 2017
SN74AUP1G80 Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop
1 Features
3 Description
•
The AUP family is TI's premier solution to the
industry's low-power needs in battery-powered
portable applications. This family assures a low staticand dynamic-power consumption across the entire
VCC range of 0.8 V to 3.6 V, resulting in increased
battery life (see AUP – The Lowest-Power Family).
This product also maintains excellent signal integrity
(see Excellent Signal Integrity).
1
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Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
Available in the Texas Instruments NanoStar™
Package
Low Static-Power Consumption
(ICC = 0.9 µA Maximum)
Low Dynamic-Power Consumption
(Cpd = 4.3 pF Typical at 3.3 V)
Low Input Capacitance (Ci = 1.5 pF Typical)
Low Noise – Overshoot and Undershoot <10% of
VCC
Ioff Supports Partial-Power-Down Mode Operation
Schmitt-Trigger Action Allows Slow Input
Transition and Better Switching Noise Immunity at
the Input
(Vhys = 250 mV Typical at 3.3 V)
Wide Operating VCC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode Signal
Operation
tpd = 4.4 ns Maximum at 3.3 V
Suitable for Point-to-Point Applications
This is a single positive-edge-triggered D-type flipflop. When data at the data (D) input meets the setup
time requirement, the data is transferred to the Q
output on the positive-going edge of the clock pulse.
Clock triggering occurs at a voltage level and is not
directly related to the rise time of the clock pulse.
Following the hold-time interval, data at the D input
can be changed without affecting the levels at the
outputs.
NanoStar™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs when the device is powered down. This
inhibits current backflow into the device which
prevents damage to the device.
Device Information(1)
PART NUMBER
2 Applications
•
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Home Automation
Factory Automation
Test and Measurement
Enterprise Switching
Telecom Infrastructure
Personal Electronics
White Goods
PACKAGE
BODY SIZE (NOM)
SN74AUP1G80DBV
SOT-23 (5)
1.60 mm × 2.90 mm
SN74AUP1G80DCK
SC70 (5)
1.25 mm × 2.00 mm
SN74AUP1G80DRY
SON (6)
1.00 mm × 1.45 mm
SN74AUP1G80DSF
SON (6)
1.00 mm × 1.00 mm
SN74AUP1G80YFP
DSBGA (6)
0.76 mm × 1.16 mm
SN74AUP1G80YZP
DSBGA (5)
0.89 mm × 1.39 mm
SN74AUP1G80DPW X2SON (5)
0.80 mm × 0.80 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
CLK
CLK
Q
D
Q
D
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AUP1G80
SCES593F – JULY 2004 – REVISED JULY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Electrical Characteristics: TA = 25°C ........................ 6
Electrical Characteristics: TA = –40°C to +85°C ....... 7
Timing Requirements ................................................ 7
Switching Characteristics: CL = 5 pF ........................ 8
Switching Characteristics: CL = 10 pF ...................... 9
Switching Characteristics: CL = 15 pF .................... 9
Switching Characteristics: CL = 30 pF .................. 10
Operating Characteristics...................................... 11
Typical Characteristics .......................................... 11
Parameter Measurement Information ................ 12
7.1 Propagation Delays, Setup and Hold Times, and
Pulse Duration ......................................................... 12
7.2 Enable and Disable Times ...................................... 13
8
Detailed Description ............................................ 14
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
14
14
15
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application .................................................. 16
10 Power Supply Recommendations ..................... 17
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 17
12 Device and Documentation Support ................. 18
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (May 2010) to Revision F
Page
•
Added DPW (X2SON) package.............................................................................................................................................. 1
•
Added Device Information table, Pin Configuration and Functions section, ESD Ratings table, Thermal Information
table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ...................................................................................................................... 1
•
Deleted Ordering Information table, see Mechanical, Packaging, and Orderable Information at the end of the data
sheet ...................................................................................................................................................................................... 1
•
Added Junction temperature, TJ in Absolute Maximum Ratings table ................................................................................... 4
2
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SCES593F – JULY 2004 – REVISED JULY 2017
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
D
1
CLK
2
GND
VCC
5
3
DCK Package
5-Pin SC70
Top View
D
1
CLK
2
GND
3
DRY Package
6-Pin SON
Top View
D
1
6
VCC
CLK
2
5
NC
GND
3
4
Q
GND
Q
B
CLK
N.C.
A
D
VCC
C
4
Q
DSF Package
6-Pin SON
Top View
D
1
6
VCC
CLK
2
5
N.C.
GND
3
4
Q
YFP Package
6-Pin DSBGA
Bottom View
2
VCC
Q
4
1
5
YZP Package
5-Pin DSBGA
Bottom View
1
2
C
GND
Q
B
CLK
A
D
Not to scale
VCC
Not to scale
DPW Package
5-Pin X2SON
Top View
GND
D
CLK
VCC
Q
Pin Functions
PIN
I/O
DESCRIPTION
DBV,
DCK
DRY, DSF
YFP
YZP
DPW
D
1
1
A1
A1
1
I
Data input
CLK
2
2
B1
B1
2
I
Positive-Edge-Triggered Clock input
GND
3
3
C1
C1
3
—
Ground pin
Q
4
4
C2
C2
4
O
Inverted output
NC
—
5
B2
—
—
—
No Internal Connection
VCC
5
6
A2
A2
5
—
Positive Supply
NAME
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
4.6
V
(2)
VI
Input voltage
–0.5
4.6
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
4.6
V
VO
Voltage range applied to any output in the high or low state (2)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
Continuous current through VCC or GND
±50
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
See
VCC
(1)
Supply voltage
VCC = 0.8 V
VIH
High-level input voltage
MIN
MAX
UNIT
0.8
3.6
V
VCC
VCC = 1.1 V to 1.95 V
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.6
VCC = 3 V to 3.6 V
2
VCC = 0.8 V
VIL
Low-level input voltage
V
0
VCC = 1.1 V to 1.95 V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.9
V
VI
Input voltage
0
3.6
VO
Output voltage
0
VCC
V
VCC = 0.8 V
–20
µA
VCC = 1.1 V
–1.1
VCC = 1.4 V
–1.7
VCC = 1.65
–1.9
VCC = 2.3 V
–3.1
IOH
High-level output current (2)
VCC = 3 V
(1)
(2)
4
V
mA
–4
All unused inputs of the device must be held at VCC or GND to assure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
Defined by the signal integrity requirements and design-goal priorities.
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Recommended Operating Conditions (continued)
See (1)
MIN
Low-level output current (2)
IOL
MAX
UNIT
VCC = 0.8 V
20
µA
VCC = 1.1 V
1.1
VCC = 1.4 V
1.7
VCC = 1.65 V
1.9
VCC = 2.3 V
3.1
VCC = 3 V
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
mA
4
VCC = 0.8 V to 3.6 V
–40
200
ns/V
85
°C
6.4 Thermal Information
SN74AUP1G80
THERMAL METRIC (1)
DBV (SOT)
DCK (SC70)
DRY (SON)
DSF (SON)
YFP (DSBGA)
YZP (DSBGA)
DPW (X2SON)
5 PINS
5 PINS
6 PINS
6 PINS
6 PINS
5 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient
thermal resistance
267.2
284.1
341.1
377.1
125.4
146.2
489.2
°C/W
RθJC(top)
Junction-to-case (top)
thermal resistance
191.9
208.5
233.1
187.7
1.9
1.4
226.3
°C/W
RθJB
Junction-to-board
thermal resistance
101.1
103.1
206.7
236.6
37.2
39.3
352.9
°C/W
ψJT
Junction-to-top
characterization
parameter
83.0
76.6
63.4
29.0
0.5
0.7
38.2
°C/W
ψJB
Junction-to-board
characterization
parameter
100.8
102.3
206.7
236.3
37.5
39.8
352.1
°C/W
n/a
n/a
n/a
n/a
n/a
n/a
150.8
°C/W
Junction-to-case
RθJC(bot) (bottom) thermal
resistance
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics: TA = 25°C
over recommended operating free-air temperature range, TA = 25°C (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
0.8 V to 3.6 V
VCC – 0.1
IOH = –1.1 mA
1.1 V
0.75 × VCC
IOH = –1.7 mA
1.4 V
1.11
IOH = –1.9 mA
1.65 V
1.32
2.3 V
IOH = –3.1 mA
IOH = –2.7 mA
3V
IOH = –4 mA
MAX
1.9
2.72
2.6
IOL = 1.1 mA
1.1 V
0.3 × VCC
IOL = 1.7 mA
1.4 V
0.31
IOL = 1.9 mA
1.65 V
0.31
0.1
0.31
2.3 V
IOL = 2.7 mA
VI = GND to 3.6 V
V
0.44
0.31
3V
IOL = 4 mA
UNIT
V
2.05
0.8 V to 3.6 V
IOL = 3.1 mA
II
TYP
IOL = 20 µA
IOL = 2.3 mA
D or CLK
input
MIN
IOH = –20 µA
IOH = –2.3 mA
VOL
VCC
0.44
0 V to 3.6 V
0.1
µA
Ioff
VI or VO = 0 V to 3.6 V
0V
0.2
µA
ΔIoff
VI or VO = 0 V to 3.6 V
0 V to 0.2 V
0.2
µA
ICC
VI = GND or VCC to 3.6 V, IO = 0
0.8 V to 3.6 V
0.5
µA
40
µA
ΔICC
VI = VCC – 0.6 V,
Ci
VI = VCC or GND
Co
VO = GND
(1)
6
(1)
IO = 0
3.3 V
0V
1.5
3.6 V
1.5
0V
3
pF
pF
One input at VCC – 0.6 V, other input at VCC or GND
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6.6 Electrical Characteristics: TA = –40°C to +85°C
over recommended operating free-air temperature range, TA = –40°C to +85°C (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
VCC
IOH = –20 µA
0.8 V to 3.6 V
VCC – 0.1
IOH = –1.1 mA
1.1 V
0.7 × VCC
IOH = –1.7 mA
1.4 V
1.03
IOH = –1.9 mA
1.65 V
1.3
IOH = –2.3 mA
IOH = –2.7 mA
2.67
2.55
0.8 V to 3.6 V
0.1
IOL = 1.1 mA
1.1 V
0.3 × VCC
IOL = 1.7 mA
1.4 V
0.37
IOL = 1.9 mA
1.65 V
0.35
IOL = 2.7 mA
0.45
0.33
3V
IOL = 4 mA
VI = GND to 3.6 V
V
0.33
2.3 V
IOL = 3.1 mA
II
V
IOL = 20 µA
IOL = 2.3 mA
D or CLK
input
UNIT
1.85
3V
IOH = –4 mA
MAX
1.97
2.3 V
IOH = –3.1 mA
VOL
MIN
0.45
0 V to 3.6 V
0.5
µA
Ioff
VI or VO = 0 V to 3.6 V
0V
0.6
µA
ΔIoff
VI or VO = 0 V to 3.6 V
0 V to 0.2 V
0.6
µA
ICC
VI = GND or VCC to 3.6 V, IO = 0
0.8 V to 3.6 V
0.9
µA
3.3 V
50
µA
VI = VCC – 0.6 V,
ΔICC
(1)
(1)
IO = 0
One input at VCC – 0.6 V, other input at VCC or GND
6.7 Timing Requirements
over recommended operating free-air temperature range, TA = –40°C to +85°C (unless otherwise noted) (see Figure 3)
VCC
MIN
0.8 V
fclock
tw
(1)
Clock frequency
Pulse duration, CLK high or low
TYP (1)
MAX
UNIT
20
1.2 V ± 0.1 V
80
1.5 V ± 0.1 V
120
1.8 V ± 0.15 V
160
2.5 V ± 0.2 V
220
3.3 V ± 0.3 V
260
0.8 V
5.5
1.2 V ± 0.1 V
2.5
1.5 V ± 0.1 V
1.5
1.8 V ± 0.15 V
1.6
2.5 V ± 0.2 V
1.7
3.3 V ± 0.3 V
1.9
MHz
TA = 25°C
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Timing Requirements (continued)
over recommended operating free-air temperature range, TA = –40°C to +85°C (unless otherwise noted) (see Figure 3)
Data high
tsu
Setup time before CLK↑
Data low
th
Hold time, data after CLK↑
VCC
MIN
TYP (1)
3.4
0.8 V
6.7
1.2 V ± 0.1 V
2.4
1.5 V ± 0.1 V
1.2
1.8 V ± 0.15 V
0.8
2.5 V ± 0.2 V
0.6
3.3 V ± 0.3 V
0.4
0.8 V
8.9
1.2 V ± 0.1 V
2
1.5 V ± 0.1 V
1.3
1.8 V ± 0.15 V
1.1
2.5 V ± 0.2 V
0.8
3.3 V ± 0.3 V
0.7
0.8 V
1
1.2 V ± 0.1 V
0
1.5 V ± 0.1 V
0
1.8 V ± 0.15 V
0
2.5 V ± 0.2 V
0
3.3 V ± 0.3 V
0
MAX
UNIT
ns
3.4
ns
0
ns
6.8 Switching Characteristics: CL = 5 pF
over recommended operating free-air temperature range, CL = 5 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
VCC = 0.8 V
VCC = 1.2 V ± 0.1 V
VCC = 1.5 V ± 0.1 V
fmax
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 0.8 V
VCC = 1.2 V ± 0.1 V
VCC = 1.5 V ± 0.1 V
tpd
CLK
Q
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
8
MIN
TA = 25°C
TA = –40°C to +85°C
175
220
237
230
TA = 25°C
TA = –40°C to +85°C
240
280
250
TA = 25°C
TA = –40°C to +85°C
280
260
TA = 25°C
17.2
TA = 25°C
3.2
TA = –40°C to +85°C
2.7
TA = 25°C
1.9
TA = –40°C to +85°C
2.1
TA = 25°C
1.7
TA = –40°C to +85°C
1.6
TA = 25°C
1.4
TA = –40°C to +85°C
1.2
TA = 25°C
1.2
TA = –40°C to +85°C
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MHz
269
TA = 25°C
TA = –40°C to +85°C
UNIT
91
TA = 25°C
TA = –40°C to +85°C
MAX
90
TA = 25°C
TA = –40°C to +85°C
TYP
1
7.1
14.9
16.3
5
9.8
10.3
3.9
7.6
ns
8.1
2.8
5.3
5.6
2.2
4.1
4.4
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6.9 Switching Characteristics: CL = 10 pF
over recommended operating free-air temperature range, CL = 10 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
TA = 25°C
VCC = 0.8 V
VCC = 1.5 V ± 0.1 V
fmax
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 0.8 V
VCC = 1.5 V ± 0.1 V
CLK
Q
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
MAX
UNIT
70
TA = 25°C
128
TA = –40°C to +85°C
170
TA = 25°C
189
TA = –40°C to +85°C
220
TA = 25°C
MHz
234
TA = –40°C to +85°C
240
TA = 25°C
273
TA = –40°C to +85°C
250
TA = 25°C
280
TA = –40°C to +85°C
260
TA = 25°C
VCC = 1.2 V ± 0.1 V
TYP
68
TA = –40°C to +85°C
VCC = 1.2 V ± 0.1 V
tpd
MIN
19.4
TA = 25°C
4.4
TA = –40°C to +85°C
3.4
TA = 25°C
3.6
TA = –40°C to +85°C
2.6
TA = 25°C
2.9
TA = –40°C to +85°C
2.1
TA = 25°C
2.2
TA = –40°C to +85°C
1.7
TA = 25°C
1.9
TA = –40°C to +85°C
1.4
8.2
16.2
17.7
5.8
10.7
11.3
4.6
8.4
ns
3
3.3
5.9
6.3
2.7
4.7
4.9
6.10 Switching Characteristics: CL = 15 pF
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
VCC = 0.8 V
VCC = 1.2 V ± 0.1 V
VCC = 1.5 V ± 0.1 V
fmax
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
MIN
TA = 25°C
TYP
MAX
52
TA = –40°C to +85°C
50
TA = 25°C
98
TA = –40°C to +85°C
130
TA = 25°C
148
TA = –40°C to +85°C
180
TA = 25°C
196
TA = –40°C to +85°C
249
TA = –40°C to +85°C
250
TA = 25°C
280
TA = –40°C to +85°C
260
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TA = 25°C
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Switching Characteristics: CL = 15 pF (continued)
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
VCC = 0.8 V
TA = 25°C
VCC = 1.2 V ± 0.1 V
VCC = 1.5 V ± 0.1 V
tpd
CLK
Q
MIN
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
TYP
MAX
UNIT
21.5
TA = 25°C
3
TA = –40°C to +85°C
4.1
TA = 25°C
3.2
TA = –40°C to +85°C
3.2
TA = 25°C
2.7
TA = –40°C to +85°C
2.6
TA = 25°C
2.2
TA = –40°C to +85°C
2.1
TA = 25°C
1.9
TA = –40°C to +85°C
1.8
9.1
17.4
19
6.5
11.7
12.3
4.2
9.2
ns
9.8
3.8
6.5
6.9
3.1
5.1
5.5
6.11 Switching Characteristics: CL = 30 pF
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
VCC = 0.8 V
VCC = 1.2 V ± 0.1 V
VCC = 1.5 V ± 0.1 V
fmax
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 0.8 V
VCC = 1.2 V ± 0.1 V
VCC = 1.5 V ± 0.1 V
tpd
CLK
Q
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
10
MIN
TA = 25°C
MAX
UNIT
32
TA = –40°C to +85°C
20
TA = 25°C
71
TA = –40°C to +85°C
80
TA = 25°C
104
TA = –40°C to +85°C
120
TA = 25°C
MHz
133
TA = –40°C to +85°C
160
TA = 25°C
181
TA = –40°C to +85°C
220
TA = 25°C
257
TA = –40°C to +85°C
260
TA = 25°C
28.4
TA = 25°C
5.1
TA = –40°C to +85°C
6.2
TA = 25°C
4.8
TA = –40°C to +85°C
6.9
TA = 25°C
4
TA = –40°C to +85°C
2
TA = 25°C
3.3
TA = –40°C to +85°C
3.2
TA = 25°C
2.9
TA = –40°C to +85°C
2.8
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TYP
11.8
20.7
28.7
8.5
14.1
16.7
6.9
11.2
ns
13.3
5.1
7.9
9.3
4.2
6.4
7.5
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6.12 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
f = 10 MHz
VCC
TYP
0.8 V
4
1.2 V ± 0.1 V
4
1.5 V ± 0.1 V
4
1.8 V ± 0.15 V
4
2.5 V ± 0.2 V
4.1
3.3 V ± 0.3 V
4.3
UNIT
pF
6.13 Typical Characteristics
100%
80%
80%
60%
3.3 V
/RJLF ‚
60%
40%
3.3 V
/RJLF ‚
40%
20%
20%
AUP
0%
†
Switching Characteristics
at 25 MHz †
Dynamic-Power Consumption
(pF)
Static-Power Consumption
(mA)
100%
AUP
0%
3.5
3
2.5
2
1.5
1
0.5
0
-0.5
0
5
Single, dual, and triple gates
10
15 20 25
Time-ns
30
35
40
45
†
AUP1G08 data at CL = 15 pF
Figure 1. AUP – The Lowest-Power Family
Figure 2. Excellent Signal Integrity
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7 Parameter Measurement Information
7.1 Propagation Delays, Setup and Hold Times, and Pulse Duration
From Output
Under Test
CL
(see Note A)
1 MΩ
LOAD CIRCUIT
CL
VM
VI
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
tw
VCC
Input
VCC/2
VCC/2
VI
VM
Input
0V
VM
VOLTAGE WAVEFORMS
PULSE DURATION
0V
t PHL
t PLH
VOH
VM
Output
VM
VOL
t PHL
VCC
Timing Input
VCC/2
0V
t PLH
t su
VOH
VM
Output
VCC
VM
VOL
Data Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A.
B.
C.
D.
E.
th
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns.
The outputs are measured one at a time, with one transition per measurement.
tPLH and tPHL are the same as tpd.
All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
12
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7.2 Enable and Disable Times
2 × VCC
S1
5 kΩ
From Output
Under Test
GND
CL
(see Note A)
5 kΩ
TEST
S1
t PLZ/t PZL
t PHZ/t PZH
2 × VCC
GND
LOAD CIRCUIT
CL
VM
VI
VD
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
VCC
Output
Control
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC/2
0V
t PLZ
t PZL
VCC
VCC/2
VOL + VD
VOL
t PHZ
t PZH
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VCC/2
VOH − VD
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74AUP1G80 is a single positive-edge-triggered D-type flip-flop. Data at the input (D) is transferred to the
output (Q) on the positive-going edge of the clock pulse when the setup time requirement is met. Because the
clock triggering occurs at a voltage level, it is not directly related to the rise time of the clock pulse. This allows
for data at the input to be changed without affecting the level at the output, following the hold-time interval.
8.2 Functional Block Diagram
CLK
CLK
Q
Q
D
D
Figure 5. Logic Diagram (Positive Logic)
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device may
create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the power output of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined the in the Absolute Maximum Ratings table must be followed at
all times.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics: TA = 25°C table. The worst case resistance is calculated with
the maximum input voltage, given in the Absolute Maximum Ratings table, and the maximum input leakage
current, given in the Electrical Characteristics: TA = 25°C table, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating
Conditions table to avoid excessive currents and oscillations. If a slow or noisy input signal is required, a device
with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.
8.3.3 Clamp Diodes
The inputs and outputs to this device have negative clamping diodes.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
14
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Feature Description (continued)
Device
VCC
Logic
Input
Output
-IIK
-IOK
GND
Figure 6. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.4 Partial Power Down (Ioff)
The inputs and outputs for this device enter a high-impedance state when the supply voltage is 0 V. The
maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical
Characteristics: TA = 25°C table.
8.3.5 Over-Voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Absolute Maximum Ratings table.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74AUP1G80 device.
Table 1. Function Table
INPUTS
CLK
D
OUTPUT
Q
↑
H
L
↑
L
H
L or H
X
Q0
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A useful application for the SN74AUP1G80 is using it as a frequency divider. By feeding back the output (Q) to
the input (D), the output toggles on every rising edge of the clock waveform. The output goes HIGH once every
two clock cycles, so essentially the frequency of the clock signal is divided by a factor of two. The device does
not have preset or clear functions so the initial state of the output is unknown. This application implements the
use of an override pin to initially set the input HIGH or LOW. Initialization is not needed, but should be kept in
mind. Post initialization, the Override input is set to a high-impedance mode, or it can be used to force a HIGH or
LOW output.
9.2 Typical Application
10 k
1.65 - 5.5V
Override
1
D
2
CLK
3
GND
VCC
5
Q
4
0.1 F
1 kHz Clock
500 Hz
Clock
Figure 7. Clock Frequency Division
9.2.1 Design Requirements
For this application, a resistor must be placed on the feedback line in order for the initialization voltage from the
override input to overpower the signal coming from the output (Q). Without a resistor the state at the input would
be unknown as the output of the SN74AUP1G80 is driving the line separate from the Override input.
The SN74AUP1G80 device uses CMOS technology and has balanced output drive. Take care to avoid bus
contention because it can drive currents that would exceed maximum limits.
9.2.2 Detailed Design Procedure
1. Recommended input conditions:
– For rise time and fall time specifications, see Δt/Δv in the Recommended Operating Conditions table.
– For specified high and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Input voltages are recommended to not go below 0 V and not exceed 4.6 V for any VCC. See the Absolute
Maximum Ratings table.
2. Recommended output conditions:
– Load currents should not exceed ±20 mA. See the Absolute Maximum Ratings table.
– Output voltages are recommended to not go below 0 V and not exceed the VCC voltage. See the Absolute
Maximum Ratings table.
3. Feedback resistor:
– A 10-kΩ resistor is chosen to bias the input so the Override input can initialize the input and output. The
resistor value is important because a resistance too high, such as 1 MΩ, would cause too much of a
voltage drop, causing the output to no longer be able to drive the input. On the other hand, a resistor too
low, such as a 1 Ω, would not bias enough and might cause bus contention between the Q output and the
override input, possibly damaging the device.
16
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Typical Application (continued)
9.2.3 Application Curve
Figure 8. Frequency Division
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the
Recommended Operating Conditions table. A 0.1-µF bypass capacitor is recommended to be connected from
the VCC terminal to GND to prevent power disturbance. To reject different frequencies of noise, use multiple
bypass capacitors in parallel. Capacitors with values of 0.1 µF and 1 µF are commonly used in parallel. The
bypass capacitor must be installed as close to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
When a printed-circuit board (PCB) trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs
primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414
times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance
and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore
some traces must turn corners. Figure 9 shows progressively better techniques of rounding corners. Only the last
example (BEST) maintains constant trace width and minimizes reflections.
11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 9. Trace Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Implications of Slow or Floating CMOS Inputs
• Designing and Manufacturing with TI's X2SON Packages
• How to Select Little Logic
• Introduction to Logic
• Power-Up Behavior of Clocked Devices
• Understanding Schmitt Triggers
• Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
NanoStar, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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PACKAGE OPTION ADDENDUM
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27-Oct-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74AUP1G80DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
H80R
SN74AUP1G80DBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
H80R
SN74AUP1G80DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
H80R
SN74AUP1G80DBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
H80R
SN74AUP1G80DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(HX5, HXF, HXK, HX
O, HXR)
SN74AUP1G80DCKRE4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(HX5, HXF, HXK, HX
O, HXR)
SN74AUP1G80DCKRG4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(HX5, HXF, HXK, HX
O, HXR)
SN74AUP1G80DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(HX5, HXO, HXR)
SN74AUP1G80DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(HX5, HXO, HXR)
SN74AUP1G80DPWR
ACTIVE
X2SON
DPW
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
BC
SN74AUP1G80DRYR
ACTIVE
SON
DRY
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HX
SN74AUP1G80DSFR
ACTIVE
SON
DSF
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
HX
SN74AUP1G80YFPR
ACTIVE
DSBGA
YFP
6
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
SN74AUP1G80YZPR
ACTIVE
DSBGA
YZP
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
HXN
-40 to 85
HXN
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Oct-2017
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
SN74AUP1G80DBVR
SOT-23
3000
180.0
8.4
DBV
5
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.23
3.17
1.37
4.0
8.0
Q3
SN74AUP1G80DBVT
SOT-23
DBV
5
250
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
SN74AUP1G80DCKR
SC70
DCK
5
3000
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74AUP1G80DCKT
SC70
DCK
5
250
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74AUP1G80DPWR
X2SON
DPW
5
3000
178.0
8.4
0.91
0.91
0.5
2.0
8.0
Q3
SN74AUP1G80DRYR
SON
DRY
6
5000
180.0
9.5
1.15
1.6
0.75
4.0
8.0
Q1
SN74AUP1G80DSFR
SON
DSF
6
5000
180.0
9.5
1.16
1.16
0.5
4.0
8.0
Q2
SN74AUP1G80YFPR
DSBGA
YFP
6
3000
178.0
9.2
0.89
1.29
0.62
4.0
8.0
Q1
SN74AUP1G80YZPR
DSBGA
YZP
5
3000
178.0
9.2
1.02
1.52
0.63
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AUP1G80DBVR
SOT-23
DBV
5
3000
202.0
201.0
28.0
SN74AUP1G80DBVT
SOT-23
DBV
5
250
202.0
201.0
28.0
SN74AUP1G80DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
SN74AUP1G80DCKT
SC70
DCK
5
250
180.0
180.0
18.0
SN74AUP1G80DPWR
X2SON
DPW
5
3000
205.0
200.0
33.0
SN74AUP1G80DRYR
SON
DRY
6
5000
184.0
184.0
19.0
SN74AUP1G80DSFR
SON
DSF
6
5000
184.0
184.0
19.0
SN74AUP1G80YFPR
DSBGA
YFP
6
3000
220.0
220.0
35.0
SN74AUP1G80YZPR
DSBGA
YZP
5
3000
220.0
220.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRY 6
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4207181/G
PACKAGE OUTLINE
DRY0006A
USON - 0.6 mm max height
SCALE 8.500
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
B
A
PIN 1 INDEX AREA
1.5
1.4
C
0.6 MAX
SEATING PLANE
0.05
0.00
0.08 C
3X 0.6
SYMM
(0.127) TYP
(0.05) TYP
3
4
4X
0.5
SYMM
2X
1
1
6
6X
0.4
0.3
PIN 1 ID
(OPTIONAL)
5X
0.25
0.15
0.1
0.05
0.35
0.25
C A B
C
4222894/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DRY0006A
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
6
1
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
LAND PATTERN EXAMPLE
1:1 RATIO WITH PKG SOLDER PADS
EXPOSED METAL SHOWN
SCALE:40X
0.05 MAX
ALL AROUND
EXPOSED
METAL
0.05 MIN
ALL AROUND
EXPOSED
METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222894/A 01/2018
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DRY0006A
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
1
6
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X
4222894/A 01/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DPW0005A
X2SON - 0.4 mm max height
SCALE 12.000
PLASTIC SMALL OUTLINE - NO LEAD
0.85
0.75
B
A
0.85
0.75
PIN 1 INDEX AREA
0.4 MAX
C
SEATING PLANE
NOTE 3
(0.1)
0.05
0.00
(0.25)
4X (0.05)
0.25 0.1
2
4
2X
0.48
3
NOTE 3
2X (0.26)
5
1
4X
0.27
0.17
(0.06)
3X
0.27
0.17
0.1 C A B
0.05 C
0.32
0.23
4223102/B 09/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The size and shape of this feature may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.78)
SYMM
4X (0.42)
( 0.1)
VIA
0.05 MIN
ALL AROUND
TYP
1
5
4X (0.22)
SYMM
4X (0.26)
(0.48)
3
2
4
(R0.05) TYP
( 0.25)
4X (0.06)
(0.21) TYP
EXPOSED METAL
CLEARANCE
SOLDER MASK
OPENING, TYP
METAL UNDER
SOLDER MASK
TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:60X
4223102/B 09/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.42)
4X (0.22)
4X (0.06)
5
1
( 0.24)
4X (0.26)
SYMM
(0.21)
TYP
SOLDER MASK
EDGE
3
2
(R0.05) TYP
(0.48)
4
SYMM
(0.78)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
92% PRINTED SOLDER COVERAGE BY AREA
SCALE:100X
4223102/B 09/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
YZP0005
DSBGA - 0.5 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.19
0.15
0.05 C
BALL TYP
0.5 TYP
C
SYMM
1
TYP
D: Max = 1.418 mm, Min =1.358 mm
B
0.5
TYP
E: Max = 0.918 mm, Min =0.858 mm
A
5X
0.015
0.25
0.21
C A B
1
2
SYMM
4219492/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YZP0005
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
5X ( 0.23)
2
1
A
(0.5) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
SOLDER MASK
OPENING
0.05 MAX
( 0.23)
SOLDER MASK
OPENING
0.05 MIN
( 0.23)
METAL
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4219492/A 05/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YZP0005
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
5X ( 0.25)
(R0.05) TYP
1
2
A
(0.5)
TYP
SYMM
B
C
METAL
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4219492/A 05/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
YFP0006
DSBGA - 0.5 mm max height
SCALE 10.000
DIE SIZE BALL GRID ARRAY
B
E
A
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.19
0.13
BALL TYP
0.05 C
0.4
TYP
SYMM
C
D: Max = 1.19 mm, Min = 1.13 mm
0.8
TYP
SYMM
B
E: Max = 0.79 mm, Min = 0.73 mm
0.4 TYP
A
6X
0.015
0.25
0.21
C A B
1
2
4223410/A 11/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFP0006
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
6X ( 0.23)
2
1
A
(0.4) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
SCALE:50X
( 0.23)
METAL
0.05 MAX
METAL UNDER
SOLDER MASK
0.05 MIN
( 0.23)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4223410/A 11/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFP0006
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
6X ( 0.25)
1
2
A
(0.4) TYP
SYMM
B
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:50X
4223410/A 11/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
DSF0006A
X2SON - 0.4 mm max height
SCALE 10.000
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
B
A
PIN 1 INDEX AREA
1.05
0.95
0.4 MAX
C
SEATING PLANE
0.05 C
(0.11) TYP
SYMM
0.05
0.00
3
4
SYMM
2X
0.7
4X
0.35
6
1
6X
(0.1)
PIN 1 ID
6X
0.45
0.35
0.22
0.12
0.07
0.05
C B A
C
4220597/A 06/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MO-287, variation X2AAF.
www.ti.com
EXAMPLE BOARD LAYOUT
DSF0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.6)
(R0.05) TYP
1
6X (0.17)
6
SYMM
4X (0.35)
4
3
SYMM
(0.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:40X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220597/A 06/2017
NOTES: (continued)
4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DSF0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.6)
(R0.05) TYP
1
6
6X (0.17)
SYMM
4X (0.35)
4
3
SYMM
(0.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:40X
4220597/A 06/2017
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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