Texas Instruments | SN74AUC1G08 Single 2-Input Positive-AND Gate (Rev. P) | Datasheet | Texas Instruments SN74AUC1G08 Single 2-Input Positive-AND Gate (Rev. P) Datasheet

Texas Instruments SN74AUC1G08 Single 2-Input Positive-AND Gate (Rev. P) Datasheet
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SN74AUC1G08
SCES374P – SEPTEMBER 2001 – REVISED JUNE 2017
SN74AUC1G08 Single 2-Input Positive-AND Gate
1 Features
3 Description
•
This single 2-input positive-AND gate is operational at
0.8-V to 2.7-V VCC, but is designed specifically for
1.65-V to 1.95-V VCC operation.
1
•
•
•
•
•
•
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Available in the Texas Instruments NanoFree™
Package
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal Operation
Ioff Supports Partial-Power-Down Mode and Back
Drive Protection
Sub-1-V Operable
Max tpd of 2.4 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
The SN74AUC1G08 device performs the Boolean
function Y + A • B or Y + A ) B in positive logic.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74AUC1G08DBV SOT-23 (5)
2.90 mm × 1.60 mm
SN74AUC1G08DCK SC70 (5)
2.00 mm × 1.25 mm
SN74AUC1G08DRL SOT-5X3 (5)
1.60 mm × 1.20 mm
2 Applications
SN74AUC1G08YZP
1.75 mm × 1.25 mm
•
•
•
•
•
•
•
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
•
•
•
•
AV Receiver
Audio Dock: Portable
Blu-Ray Player and Home Theater
Embedded PC
MP3 Player/Recorder (Portable Audio)
Personal Digital Assistant (PDA)
Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital
Solid State Drive (SSD): Client and Enterprise
TV: LCD/Digital and High-Definition (HDTV)
Tablet: Enterprise
Video Analytics: Server
Wireless Headset, Keyboard, and Mouse
DSBGA (5)
Logic Diagram (Positive Logic)
A
B
1
2
4
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AUC1G08
SCES374P – SEPTEMBER 2001 – REVISED JUNE 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
3
4
4
4
5
5
5
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics: CL = 15 pF ......................
Switching Characteristics: CL = 30 pF ......................
6.8 Operating Characteristics.......................................... 5
7
8
Parameter Measurement Information .................. 6
Detailed Description .............................................. 7
8.1 Functional Block Diagram ......................................... 7
8.2 Device Functional Modes.......................................... 7
9
Device and Documentation Support.................... 8
9.1
9.2
9.3
9.4
9.5
9.6
Documentation Support ............................................
Receiving Notification of Documentation Updates....
Community Resources..............................................
Trademarks ...............................................................
Electrostatic Discharge Caution ................................
Glossary ....................................................................
8
8
8
8
8
8
10 Mechanical, Packaging, and Orderable
Information ............................................................. 8
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision O (April 2007) to Revision P
Page
•
Deleted DRY Package throughout data sheet ....................................................................................................................... 1
•
Added Applications, Device Information table, ESD Ratings table, Thermal Information table, Detailed Description,
Device and Documentation Support, and Mechanical, Packaging, and Orderable Information ............................................ 1
•
Deleted Ordering Information, see Mechanical, Packaging, and Orderable Information ....................................................... 1
2
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SCES374P – SEPTEMBER 2001 – REVISED JUNE 2017
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
A
1
B
2
GND
3
DRL Package
5-Pin SOT-5X3
Top View
VCC
5
1
B
2
GND
3
5
4
1
B
2
GND
3
Y
4
5
VCC
4
Y
YZP Package
5-Pin DSBGA
Bottom View
DCK Package
5-Pin SC70
Top View
A
A
VCC
1
2
C
GND
Y
B
B
A
A
VCC
Not to scale
Y
Pin Functions
PIN
I/O
DESCRIPTION
DBV, DCK,
DRL
YZP
A
1
A1
I
A logic input
B
2
B1
I
B logic input
GND
3
C1
—
Ground
Y
4
C2
O
Y AND Logic Output
VCC
5
A2
—
Positive Supply
NAME
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCC
Supply voltage
–0.5
3.6
V
VI
Input voltage (2)
–0.5
3.6
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
3.6
V
–0.5
(2)
VO
Output voltage
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
Continuous current through VCC or GND
±100
mA
150
°C
Tstg
(1)
(2)
Storage temperature
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
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SN74AUC1G08
SCES374P – SEPTEMBER 2001 – REVISED JUNE 2017
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6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
1000
Machine Model (A115-A)
200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
(1)
See
VCC
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
MIN
MAX
UNIT
0.8
2.7
V
Supply voltage
VCC = 0.8 V to 1.95 V
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
V
VCC = 0.8 V to 1.95 V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
0
0
3.6
V
VCC
V
VCC = 0.8 V
–0.7
VCC = 1.1 V
–3
VCC = 1.4 V
–5
VCC = 1.65 V
–8
VCC = 2.3 V
–9
VCC = 0.8 V
0.7
VCC = 1.1 V
3
VCC = 1.4 V
5
VCC = 1.65 V
8
VCC = 2.3 V
9
VCC = 0.8 V to 1.95 V
20
VCC = 2.3 V to 2.7 V
10
–40
V
85
mA
mA
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
6.4 Thermal Information
SN74AUC1G08
THERMAL METRIC (1)
RθJA
(1)
4
Junction-to-ambient thermal resistance
DBV (SOT-23)
DCK (SC70)
DRL (SOT5X3)
YZP
(DSBGA)
5 PINS
5 PINS
5 PINS
5 PINS
206
252
142
132
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
VOL
II
TYP (1)
MIN
MAX
IOH = –100 µA
0.8 V to 2.7 V
IOH = –0.7 mA
0.8 V
IOH = –3 mA
1.1 V
0.8
IOH = –5 mA
1.4 V
1
IOH = –8 mA
1.65 V
1.2
IOH = –9 mA
2.3 V
1.8
IOL = 100 µA
0.8 V to 2.7 V
IOL = 0.7 mA
0.8 V
IOL = 3 mA
1.1 V
0.3
IOL = 5 mA
1.4 V
0.4
IOL = 8 mA
1.65 V
0.45
IOL = 9 mA
2.3 V
0.6
UNIT
VCC – 0.1
0.55
V
0.2
0.25
V
VI = VCC or GND
0 to 2.7 V
±5
µA
Ioff
VI or VO = 2.7 V
0
±10
µA
ICC
VI = VCC or GND,
10
µA
CI
VI = VCC or GND
(1)
A or B input
VCC
IO = 0
0.8 V to 2.7 V
2.5 V
3
pF
All typical values are at TA = 25°C.
6.6 Switching Characteristics: CL = 15 pF
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1)
PARAMETER
tpd
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
TYP
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
A or B
Y
4.7
0.9
3.3
0.6
2.3
0.4
1.1
1.7
0.2
1.6
UNIT
ns
6.7 Switching Characteristics: CL = 30 pF
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
UNIT
MIN
TYP
MAX
MIN
MAX
0.7
1.3
2.4
0.5
2
ns
6.8 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation
capacitance
TEST
CONDITIONS
VCC = 0.8 V
VCC = 1.2 V
VCC = 1.5 V
VCC = 1.8 V
VCC = 2.5 V
TYP
TYP
TYP
TYP
TYP
f = 10 MHz
15
15
15
15
19
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UNIT
pF
5
SN74AUC1G08
SCES374P – SEPTEMBER 2001 – REVISED JUNE 2017
www.ti.com
7 Parameter Measurement Information
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
t PLH/t PHL
t PLZ/t PZL
t PHZ/t PZH
Open
2 × VCC
GND
RL
LOAD CIRCUIT
VCC
CL
RL
VD
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
t su
VCC
VCC/2
Input
VCC/2
th
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
t PHL
t PLH
VOH
VCC/2
Output
VCC/2
VOL
t PHL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC/2
VCC/2
VCC/2
VOL
VCC/2
0V
t PZL
t PLZ
VCC
VCC/2
t PZH
t PLH
VOH
Output
VCC
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + VD
VOL
t PHZ
VCC/2
VOH − VD
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
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SCES374P – SEPTEMBER 2001 – REVISED JUNE 2017
8 Detailed Description
8.1 Functional Block Diagram
A
B
1
4
2
Y
Figure 2. Logic Diagram (Positive Logic)
8.2 Device Functional Modes
Table 1 lists the functional modes of the SN74AUC1G08.
Table 1. Function Table
INPUTS
A
B
OUTPUT
Y
H
H
H
L
X
L
X
L
L
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SN74AUC1G08
SCES374P – SEPTEMBER 2001 – REVISED JUNE 2017
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9 Device and Documentation Support
9.1 Documentation Support
9.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004.
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
9.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
9.4 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
9.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
8
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Nov-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74AUC1G08DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(U08K, U08R)
SN74AUC1G08DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(UE5, UEF, UEK, UE
R)
SN74AUC1G08DCKRG4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(UE5, UEF, UEK, UE
R)
SN74AUC1G08DRLR
ACTIVE
SOT-5X3
DRL
5
4000
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
(UE7, UER)
SN74AUC1G08DRLRG4
ACTIVE
SOT-5X3
DRL
5
4000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(UE7, UER)
SN74AUC1G08YZPR
ACTIVE
DSBGA
YZP
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
UEN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-Nov-2018
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
SOT-23
DBV
5
3000
180.0
8.4
SN74AUC1G08DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
SN74AUC1G08DRLR
SOT-5X3
DRL
5
4000
180.0
8.4
1.98
SN74AUC1G08DRLR
SOT-5X3
DRL
5
4000
180.0
9.5
1.78
SN74AUC1G08YZPR
DSBGA
YZP
5
3000
178.0
9.2
1.02
SN74AUC1G08DBVR
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
Pack Materials-Page 1
3.23
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.17
1.37
4.0
8.0
Q3
2.5
1.2
4.0
8.0
Q3
1.78
0.69
4.0
8.0
Q3
1.78
0.69
4.0
8.0
Q3
1.52
0.63
4.0
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AUC1G08DBVR
SOT-23
DBV
5
3000
202.0
201.0
28.0
SN74AUC1G08DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
SN74AUC1G08DRLR
SOT-5X3
DRL
5
4000
202.0
201.0
28.0
SN74AUC1G08DRLR
SOT-5X3
DRL
5
4000
184.0
184.0
19.0
SN74AUC1G08YZPR
DSBGA
YZP
5
3000
220.0
220.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
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EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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PACKAGE OUTLINE
YZP0005
DSBGA - 0.5 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.19
0.15
0.05 C
BALL TYP
0.5 TYP
C
SYMM
1
TYP
D: Max = 1.418 mm, Min =1.358 mm
B
0.5
TYP
E: Max = 0.918 mm, Min =0.858 mm
A
5X
0.015
0.25
0.21
C A B
1
2
SYMM
4219492/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YZP0005
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
5X ( 0.23)
2
1
A
(0.5) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
SOLDER MASK
OPENING
0.05 MAX
( 0.23)
SOLDER MASK
OPENING
0.05 MIN
( 0.23)
METAL
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4219492/A 05/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YZP0005
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
5X ( 0.25)
(R0.05) TYP
1
2
A
(0.5)
TYP
SYMM
B
C
METAL
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4219492/A 05/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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