Texas Instruments | SN74LVC1G132 Single 2-Input NAND Gate With Schmitt-Trigger Inputs (Rev. D) | Datasheet | Texas Instruments SN74LVC1G132 Single 2-Input NAND Gate With Schmitt-Trigger Inputs (Rev. D) Datasheet

Texas Instruments SN74LVC1G132 Single 2-Input NAND Gate With Schmitt-Trigger Inputs (Rev. D) Datasheet
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SN74LVC1G132
SCES546D – FEBRUARY 2004 – REVISED JUNE 2017
SN74LVC1G132 Single 2-Input NAND Gate With Schmitt-Trigger Inputs
1 Features
3 Description
•
The SN74LVC1G132 device contains one 2-input
NAND gate with Schmitt-trigger inputs designed for
1.65-V to 5.5-V VCC operation and performs the
Boolean function Y = A × B or Y = A + B in positive
logic.
1
•
•
•
•
•
•
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Available in Texas Instruments
NanoStar™ and NanoFree™ Packages
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 5.3 ns at 3.3 V
Low Power Consumption, 10-µA Maximum ICC
±24-mA Output Drive at 3.3 V
Ioff Supports Partial-Power-Down Mode Operation
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
AV Receiver
Audio Dock: Portable
Blu-Ray Player and Home Theater
Embedded PC
MP3 Player/Recorder (Portable Audio)
Personal Digital Assistant (PDA)
Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital
Solid State Drive (SSD): Client and Enterprise
TV: LCD/Digital and High-Definition (HDTV)
Tablet: Enterprise
Video Analytics: Server
Wireless Headset, Keyboard, and Mouse
Because of Schmitt action, this device has different
input threshold levels for positive-going (VT+) and
negative-going (VT–) signals.
This device can be triggered from the slowest of input
ramps and still give clean jitter-free output signals.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
NanoStar™ and NanoFree™ package technology is
a major breakthrough in IC packaging concepts,
using the die as the package.
Device Information(1)
ORDER NUMBER
PACKAGE
BODY SIZE
SN74LVC1G132DBV
SOT-23 (5)
2.90 mm × 1.60 mm
SN74LVC1G132DCK
SC70 (5)
2.00 mm × 1.25 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
A
Y
B
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G132
SCES546D – FEBRUARY 2004 – REVISED JUNE 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
3
4
4
4
5
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics: –40°C to +85°C, CL = 15
pF ...............................................................................
6.7 Switching Characteristics: –40°C to +85°C...............
6.8 Switching Characteristics: –40°C to +125°C.............
5
6
6
6.9 Operating Characteristics.......................................... 6
7
8
Parameter Measurement Information .................. 7
Detailed Description .............................................. 9
8.1 Functional Block Diagram ......................................... 9
8.2 Device Functional Modes.......................................... 9
9
Device and Documentation Support.................. 10
9.1
9.2
9.3
9.4
9.5
9.6
Documentation Support .......................................... 10
Receiving Notification of Documentation Updates.. 10
Community Resources............................................ 10
Trademarks ............................................................. 10
Electrostatic Discharge Caution .............................. 10
Glossary .................................................................. 10
10 Mechanical, Packaging, and Orderable
Information ........................................................... 11
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (December 2013) to Revision D
Page
•
Added Applications, Device Information table, Pin Configuration and Functions section, ESD Ratings table, Thermal
Information table, Feature Description section, Device Functional Modes, Device and Documentation Support
section, and Mechanical, Packaging, and Orderable Information section.............................................................................. 1
•
Deleted YEP, YZP packages throughout data sheet ............................................................................................................. 1
Changes from Revision B (September 2006) to Revision C
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Removed Ordering Information table ..................................................................................................................................... 1
•
Updated operating temperature range. .................................................................................................................................. 4
•
Added ESD warning. ............................................................................................................................................................ 10
2
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SCES546D – FEBRUARY 2004 – REVISED JUNE 2017
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
A
1
B
2
GND
3
DCK Package
5-Pin SC70
Top View
VCC
5
Y
4
A
1
B
2
GND
3
5
VCC
4
Y
See mechanical drawings for dimensions.
Pin Functions
PIN
NAME
DBV, DCK
A
1
B
GND
I/O
DESCRIPTION
I
A logic input
2
I
B logic input
3
—
Ground
VCC
5
—
Positive supply
Y
4
O
Y NAND logic output
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
6.5
V
(2)
VI
Input voltage
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
150
°C
Tstg
(1)
(2)
(3)
Storage temperature
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
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6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
1000
Machine Model (A115-A)
200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
VCC
Supply voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
MIN
MAX
Operating
1.65
5.5
Data retention only
1.5
5.5
V
0
VCC
V
VCC = 1.65 V
–4
VCC = 2.3 V
–8
–16
VCC = 3 V
Low-level output current
(1)
mA
–24
VCC = 4.5 V
–32
VCC = 1.65 V
4
8
16
VCC = 3 V
mA
24
VCC = 4.5 V
TA
V
0
VCC = 2.3 V
IOL
UNIT
32
Operating free-air temperature
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
6.4 Thermal Information
SN74LVC1G132
THERMAL METRIC
RθJA
(1)
4
(1)
Junction-to-ambient thermal resistance
DBV (SOT-23)
DCK (SC70)
5 PINS
5 PINS
206
252
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
–40°C to +85°C
VCC
VT+
Positive-going
input threshold
voltage
VT–
Negative-going
input threshold
voltage
ΔVT
Hysteresis
(VT+ – VT–)
MIN
VOH
1.16
0.79
1.16
1.56
1.11
1.56
3V
1.5
1.87
1.5
1.87
4.5 V
2.16
2.74
2.16
2.74
5.5 V
2.61
3.33
2.61
3.33
1.65 V
0.39
0.62
0.39
0.62
2.3 V
0.58
0.87
0.58
0.87
3V
0.84
1.14
0.84
1.16
4.5 V
1.41
1.79
1.41
1.84
5.5 V
1.87
2.29
1.87
2.33
1.65 V
0.37
0.62
0.37
0.62
2.3 V
0.48
0.77
0.48
0.77
3V
0.56
0.87
0.54
0.87
4.5 V
0.71
1.04
0.66
1.04
0.71
1.11
0.67
1.11
VCC – 0.1
VCC – 0.1
1.65 V
1.2
1.2
2.3 V
1.9
1.9
2.4
2.4
2.3
2.3
3V
3.8
4.5 V
IOL = 100 µA
1.65 V to 5.5 V
0.1
0.1
IOL = 4 mA
1.65 V
0.45
0.45
IOL = 8 mA
2.3 V
0.3
0.3
0.4
0.4
0.55
0.55
0.55
0.55
4.5 V
VI = 5.5 V or GND
Ioff
VI or VO = 5.5 V
ICC
VI = VCC or GND, IO = 0
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
V
V
V
3.8
3V
IOL = 32 mA
UNIT
V
IOH = –32 mA
IOL = 24 mA
(1)
MAX
1.11
IOH = –8 mA
IOL = 16 mA
A or B inputs
TYP (1)
0.79
IOH = –4 mA
IOH = –24 mA
II
MIN
2.3 V
1.65 V to 5.5 V
IOH = –16 mA
VOL
–40°C to +125°C
MAX
1.65 V
5.5 V
IOH = –100 µA
TYP (1)
V
1.65 V to 5.5 V
±1
±1
µA
0
±10
±10
µA
1.65 V to 5.5 V
10
10
µA
3 V to 5.5 V
500
500
µA
3.3 V
3.5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
6.6 Switching Characteristics: –40°C to +85°C, CL = 15 pF
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1)
–40°C to +85°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
Y
VCC = 1.8 V
±0.15 V
VCC = 2.5 V
±0.2 V
VCC = 3.3 V
±0.3 V
VCC = 5 V
±0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
4
16
2.5
7
2
5.3
1.5
4.4
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6.7 Switching Characteristics: –40°C to +85°C
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2)
–40°C to +85°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
Y
VCC = 1.8 V
±0.15 V
VCC = 2.5 V
±0.2 V
VCC = 3.3 V
±0.3 V
VCC = 5 V
±0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
4
16
3
7.5
2
6
2
5
ns
6.8 Switching Characteristics: –40°C to +125°C
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2)
–40°C to +125°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
Y
VCC = 1.8 V
±0.15 V
VCC = 2.5 V
±0.2 V
VCC = 3.3 V
±0.3 V
VCC = 5 V
±0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
4
16.5
3
8
2
6.5
2
5.5
ns
6.9 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance
TEST
CONDITIONS
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
f = 10 MHz
17
18
18
20
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UNIT
pF
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SCES546D – FEBRUARY 2004 – REVISED JUNE 2017
7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
15 pF
15 pF
15 pF
15 pF
1 MW
1 MW
1 MW
1 MW
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
VM
VOL
tPHL
VM
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
8
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8 Detailed Description
8.1 Functional Block Diagram
A
Y
B
Figure 3. Logic Diagram (Positive Logic)
8.2 Device Functional Modes
Table 1 lists the functional modes of the SN74LVC1G132.
Table 1. Function Table
INPUTS
B
OUTPUT
Y
L
L
H
L
H
H
H
L
H
H
H
L
A
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9 Device and Documentation Support
9.1 Documentation Support
9.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
9.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
9.4 Trademarks
NanoStar, NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
9.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
10
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10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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4-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
74LVC1G132DCKRG4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D5R
74LVC1G132DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D5R
SN74LVC1G132DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(C3BJ, C3BR)
SN74LVC1G132DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(C3BJ, C3BR)
SN74LVC1G132DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(D55, D5J, D5R)
SN74LVC1G132DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(D55, D5J, D5R)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Apr-2019
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jan-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
74LVC1G132DCKRG4
Package Package Pins
Type Drawing
SC70
DCK
5
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
180.0
8.4
2.47
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2.3
1.25
4.0
8.0
Q3
74LVC1G132DCKTG4
SC70
DCK
5
250
180.0
8.4
2.47
2.3
1.25
4.0
8.0
Q3
SN74LVC1G132DBVR
SOT-23
DBV
5
3000
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
SN74LVC1G132DBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
SN74LVC1G132DBVT
SOT-23
DBV
5
250
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
SN74LVC1G132DBVT
SOT-23
DBV
5
250
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
SN74LVC1G132DCKR
SC70
DCK
5
3000
180.0
8.4
2.47
2.3
1.25
4.0
8.0
Q3
SN74LVC1G132DCKR
SC70
DCK
5
3000
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74LVC1G132DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
SN74LVC1G132DCKT
SC70
DCK
5
250
180.0
8.4
2.47
2.3
1.25
4.0
8.0
Q3
SN74LVC1G132DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jan-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
74LVC1G132DCKRG4
SC70
DCK
5
3000
183.0
183.0
20.0
74LVC1G132DCKTG4
SC70
DCK
5
250
183.0
183.0
20.0
SN74LVC1G132DBVR
SOT-23
DBV
5
3000
202.0
201.0
28.0
SN74LVC1G132DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
SN74LVC1G132DBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
SN74LVC1G132DBVT
SOT-23
DBV
5
250
202.0
201.0
28.0
SN74LVC1G132DCKR
SC70
DCK
5
3000
202.0
201.0
28.0
SN74LVC1G132DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
SN74LVC1G132DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
SN74LVC1G132DCKT
SC70
DCK
5
250
202.0
201.0
28.0
SN74LVC1G132DCKT
SC70
DCK
5
250
180.0
180.0
18.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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