Texas Instruments | SN74LVC2T45 Dual-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation (Rev. K) | Datasheet | Texas Instruments SN74LVC2T45 Dual-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation (Rev. K) Datasheet

Texas Instruments SN74LVC2T45 Dual-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation (Rev. K) Datasheet
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SN74LVC2T45
SCES516K – DECEMBER 2003 – REVISED JUNE 2017
SN74LVC2T45 Dual-Bit Dual-Supply Bus Transceiver With Configurable Voltage
Translation
1 Features
3 Description
•
This dual-bit noninverting bus transceiver uses two
separate configurable power-supply rails. The A port
is designed to track VCCA. VCCA accepts any supply
voltage from 1.65 V to 5.5 V. The B port is designed
to track VCCB. VCCB accepts any supply voltage from
1.65 V to 5.5 V. This allows for universal low-voltage
bidirectional translation between any of the 1.8-V,
2.5-V, 3.3-V, and 5-V voltage nodes.
1
•
•
•
•
•
•
•
•
•
Fully Configurable Dual-Rail Design Allows Each
Port to Operate Over the Full 1.65-V to 5.5-V
Power-Supply Range
VCC Isolation Feature – If Either VCC Input Is at
GND, Both Ports Are in the High-Impedance State
DIR Input Circuit Referenced to VCCA
Low Power Consumption, 4-μA Max ICC
Available in the Texas Instruments NanoFree™
Package
±24-mA Output Drive at 3.3 V
Ioff Supports Partial-Power-Down Mode Operation
Max Data Rates
– 420 Mbps (3.3-V to 5-V Translation)
– 210 Mbps (Translate to 3.3 V)
– 140 Mbps (Translate to 2.5 V)
– 75 Mbps (Translate to 1.8 V)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 4000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
2 Applications
•
•
•
•
Personal Electronic
Industrial
Enterprise
Telecom
The SN74LVC2T45 is designed for asynchronous
communication between two data buses. The logic
levels of the direction-control (DIR) input activate
either the B-port outputs or the A-port outputs. The
device transmits data from the A bus to the B bus
when the B-port outputs are activated, and from the B
bus to the A bus when the A-port outputs are
activated. The input circuitry on both A and B ports
always is active and must have a logic HIGH or LOW
level applied to prevent excess ICC and ICCZ.
The SN74LVC2T45 is designed so that the DIR input
circuit is supplied by VCCA. This device is fully
specified for partial-power-down applications using
Ioff. The Ioff circuitry disables the outputs, preventing
damaging current backflow through the device when
it is powered down.
The VCC isolation feature ensures that if either VCC
input is at GND, both ports are in the high-impedance
state. NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
Device Information(1)
PACKAGE
BODY SIZE (NOM)
SN74LVC2T45DCT
PART NUMBER
SM8 (8)
2.95 mm x 2.80 mm
SN74LVC2T45DCU
VSSOP (8)
2.30 mm x 2.00 mm
SN74LVC2T45YZP
DSBGA (8)
1.89 mm x 0.89 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Functional Block Diagram
DIR
A1
5
2
7
A2
B1
3
6
VCCA
B2
VCCB
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC2T45
SCES516K – DECEMBER 2003 – REVISED JUNE 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
7
8
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions ...................... 4
Thermal Information .................................................. 5
Electrical Characteristics .......................................... 6
Switching Characteristics: VCCA = 1.8 V ± 0.15 V..... 6
Switching Characteristics: VCCA = 2.5 V ± 0.2 V....... 7
Switching Characteristics: VCCA = 3.3 V ± 0.3 V....... 7
Switching Characteristics: VCCA = 5 V ± 0.5 V.......... 8
Operating Characteristics........................................ 8
Typical Characteristics ............................................ 9
Parameter Measurement Information ................ 12
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 13
9
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Applications ................................................ 14
10 Power Supply Recommendations ..................... 17
10.1 Power-Up Considerations ..................................... 17
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 18
12 Device and Documentation Support ................. 19
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
19
13 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (October 2014) to Revision K
Page
•
Changed data sheet title......................................................................................................................................................... 1
•
Added Junction temperature, TJ in Absolute Maximum Ratings ............................................................................................ 4
•
Added Documentation Support, Receiving Notification of Documentation Updates and Community Resources .............. 19
Changes from Revision I (March 2007) to Revision J
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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SCES516K – DECEMBER 2003 – REVISED JUNE 2017
5 Pin Configuration and Functions
DCT or DCU Package
8-Pin SM8 or VSSOP
Top View
VCCA
A1
A2
GND
1
8
2
7
3
6
4
5
YZP Package
8-Pin DSGBA
Bottom View
VCCB
B1
B2
DIR
1
2
D
GND
DIR
C
A2
B2
B
A1
B1
A
VCCA
VCCB
Not to scale
Pin Functions: DCT, DCU
PIN
NO.
NAME
TYPE
DESCRIPTION
A-port supply voltage. 1.65 V ≤ VCCA ≤ 5.5 V
1
VCCA
P
2
A1
I/O
Input/output A1. Referenced to VCCA
3
A2
I/O
Input/output A2. Referenced to VCCA
4
GND
G
Ground
5
DIR
I
Direction control signal
6
B2
I/O
Input/output B2. Referenced to VCCB
7
B1
I/O
Input/output B1. Referenced to VCCB
8
VCCB
P
B-port supply voltage. 1.65 V ≤ VCCB ≤ 5.5 V
Pin Functions: YZP
PIN
TYPE
DESCRIPTION
BALL
NAME
A1
VCCA
A2
VCCB
B1
A1
I/O
Input/output A1. Referenced to VCCA
B2
B1
I/O
Input/output B1. Referenced to VCCB
C1
A2
I/O
Input/output A2. Referenced to VCCA
C2
B2
I/O
Input/output B2. Referenced to VCCB
D1
GND
G
Ground
D2
DIR
I
Direction control signal
P
A-port supply voltage. 1.65 V ≤ VCCA ≤ 5.5 V
P
B-port supply voltage. 1.65 V ≤ VCCB ≤ 5.5 V
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply voltage
–0.5
6.5
V
VI
Input voltage (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or
low state (2) (3)
A port
–0.5
VCCA + 0.5
B port
–0.5
VCCB + 0.5
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
VCCA
VCCB
(1)
(2)
(3)
–65
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Machine model (A115-A)
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
(2) (3)
VCCI
VCCA
VCCB
VIH
VCCO
Supply voltage
High-level
input voltage
Data inputs (4)
Low-level
input voltage
Data inputs (4)
(4)
4
5.5
1.65
5.5
VCCI × 0.65
2.3 V to 2.7 V
1.7
3 V to 3.6 V
2
4.5 V to 5.5 V
VCCI × 0.7
UNIT
V
V
VCCI × 0.35
2.3 V to 2.7 V
0.7
3 V to 3.6 V
0.8
4.5 V to 5.5 V
(1)
(2)
(3)
MAX
1.65 V to 1.95 V
1.65 V to 1.95 V
VIL
MIN
1.65
V
VCCI × 0.3
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. See Implications of Slow or
Floating CMOS Inputs, SCBA004.
For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V.
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)(1) (2) (3)
VCCI
High-level
input voltage
VIH
DIR
(referenced to VCCA) (5)
DIR
(referenced to VCCA) (5)
VCCO
MIN
1.65 V to 1.95 V
VCCA × 0.65
2.3 V to 2.7 V
1.7
3 V to 3.6 V
2
4.5 V to 5.5 V
VCCA × 0.7
MAX
UNIT
V
1.65 V to 1.95 V
VCCA × 0.35
2.3 V to 2.7 V
0.7
3 V to 3.6 V
0.8
VIL
Low-level
input voltage
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCCO
V
4.5 V to 5.5 V
VCCA × 0.3
1.65 V to 1.95 V
IOH
High-level output current
IOL
Low-level output current
Δt/Δv
Input transition
rise or fall rate
Data inputs
Control input
TA
(5)
V
–4
2.3 V to 2.7 V
–8
3 V to 3.6 V
–24
4.5 V to 5.5 V
–32
1.65 V to 1.95 V
4
2.3 V to 2.7 V
8
3 V to 3.6 V
24
4.5 V to 5.5 V
32
1.65 V to 1.95 V
20
2.3 V to 2.7 V
20
3 V to 3.6 V
10
4.5 V to 5.5 V
5
1.65 V to 5.5 V
5
Operating free-air temperature
–40
mA
mA
ns/V
85
°C
For VCCI values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V.
6.4 Thermal Information
SN74LVC2T45
THERMAL METRIC (1)
DCT
DCU
YZP
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
184.0
203.6
105.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
114.7
75.9
1.6
°C/W
RθJB
Junction-to-board thermal resistance
96.4
82.3
10.8
°C/W
ψJT
Junction-to-top characterization parameter
40.8
7.2
3.1
°C/W
ψJB
Junction-to-board characterization parameter
95.4
81.9
10.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics (1) (2)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 μA
IOH = –8 mA
1.65 V to 4.5 V
1.65 V to 4.5 V
1.65 V
1.65 V
1.2
2.3 V
2.3 V
1.9
VI = VIH
Ioff
B port
A or B
port
IOZ
ICCA
3.8
IOL = 100 μA
1.65 V to 4.5 V
1.65 V to 4.5 V
0.1
1.65 V
1.65 V
0.45
2.3 V
2.3 V
0.3
3V
3V
0.55
VI = VCCA or GND
VO = VCCO or GND
VI = VCCI or GND, IO = 0
One A port at VCCA – 0.6 V,
DIR at VCCA,
B port = open
DIR
DIR at VCCA – 0.6 V,
B port = open,
A port at VCCA or GND
ΔICCB
B port
One B port at VCCB – 0.6 V,
DIR at GND, A port = open
CI
DIR
Cio
A or B
port
(1)
(2)
4.5 V
4.5 V
1.65 V to 5.5 V
1.65 V to 5.5 V
±1
±2
0V
0 to 5.5 V
±1
±2
0 to 5.5 V
0V
±1
±2
1.65 V to 5.5 V
1.65 V to 5.5 V
±1
±2
1.65 V to 5.5 V
1.65 V to 5.5 V
5V
0V
2
0V
5V
–2
1.65 V to 5.5 V
1.65 V to 5.5 V
3
5V
0V
–2
0V
5V
2
1.65 V to 5.5 V
1.65 V to 5.5 V
4
VI or VO = 0 to 5.5 V
A port
ΔICCA
V
2.4
VI = VIL
UNIT
VCCO – 0.1
3V
VI = VCCI or GND, IO = 0
ICCA + ICCB
(see Table 5)
MAX
4.5 V
VI = VCCI or GND, IO = 0
ICCB
MIN
3V
IOL = 32 mA
A port
MAX
4.5 V
IOL = 24 mA
DIR
TYP
IOH = –32 mA
IOL = 8 mA
II
MIN
IOH = –24 mA
IOL = 4 mA
VOL
–40°C to +85°C
VCCB
IOH = –4 mA
VOH
TA = 25°C
VCCA
V
0.55
µA
µA
µA
3
µA
µA
µA
50
3 V to 5.5 V
3 V to 5.5 V
µA
50
3 V to 5.5 V
3 V to 5.5 V
50
µA
VI = VCCA or GND
3.3 V
3.3 V
2.5
pF
VO = VCCA/B or GND
3.3 V
3.3 V
6
pF
VCCO is the VCC associated with the output port.
VCCI is the VCC associated with the input port.
6.6 Switching Characteristics: VCCA = 1.8 V ± 0.15 V
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) (see Figure 17)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
6
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
VCCB = 1.8 V
±0.15 V
VCCB = 2.5 V
±0.2 V
VCCB = 3.3 V
±0.3 V
VCCB = 5 V
±0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3
17.7
2.2
10.3
1.7
8.3
1.4
7.2
2.8
14.3
2.2
8.5
1.8
7.1
1.7
7
3
17.7
2.3
16
2.1
15.5
1.9
15.1
2.8
14.3
2.1
12.9
2
12.6
1.8
12.2
10.6
30.9
10.3
30.5
10.5
30.5
10.7
29.3
7.3
19.7
7.5
19.6
7.5
19.5
7
19.4
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ns
ns
ns
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Switching Characteristics: VCCA = 1.8 V ± 0.15 V (continued)
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) (see Figure 17)
PARAMETER
tPHZ
tPLZ
(1)
tPZH
(1)
tPZL
(1)
tPZH
(1)
tPZL
(1)
FROM
(INPUT)
TO
(OUTPUT)
DIR
B
DIR
A
DIR
B
VCCB = 1.8 V
±0.15 V
VCCB = 2.5 V
±0.2 V
VCCB = 3.3 V
±0.3 V
VCCB = 5 V
±0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
10
27.9
8.4
14.9
6.5
11.3
4.1
8.6
6.5
19.5
7.2
12.6
4.3
9.7
2.1
7.1
37.2
28.6
25.2
22.2
42.2
27.8
23.9
20.8
37.4
29.9
27.8
26.6
45.2
39
37.6
36.3
ns
ns
ns
The enable time is a calculated value, derived using the formula shown in the Enable Times section.
6.7 Switching Characteristics: VCCA = 2.5 V ± 0.2 V
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 17)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
(1)
tPZH
(1)
tPZL
(1)
tPZH
(1)
tPZL
(1)
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.8 V
±0.15 V
MIN
VCCB = 2.5 V
±0.2 V
VCCB = 3.3 V
±0.3 V
VCCB = 5 V
±0.5 V
UNIT
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.3
16
1.5
8.5
1.3
6.4
1.1
5.1
2.1
12.9
1.4
7.5
1.3
5.4
0.9
4.6
2.2
10.3
1.5
8.5
1.4
8
1
7.5
2.2
8.5
1.4
7.5
1.3
7
0.9
6.2
6.6
17.1
7.1
16.8
6.8
16.8
5.2
16.5
5.3
12.6
5.2
12.5
4.9
12.3
4.8
12.3
10.7
27.9
8.1
13.9
5.8
10.5
3.5
7.6
7.8
18.9
6.2
11.2
3.6
8.9
1.4
6.2
29.2
19.7
16.9
13.7
36.4
21.4
17.5
13.8
28.6
21
18.7
17.4
30
24.3
22.2
21.1
ns
ns
ns
ns
ns
ns
The enable time is a calculated value, derived using the formula shown in the Enable Times section.
6.8 Switching Characteristics: VCCA = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 17)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
(1)
tPZH
(1)
tPZL
(1)
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
VCCB = 1.8 V
±0.15 V
VCCB = 2.5 V
±0.2 V
VCCB = 3.3 V
±0.3 V
VCCB = 5 V
±0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.1
15.5
1.4
8
0.7
5.6
0.7
4.4
2
12.6
1.3
7
0.8
5
0.7
4
1.7
8.3
1.3
6.4
0.7
5.8
0.6
5.4
1.8
7.1
1.3
5.4
0.8
5
0.7
4.5
5
10.9
5.1
10.8
5
10.8
5
10.4
3.4
8.4
3.7
8.4
3.9
8.1
3.3
7.8
11.2
27.3
8
13.7
5.8
10.4
2.9
7.4
9.4
17.7
5.6
11.3
4.3
8.3
1
5.6
26
17.7
14.1
11
34.4
19.1
15.4
11.9
ns
ns
ns
ns
ns
The enable time is a calculated value, derived using the formula shown in the Enable Times section.
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Switching Characteristics: VCCA = 3.3 V ± 0.3 V (continued)
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 17)
PARAMETER
tPZH
(1)
tPZL
(1)
FROM
(INPUT)
TO
(OUTPUT)
DIR
B
VCCB = 1.8 V
±0.15 V
MIN
VCCB = 2.5 V
±0.2 V
MAX
MIN
MAX
VCCB = 3.3 V
±0.3 V
MIN
VCCB = 5 V
±0.5 V
MAX
MIN
UNIT
MAX
23.9
16.4
13.9
12.2
23.5
17.8
15.8
14.4
ns
6.9 Switching Characteristics: VCCA = 5 V ± 0.5 V
over recommended operating free-air temperature range, VCCA = 5 V ± 0.5 V (unless otherwise noted) (see Figure 17)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
(1)
tPZH
(1)
tPZL
(1)
tPZH
(1)
tPZL
(1)
VCCB = 1.8 V
±0.15 V
VCCB = 2.5 V
±0.2 V
VCCB = 3.3 V
±0.3 V
VCCB = 5 V
±0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1.9
15.1
1
7.5
0.6
5.4
0.5
3.9
1.8
12.2
0.9
6.2
0.7
4.5
0.5
3.5
1.4
7.2
1
5.1
0.7
4.4
0.5
3.9
1.7
7
0.9
4.6
0.7
4
0.5
3.5
2.9
8.2
2.9
7.9
2.8
7.9
2.2
7.8
1.4
6.9
1.3
6.7
0.7
6.7
0.7
6.6
11.2
26.1
7.2
13.9
5.8
10.1
1.3
7.3
8.4
16.9
5
11
4
7.7
1
5.6
24.1
16.1
12.1
9.5
33.1
18.5
14.1
10.8
22
14.2
12.1
10.5
20.4
14.1
12.4
11.3
ns
ns
ns
ns
ns
ns
The enable time is a calculated value, derived using the formula shown in the Enable Times section.
6.10 Operating Characteristics
TA = 25°C
PARAMETER
CpdA
CpdB
(1)
8
(1)
A-port input,
B-port output
B-port input,
A-port output
(1)
A-port input,
B-port output
B-port input,
A-port output
TEST
CONDITIONS
CL = 0 pF,
f = 10 MHz,
tr = tf = 1 ns
CL = 0 pF,
f = 10 MHz,
tr = tf = 1 ns
VCCA =
VCCB = 1.8 V
VCCA =
VCCB = 2.5 V
VCCA =
VCCB = 3.3 V
VCCA =
VCCB = 5 V
TYP
TYP
TYP
TYP
3
4
4
4
18
19
20
21
18
19
20
21
3
4
4
4
UNIT
pF
pF
Power dissipation capacitance per transceiver
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6.11 Typical Characteristics
10
10
9
9
8
8
VCCB = 1.8 V
VCCB = 1.8 V
7
6
VCCB = 2.5 V
5
6
t PLH− ns
t PHL − ns
7
VCCB = 2.5 V
5
VCCB = 3.3 V
4
4
VCCB = 5 V
3
VCCB = 3.3 V
3
VCCB = 5 V
2
2
1
1
0
0
0
5
10
15
20
25
30
0
35
5
10
Figure 1. Typical Propagation Delay of High-to-Low (A to B)
vs Load Capacitance TA = 25°C, VCCA = 1.8 V
10
9
9
8
8
6
6
VCCB = 5 V
t PLH − ns
t PHL − ns
7
4
30
35
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
5
4
3
3
2
2
1
1
0
0
0
5
10
15
20
25
30
35
0
5
10
CL − pF
Figure 3. Typical Propagation Delay of High-to-Low (B to A)
vs Load Capacitance TA = 25°C, VCCA = 1.8 V
10
9
9
8
8
7
7
VCCB = 1.8 V
t PLH − ns
6
5
VCCB = 2.5 V
4
VCCB = 3.3 V
3
3
VCCB = 5 V
VCCB = 3.3 V
30
35
6
4
2
25
VCCB = 1.8 V
5
VCCB = 2.5 V
15
20
CL − pF
Figure 4. Typical Propagation Delay of Low-to-High (B to A)
vs Load Capacitance TA = 25°C, VCCA = 1.8 V
10
t PHL − ns
25
VCCB = 1.8 V
VCCB = 1.8 V
7
VCCB = 2.5 V
VCCB = 3.3 V
20
Figure 2. Typical Propagation Delay of Low-to-High (A to B)
vs Load Capacitance TA = 25°C, VCCA = 1.8 V
10
5
15
CL − pF
CL − pF
2
VCCB = 5 V
1
1
0
0
0
5
10
15
20
25
30
35
0
CL − pF
5
10
15
20
25
30
35
CL − pF
Figure 5. Typical Propagation Delay of High-to-Low (A to B)
vs Load Capacitance TA = 25°C, VCCA = 2.5 V
Figure 6. Typical Propagation Delay of Low-to-High (A to B)
vs Load Capacitance TA = 25°C, VCCA = 2.5 V
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Typical Characteristics (continued)
10
9
9
8
8
7
7
t PHL − ns
10
t PLH − ns
6
VCCB = 1.8 V
5
4
6
4
3
VCCB = 3.3 V
VCCB = 5 V
2
VCCB = 2.5 V
VCCB = 3.3 V
3
VCCB = 2.5 V
VCCB = 5 V
2
1
1
0
0
5
10
15
20
CL − pF
25
30
0
35
0
5
10
15
20
25
30
35
CL − pF
Figure 7. Typical Propagation Delay of High-to-Low (B to A)
vs Load Capacitance TA = 25°C, VCCA = 2.5 V
Figure 8. Typical Propagation Delay of Low-to-High (B to A)
vs Load Capacitance TA = 25°C, VCCA = 2.5 V
10
10
9
9
8
8
VCCB = 1.8 V
7
7
VCCB = 1.8 V
6
6
t PLH − ns
t PHL − ns
VCCB = 1.8 V
5
5
VCCB = 2.5 V
4
3
VCCB = 2.5 V
5
4
VCCB = 3.3 V
3
VCCB = 5 V
2
2
VCCB = 3.3 V
1
1
VCCB = 5 V
0
0
0
5
10
15
20
25
30
35
0
5
10
20
25
30
35
Figure 10. Typical Propagation Delay of Low-to-High (A to
B) vs Load Capacitance TA = 25°C, VCCA = 3.3 V
10
10
9
9
8
8
7
7
6
6
t PLH − ns
t PHL − ns
Figure 9. Typical Propagation Delay of High-to-Low (A to B)
vs Load Capacitance TA = 25°C, VCCA = 3.3 V
5
VCCB = 1.8 V
4
3
VCCB = 1.8 V
5
4
3
2
VCCB = 2.5 V
VCCB = 2.5 V
2
VCCB = 3.3 V
VCCB = 3.3 V
1
1
VCCB = 5 V
0
VCCB = 5 V
0
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30
35
CL − pF
CL − pF
Figure 11. Typical Propagation Delay of High-to-Low (B to
A) vs Load Capacitance TA = 25°C, VCCA = 3.3 V
10
15
CL − pF
CL − pF
Figure 12. Typical Propagation Delay of Low-to-High (B to
A) vs Load Capacitance TA = 25°C, VCCA = 3.3 V
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Typical Characteristics (continued)
10
10
9
9
8
8
VCCB = 1.8 V
7
7
VCCB = 1.8 V
t PLH − ns
t PHL − ns
6
5
4
6
5
VCCB = 2.5 V
4
VCCB = 2.5 V
VCCB = 3.3 V
3
3
2
2
VCCB = 5 V
VCCB = 3.3 V
1
0
1
VCCB = 5 V
0
0
5
10
15
20
25
30
35
0
5
10
CL − pF
9
8
8
7
7
6
6
t PLH − ns
t PHL− ns
10
9
5
3
VCCB = 2.5 V
25
30
35
Figure 14. Typical Propagation Delay of Low-to-High (A to
B) vs Load Capacitance TA = 25°C, VCCA = 5 V
10
4
20
CL − pF
Figure 13. Typical Propagation Delay of High-to-Low (A to
B) vs Load Capacitance TA = 25°C, VCCA = 5 V
VCCB = 1.8 V
15
5
VCCB = 1.8 V
4
VCCB = 2.5 V
3
2
2
VCCB = 3.3 V
VCCB = 3.3 V
VCCB = 5 V
1
VCCB = 5 V
1
0
0
0
5
10
15
20
25
30
35
0
CL − pF
5
10
15
20
25
30
35
CL − pF
Figure 15. Typical Propagation Delay of High-to-Low (B to
A) vs Load Capacitance TA = 25°C, VCCA = 5 V
Figure 16. Typical Propagation Delay of Low-to-High (B to
A) vs Load Capacitance TA = 25°C, VCCA = 5 V
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7 Parameter Measurement Information
2 × VCCO
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCCO
GND
RL
tw
LOAD CIRCUIT
VCCI
VCCI/2
Input
VCCO
CL
RL
VTP
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
15 pF
15 pF
15 pF
15 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
0.15 V
0.15 V
0.3 V
0.3 V
VCCI/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VCCA
Output
Control
(low-level
enabling)
VCCA/2
VCCA/2
0V
tPLZ
tPZL
VCCI
Input
VCCI/2
VCCI/2
0V
tPLH
Output
tPHL
VOH
VCCO/2
VOL
VCCO/2
VCCO
Output
Waveform 1
S1 at 2 × VCCO
(see Note B)
VCCO/2
VOL + VTP
VOL
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCCO/2
VOH − VTP
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR v10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
J. All parameters and waveforms are not applicable to all devices.
Figure 17. Load Circuit and Voltage Waveforms
12
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8 Detailed Description
8.1 Overview
The SN74LVC2T45 is dual-bit, dual-supply noninverting voltage level translation. Pin Ax and direction control pin
are support by VCCA and pin Bx are support by VCCB. The A port is able to accept I/O voltages ranging from 1.65
V to 5.5 V, while the B port can accept I/O voltages from 1.65 V to 5.5 V. The high on DIR allows data
transmission from A to B and a low on DIR allows data transmission from B to A.
8.2 Functional Block Diagram
DIR
5
2
A1
7
B1
3
A2
6
VCCA
B2
VCCB
Figure 18. Logic Diagram (Positive Logic)
8.3 Feature Description
8.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V
Power-Supply Range
Both VCCA and VCCB can be supplied at any voltage between 1.65 V and 5.5 V making the device suitable for
translating between any of the voltage nodes (1.8-V, 2.5-V, 3.3-V and 5-V).
8.3.2 Support High-Speed Translation
SN74LVC2T45 can support high data rate application. The translated signal data rate can be up to 420 Mbps
when signal is translated from 3.3 V to 5 V.
8.3.3 Ioff Supports Partial-Power-Down Mode Operation
Ioff will prevent backflow current by disabling I/O output circuits when device is in partial-power-down mode.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74LVC2T45 device.
Table 1. Function Table (1) (Each Transceiver)
(1)
INPUT
DIR
OPERATION
L
B data to A bus
H
A data to B bus
Input circuits of the data I/Os always are active.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC2T45 device can be used in level-translation applications for interfacing devices or systems
operating at different interface voltages with one another. The maximum data rate can be up to 420 Mbps when
device translate signal from 3.3 V to 5 V.
9.2 Typical Applications
9.2.1 Unidirectional Logic Level-Shifting Application
Figure 19 shows an example of the SN74LVC2T45 being used in a unidirectional logic level-shifting application.
VCC2
VCC1
VCC1
VCC2
1
8
2
7
3
6
4
5
VCC2
VCC1
SYSTEM-1
SYSTEM-2
Figure 19. Unidirectional Logic Level-Shifting Application
9.2.1.1 Design Requirements
Table 2 lists the pins and pin descriptions of the SN74LVC2T45 connections with SYSTEM-1 and SYSTEM-2.
Table 2. SN74LVC2T45 Pin Connections With SYSTEM-1 and SYSTEM-2
14
PIN
NAME
FUNCTION
DESCRIPTION
1
VCCA
VCC1
SYSTEM-1 supply voltage (1.65 V to 5.5 V)
2
A1
OUT1
Output level depends on VCC1 voltage.
3
A2
OUT2
Output level depends on VCC1 voltage.
4
GND
GND
Device GND
5
DIR
DIR
GND (low level) determines B-port to A-port direction.
6
B2
IN2
Input threshold value depends on VCC2 voltage.
7
B1
IN1
Input threshold value depends on VCC2 voltage.
8
VCCB
VCC2
SYSTEM-2 supply voltage (1.65 V to 5.5 V)
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For this design example, use the parameters listed in Table 3.
Table 3. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
1.65 V to 5.5 V
Output voltage range
1.65 V to 5.5 V
9.2.1.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the SN74LVC2T45 device to determine the input
voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low
the value must be less than the VIL of the input port.
• Output voltage range
– Use the supply voltage of the device that the SN74LVC2T45 device is driving to determine the output
voltage range.
9.2.1.3 Application Curve
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9.2.2 Bidirectional Logic Level-Shifting Application
Figure 20 shows the SN74LVC2T45 being used in a bidirectional logic level-shifting application. Because the
SN74LVC2T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid
bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
VCC1
VCC1
VCC2
Pullup/Down
or Bus Hold(1)
Pullup/Down
or Bus Hold(1)
I/O-1
VCC2
1
8
2
7
3
6
4
5
I/O-2
DIR CTRL
SYSTEM-1
SYSTEM-2
Figure 20. Bidirectional Logic Level-Shifting Application
9.2.2.1 Design Requirements
Please refer to Unidirectional Logic Level-Shifting Application.
9.2.2.2 Detailed Design Procedure
Table 4 shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to SYSTEM-1.
Table 4. Data Transmission Sequence
STATE
DIR CTRL
I/O-1
I/O-2
1
H
Out
In
2
H
Hi-Z
Hi-Z
SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The busline state depends on pullup or pulldown. (1)
3
L
Hi-Z
Hi-Z
DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on pullup or
pulldown. (1)
4
L
In
Out
SYSTEM-2 data to SYSTEM-1
(1)
DESCRIPTION
SYSTEM-1 data to SYSTEM-2
SYSTEM-1 and SYSTEM-2 must use the same conditions, that is, both pullup or both pulldown.
9.2.2.2.1 Enable Times
Calculate the enable times for the SN74LVC2T45 using the following formulas:
• tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
• tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
• tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
• tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74LVC2T45 initially is transmitting from A to B, then
the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B
port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
16
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9.2.2.3 Application Curve
10 Power Supply Recommendations
10.1 Power-Up Considerations
A proper power-up sequence with inputs held at ground should be followed as listed :
1. Connect ground before any supply voltage is applied.
2. Power up VCCA.
3. VCCB can be ramped up along with or after VCCA.
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply,
0.1 µF is recommended. If there are multiple VCC pins, 0.01 µF or 0.022 µF is recommended for each power pin.
It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1-µF and 1-µF are
commonly used in parallel. The bypass capacitor must be installed as close to the power pin as possible for best
results.
Table 5. Typical Total Static Power Consumption (ICCA + ICCB)
VCCB
VCCA
0V
1.8 V
2.5 V
3.3 V
5V
<1
0V
0
<1
<1
<1
1.8 V
<1
<2
<2
<2
2
2.5 V
<1
<2
<2
<2
<2
3.3 V
<1
<2
<2
<2
<2
5V
<1
2
<2
<2
<2
UNIT
µA
11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, following common printed-circuit board layout guidelines is recommended.
• Bypass capacitors should be used on power supplies.
• Short trace lengths should be used to avoid excessive loading.
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Layout Guidelines (continued)
•
Placing pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of
signals depending on the system requirements
11.2 Layout Example
LEGEND
VIA to Power Plane
Polygonal Copper Pour
VIA to GND Plane (Inner Layer)
VCCB
VCCA
Bypass Capacitor
Bypass Capacitor
1
VCCA
VCCB
8
From
Controller
2
A1
B1
7
To
System
From
Controller
3
A2
B2
6
To
System
4
GND
DIR
5
VCCA
SN74LVC2T45
18
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004.
Designing with SN74LVCXT245
translators,SLVA746
and
SN74LVCHXT245
Family
of
Direction
controlled
voltage
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2003–2017, Texas Instruments Incorporated
Product Folder Links: SN74LVC2T45
19
PACKAGE OPTION ADDENDUM
www.ti.com
15-May-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LVC2T45DCTR
ACTIVE
SM8
DCT
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CT2
Z
SN74LVC2T45DCTRE4
ACTIVE
SM8
DCT
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CT2
Z
SN74LVC2T45DCTT
ACTIVE
SM8
DCT
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CT2
Z
SN74LVC2T45DCTTG4
ACTIVE
SM8
DCT
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CT2
Z
SN74LVC2T45DCUR
ACTIVE
VSSOP
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
(CT2Q ~ CT2R ~ T2)
CZ
SN74LVC2T45DCURE4
ACTIVE
VSSOP
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CT2R
SN74LVC2T45DCURG4
ACTIVE
VSSOP
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CT2R
SN74LVC2T45DCUT
ACTIVE
VSSOP
DCU
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(CT2Q ~ CT2R ~ T2)
CZ
SN74LVC2T45DCUTG4
ACTIVE
VSSOP
DCU
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CT2R
SN74LVC2T45YZPR
ACTIVE
DSBGA
YZP
8
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(TB ~ TB7 ~ TBN)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
15-May-2017
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC2T45 :
• Automotive: SN74LVC2T45-Q1
• Enhanced Product: SN74LVC2T45-EP
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74LVC2T45DCTR
Package Package Pins
Type Drawing
SM8
DCT
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
180.0
13.0
3.35
4.5
1.55
4.0
12.0
Q3
SN74LVC2T45DCTT
SM8
DCT
8
250
180.0
13.0
3.35
4.5
1.55
4.0
12.0
Q3
SN74LVC2T45DCUR
VSSOP
DCU
8
3000
180.0
9.0
2.05
3.3
1.0
4.0
8.0
Q3
SN74LVC2T45DCURG4
VSSOP
DCU
8
3000
180.0
8.4
2.25
3.35
1.05
4.0
8.0
Q3
SN74LVC2T45DCUTG4
VSSOP
DCU
8
250
180.0
8.4
2.25
3.35
1.05
4.0
8.0
Q3
SN74LVC2T45YZPR
DSBGA
YZP
8
3000
180.0
8.4
1.02
2.02
0.63
4.0
8.0
Q1
SN74LVC2T45YZPR
DSBGA
YZP
8
3000
178.0
9.2
1.02
2.02
0.63
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC2T45DCTR
SM8
DCT
8
3000
182.0
182.0
20.0
SN74LVC2T45DCTT
SM8
DCT
8
250
182.0
182.0
20.0
SN74LVC2T45DCUR
VSSOP
DCU
8
3000
182.0
182.0
20.0
SN74LVC2T45DCURG4
VSSOP
DCU
8
3000
202.0
201.0
28.0
SN74LVC2T45DCUTG4
VSSOP
DCU
8
250
202.0
201.0
28.0
SN74LVC2T45YZPR
DSBGA
YZP
8
3000
182.0
182.0
20.0
SN74LVC2T45YZPR
DSBGA
YZP
8
3000
220.0
220.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
8
0,13 M
5
0,15 NOM
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
1
0,25
4
0° – 8°
3,15
2,75
0,60
0,20
1,30 MAX
Seating Plane
0,10
0,10
0,00
NOTES: A.
B.
C.
D.
4188781/C 09/02
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion
Falls within JEDEC MO-187 variation DA.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OUTLINE
YZP0008
DSBGA - 0.5 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.19
0.15
0.05 C
BALL TYP
0.5 TYP
D
C
SYMM
1.5
TYP
0.5
TYP
8X
0.015
D: Max = 1.918 mm, Min =1.858 mm
B
0.25
0.21
C A B
E: Max = 0.918 mm, Min =0.858 mm
A
1
2
SYMM
4223082/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YZP0008
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
8X ( 0.23)
2
1
A
(0.5) TYP
B
SYMM
C
D
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
SOLDER MASK
OPENING
0.05 MAX
( 0.23)
SOLDER MASK
OPENING
0.05 MIN
( 0.23)
METAL
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4223082/A 07/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YZP0008
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
8X ( 0.25)
(R0.05) TYP
1
2
A
(0.5)
TYP
B
SYMM
C
METAL
TYP
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4223082/A 07/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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