Texas Instruments | SN74LVC1G373 Single D-Type Latch With 3-State Output (Rev. F) | Datasheet | Texas Instruments SN74LVC1G373 Single D-Type Latch With 3-State Output (Rev. F) Datasheet

Texas Instruments SN74LVC1G373 Single D-Type Latch With 3-State Output (Rev. F) Datasheet
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SN74LVC1G373
SCES528F – DECEMBER 2003 – REVISED MAY 2017
SN74LVC1G373 Single D-Type Latch With 3-State Output
1 Features
3 Description
•
The SN74LVC1G373 device is a single D-type latch
designed for 1.65-V to 5.5-V VCC operation.
1
•
•
•
•
•
•
•
•
Available in the Texas Instruments
NanoFree™ Package
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Provides Down Translation to VCC
Max tpd of 4 ns at 3.3 V
Low Power Consumption: 10-μA
Maximum ICC
±24-mA Output Drive at 3.3 V
Ioff Supports Partial-Power-Down Mode and Back
Drive Protection
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
This device is particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus drivers,
and working registers. While the latch-enable (LE)
input is high, the Q outputs follow the data (D) inputs.
When LE is taken low, the Q outputs are latched at
the logic levels set up at the D inputs.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
OE does not affect the internal operations of the
latch. Old data can be retained or new data can be
entered while the outputs are in the high-impedance
state.
2 Applications
•
•
•
•
•
•
Device Information(1)
Servers
Printers
Telecom and Grid Infrastructure
Memory Addressing
Buffer Registers
Electronic Point of Sale
PACKAGE NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LVC1G373DBV
SOT-23 (6)
2.90 mm × 1.60 mm
SN74LVC1G373DCK
SC70 (6)
2.00 mm × 1.25 mm
SN74LVC1G373YZP
DSBGA (6)
1.41 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
OE
LE
6
1
C
D
3
4
Q
D
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G373
SCES528F – DECEMBER 2003 – REVISED MAY 2017
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
7
8
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Timing Requirements: TA = –40°C to +85°C ............ 6
Timing Requirements: TA = –40°C to +125°C .......... 6
Switching Characteristics: TA = –40°C to +85°C ...... 7
Switching Characteristics: TA = –40°C to +85°C ...... 7
Switching Characteristics: TA = –40°C to +125°C .. 8
Operating Characteristics........................................ 8
Typical Characteristics ............................................ 9
Parameter Measurement Information ................ 10
Detailed Description ............................................ 12
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
12
13
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application .................................................. 14
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 16
12 Device and Documentation Support ................. 17
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
17
13 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (September 2016) to Revision F
Page
•
Changed YZP Package pinout diagram and added YZP pin numbers in Pin Functions table .............................................. 3
•
Added Balanced High-Drive CMOS Push-Pull Outputs, Standard CMOS Inputs, Clamp Diodes, Partial Power Down
(Ioff), Over-voltage Tolerant Inputs ........................................................................................................................................ 12
•
Added Trace Example in Layout Example section............................................................................................................... 16
•
Added Documentation Support section ................................................................................................................................ 17
Changes from Revision D (December 2013) to Revision E
•
Page
Added Applications section, Device Information table, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
Changes from Revision C (May 2007) to Revision D
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Deleted Ordering Information table; see POA at the end of the data sheet........................................................................... 1
•
Updated operating temperature range. .................................................................................................................................. 5
2
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SCES528F – DECEMBER 2003 – REVISED MAY 2017
5 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
DCK Package
6-Pin SC70
Top View
LE
1
6
OE
GND
2
5
VCC
D
3
4
LE
1
6
OE
GND
2
5
VCC
D
3
4
Q
Q
See mechanical drawings for dimensions.
YZP Package
6-Pin DSBGA
Bottom View
1
2
C
D
Q
B
GND
VCC
A
LE
OE
Not to scale
Pin Functions
PIN
NAME
I/O
DESCRIPTION
DCK, DBV
YZP
LE
1
A1
I
GND
2
B1
—
D
3
C1
I
D latch input
Q
4
C2
O
Q latch output
VCC
5
B2
—
Positive supply
OE
6
A2
I
Latch Enable; output follows D input when high
Ground
Active low output enable; Hi-Z output when high
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
6.5
V
(2)
VI
Input voltage
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2) (3)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
TJ
Absolute maximum Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±2000
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. CDM tested on DBV
package
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SCES528F – DECEMBER 2003 – REVISED MAY 2017
6.3 Recommended Operating Conditions
(1)
See
VCC
Supply voltage
MIN
MAX
Operating
1.65
5.5
Data retention only
1.5
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
Low-level input voltage
VO
5.5
1.7
5.5
2
5.5
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VIL
0.65 × VCC
VCC = 2.3 V to 2.7 V
0.7 × VCC
5.5
VCC = 1.65 V to 1.95 V
0
0.35 × VCC
VCC = 2.3 V to 2.7 V
0
0.7
VCC = 3 V to 3.6 V
0
0.8
VCC = 4.5 V to 5.5 V
0
0.3 × VCC
0
VCC
Output voltage
VCC = 1.65 V
High-level output current
Δt/Δv
TA
(1)
Operating free-air temperature
V
mA
–24
VCC = 4.5 V
–32
VCC = 1.65 V
4
8
16
VCC = 3 V
Input transition rise or fall rate
V
–8
VCC = 3 V
Low-level output current
V
–16
VCC = 2.3 V
IOL
V
–4
VCC = 2.3 V
IOH
UNIT
mA
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
5
DSBGA package
–40
85
All other packages
–40
125
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs (SCBA004).
6.4 Thermal Information
SN74LVC1G373
THERMAL METRIC
(1)
DBV (SOT-23)
DCK (SC70)
YZP (DSBGA)
6 PINS
6 PINS
6 PINS
UNIT
219.8
255.2
131
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
189
121.9
1.3
°C/W
RθJB
Junction-to-board thermal resistance
65.8
58
22.6
°C/W
ψJT
Junction-to-top characterization parameter
67.3
7.2
5.2
°C/W
ψJB
Junction-to-board characterization parameter
65.2
57.3
22.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = –100 µA
VOH
1.65 V to 5.5 V
1.65 V
1.2
IOH = –8 mA
2.3 V
1.9
3V
IOH = –24 mA
VOL
MAX
V
2.4
2.3
IOH = –32 mA
4.5 V
IOL = 100 µA
1.65 V to 5.5 V
0.1
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
3.8
2.3 V
0.3
IOL = 16 mA
IOL= 24 mA
IOL= 32 mA
0.4
TA = –40°C to 85°C
3V
V
0.55
TA = –40°C to 125°C
0.65
TA = –40°C to 85°C
0.55
4.5 V
TA = –40°C to 125°C
0.65
II
VI = 5.5 V or GND
IOZ
VO = 0 to 5.5 V
3.6 V
±5
Ioff
VI or VO = 5.5 V
0
±10
ICC
VI = 5.5 V or GND, IO = 0
1.65 V to 5.5 V
10
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
3 V to 5.5 V
500
Ci
VI = VCC or GND
TA = –40°C to 85°C
3.3 V
3.5
Co
VO = VCC or GND
TA = –40°C to 85°C
3.3 V
6
(1)
UNIT
VCC – 0.1
IOH = –4 mA
IOH = –16 mA
TYP (1)
MIN
0 V to 5.5 V
±1
µA
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
6.6 Timing Requirements: TA = –40°C to +85°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
MIN
tw
Pulse duration, LE high
VCC = 1.8 V ± 0.15 V
tsu
th
Setup time, data before LE↓
Hold time, data after LE↓
MAX
UNIT
3
2.4
VCC = 2.5 V ± 0.2 V
2
VCC = 3.3 V ± 0.3 V
1.5
VCC = 5 V ± 0.5 V
1.5
VCC = 1.8 V ± 0.15 V
2.5
VCC = 2.5 V ± 0.2 V
1.5
VCC = 3.3 V ± 0.3 V
1.5
VCC = 5 V ± 0.5 V
1.5
ns
6.7 Timing Requirements: TA = –40°C to +125°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
MIN
tw
tsu
th
6
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
MAX
UNIT
3
VCC = 1.8 V ± 0.15 V
2.9
VCC = 2.5 V ± 0.2 V
2.1
VCC = 3.3 V ± 0.3 V
1.5
VCC = 5 V ± 0.5 V
1.5
VCC = 1.8 V ± 0.15 V
3
VCC = 2.5 V ± 0.2 V
1.5
VCC = 3.3 V ± 0.3 V
1.5
VCC = 5 V ± 0.5 V
1.5
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ns
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6.8 Switching Characteristics: TA = –40°C to +85°C
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
D
tpd
Q
LE
ten
tdis
OE
OE
Q
Q
TEST CONDITIONS
MIN
MAX
VCC = 1.8 V ± 0.15 V
2
15
VCC = 2.5 V ± 0.2 V
15
5
VCC = 3.3 V ± 0.3 V
1
4
VCC = 5 V ± 0.5 V
1
3.5
VCC = 1.8 V ± 0.15 V
2
15
VCC = 2.5 V ± 0.2 V
1.5
5
VCC = 3.3 V ± 0.3 V
1
4
VCC = 5 V ± 0.5 V
1
3.5
VCC = 1.8 V ± 0.15 V
2
12.5
VCC = 2.5 V ± 0.2 V
1.5
4.5
VCC = 3.3 V ± 0.3 V
1
4
VCC = 5 V ± 0.5 V
1
2.5
VCC = 1.8 V ± 0.15 V
2
14
VCC = 2.5 V ± 0.2 V
1.5
7
VCC = 3.3 V ± 0.3 V
1
7.9
VCC = 5 V ± 0.5 V
1
5.3
UNIT
ns
6.9 Switching Characteristics: TA = –40°C to +85°C
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
D
tpd
Q
LE
ten
tdis
OE
OE
Q
Q
TEST CONDITIONS
MIN
MAX
VCC = 1.8 V ± 0.15 V
2
16
VCC = 2.5 V ± 0.2 V
1.5
7.3
VCC = 3.3 V ± 0.3 V
1
5.4
VCC = 5 V ± 0.5 V
1
4
VCC = 1.8 V ± 0.15 V
2
16.3
VCC = 2.5 V ± 0.2 V
1.5
7.4
VCC = 3.3 V ± 0.3 V
1
5.5
VCC = 5 V ± 0.5 V
1
4
VCC = 1.8 V ± 0.15 V
2
13
VCC = 2.5 V ± 0.2 V
1.5
6.3
VCC = 3.3 V ± 0.3 V
1
5.1
VCC = 5 V ± 0.5 V
1
3.7
VCC = 1.8 V ± 0.15 V
2
17.4
VCC = 2.5 V ± 0.2 V
1
5.9
VCC = 3.3 V ± 0.3 V
1
6.5
VCC = 5 V ± 0.5 V
1
4.6
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UNIT
ns
7
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SCES528F – DECEMBER 2003 – REVISED MAY 2017
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6.10 Switching Characteristics: TA = –40°C to +125°C
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
D
tpd
Q
LE
ten
OE
tdis
Q
OE
ten
Q
OE
tdis
Q
OE
Q
TEST CONDITIONS
MIN
MAX
VCC = 1.8 V ± 0.15 V
2
17
VCC = 2.5 V ± 0.2 V
1.5
8
VCC = 3.3 V ± 0.3 V
1
6
VCC = 5 V ± 0.5 V
1
4.5
VCC = 1.8 V ± 0.15 V
2
17
VCC = 2.5 V ± 0.2 V
1.5
8
VCC = 3.3 V ± 0.3 V
1
6
VCC = 5 V ± 0.5 V
1
4.5
VCC = 1.8 V ± 0.15 V
2
13.5
VCC = 2.5 V ± 0.2 V
1.5
7
VCC = 3.3 V ± 0.3 V
1
5.5
VCC = 5 V ± 0.5 V
1
4
VCC = 1.8 V ± 0.15 V
2
18.4
VCC = 2.5 V ± 0.2 V
1
6.2
VCC = 3.3 V ± 0.3 V
1
6.8
VCC = 5 V ± 0.5 V
1
5
VCC = 1.8 V ± 0.15 V
2
14
VCC = 2.5 V ± 0.2 V
1.5
8.3
VCC = 3.3 V ± 0.3 V
0.9
6.5
VCC = 5 V ± 0.5 V
0.7
5.5
VCC = 1.8 V ± 0.15 V
2
16
VCC = 2.5 V ± 0.2 V
1.1
7.3
VCC = 3.3 V ± 0.3 V
1.4
6
VCC = 5 V ± 0.5 V
0.8
5.1
UNIT
ns
6.11 Operating Characteristics
TA = 25°C
PARAMETER
TEST CONDITIONS
Outputs enabled
Cpd
Power dissipation
capacitance
f = 10 MHz
Outputs disabled
8
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TYP
VCC = 1.8 V
19
VCC = 2.5 V
19
VCC = 3.3 V
19
VCC = 5 V
20
VCC = 1.8 V
3
VCC = 2.5 V
3
VCC = 3.3 V
3
VCC = 5 V
4
UNIT
pF
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6.12 Typical Characteristics
16
CL 30pF/50pF
CL 15pF
14
TPDMax (ns)
12
10
8
6
4
2
1.5
2
2.5
3
3.5
VCC (V)
4
4.5
5
D001
Figure 1. Propagation delay vs VCC
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
15 pF
15 pF
15 pF
15 pF
1 MW
1 MW
1 MW
1 MW
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
VM
VOL
tPHL
tPLZ
VLOAD/2
VM
tPZH
VM
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VOH
Output
VM
tPZL
tPHL
VM
Output
VI
Output
Control
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
10
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Parameter Measurement Information (continued)
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
A buffered output-enable (OE) input can be used to place the output in either a normal logic state (high or low
logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the bus
lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components. To ensure the high-impedance state during power up or power down, OE should
be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking
capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down.
8.2 Functional Block Diagram
OE
LE
6
1
C
D
3
4
Q
D
Figure 4. Logic Diagram (Positive Logic)
8.3 Feature Description
8.3.1 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and
damage due to over-current. The electrical and thermal limits defined the in the Absolute Maximum Ratings must
be followed at all times.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modelled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating
Conditions to avoid excessive currents and oscillations. If a slow or noisy input signal is required, a device with a
Schmitt-trigger input should be utilized to condition the input signal prior to the standard CMOS input.
12
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SCES528F – DECEMBER 2003 – REVISED MAY 2017
Feature Description (continued)
8.3.3 Clamp Diodes
The inputs and outputs to this device have negative clamping diodes.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
VCC
Device
Logic
Input
Output
-IIK
-IOK
GND
Figure 5. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.4 Partial Power Down (Ioff)
The inputs and outputs for this device enter a high impedance state when the supply voltage is 0 V. The
maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical
Characteristics.
8.3.5 Over-voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Absolute Maximum Ratings.
8.4 Device Functional Modes
Table 1 lists the functions of this device.
Table 1. Function Table
INPUTS
D
OUTPUT
Q
OE
LE
L
H
L
L
L
H
H
H
L
L
X
Q0
H
X
X
Hi-Z
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SCES528F – DECEMBER 2003 – REVISED MAY 2017
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC1G373 latches can be used to store one bit of data. Figure 6 shows a typical application. The
multiplexer is used to convert parallel data coming in from the latch into serial data using the A, B, and C select
pins moving up in a sequence. With latch input low by a trigger event, the output Q holds the previous Q0 data
entered until the LE pin is cleared.
9.2 Typical Application
Trigger Event LE
Live Data
Q
Y0
1
D
COM
Serial output
SN74LV4051A
8
LE
D
Q
Y7
A
B
C
Copyright © 2016, Texas Instruments Incorporated
Figure 6. Latch Used With Multiplexer for Parallel to Serial Conversion
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive also creates fast edges into light loads, so
routing and load conditions must be considered to prevent ringing.
14
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SCES528F – DECEMBER 2003 – REVISED MAY 2017
Typical Application (continued)
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– For rise time and fall time specifications, see Δt/ΔV in Recommended Operating Conditions.
– For specified High and low levels, see VIH and VIL in Recommended Operating Conditions.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommended Output Conditions
– Load currents should not exceed 32 mA per output and 100 mA total through the part.
– Outputs must not be pulled above VCC.
9.2.3 Application Curve
14
CL30pF/50pF
CL15pF
12
tENMax(ns)
10
8
6
4
2
1.5
2
2.5
3
3.5
VCC (V)
4
4.5
5
D001
Figure 7. Enable Time vs VCC
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SN74LVC1G373
SCES528F – DECEMBER 2003 – REVISED MAY 2017
www.ti.com
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
Recommended Operating Conditions.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, TI recommends a 0.1-µF bypass capacitor. If there are multiple VCC pins, TI recommends 0.01-µF or
0.022-µF bypass capacitor for each power pin. It is acceptable to parallel multiple bypass capacitors to reject
different frequencies of noise. 0.1-µF and 1-µF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 8 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient.
Even low data rate digital signals can have high frequency signal components due to fast edge rates. When a
PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the
change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. Figure 9 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
11.2 Layout Example
Vcc
Input
Unused Input
Output
Output
Unused Input
Input
Figure 8. Proper Multiple Input Termination Diagram
BETTER
BEST
2W
WORST
1W min.
W
Figure 9. Trace Example
16
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SN74LVC1G373
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SCES528F – DECEMBER 2003 – REVISED MAY 2017
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs (SCBA004)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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17
PACKAGE OPTION ADDENDUM
www.ti.com
4-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
74LVC1G373DBVRE4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(CA35, CA3R)
74LVC1G373DCKRE4
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D35
74LVC1G373DCKRG4
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D35
SN74LVC1G373DBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(CA35, CA3R)
SN74LVC1G373DCKR
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(D35, D3J, D3R)
SN74LVC1G373YZPR
ACTIVE
DSBGA
YZP
6
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
D3N
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Apr-2019
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Mar-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
74LVC1G373DCKRG4
SC70
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DCK
6
3000
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74LVC1G373DBVR
SOT-23
DBV
6
3000
178.0
9.2
3.3
3.23
1.55
4.0
8.0
Q3
SN74LVC1G373DCKR
SC70
DCK
6
3000
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74LVC1G373DCKR
SC70
DCK
6
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
SN74LVC1G373YZPR
DSBGA
YZP
6
3000
178.0
9.2
1.02
1.52
0.63
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Mar-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
74LVC1G373DCKRG4
SC70
DCK
6
3000
180.0
180.0
18.0
SN74LVC1G373DBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
SN74LVC1G373DCKR
SC70
DCK
6
3000
180.0
180.0
18.0
SN74LVC1G373DCKR
SC70
DCK
6
3000
180.0
180.0
18.0
SN74LVC1G373YZPR
DSBGA
YZP
6
3000
220.0
220.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
6
2X 0.95
1.9
1.45 MAX
3.05
2.75
5
2
4
0.50
6X
0.25
0.2
C A B
3
(1.1)
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X (0.95)
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214840/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X(0.95)
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
YZP0006
DSBGA - 0.5 mm max height
SCALE 9.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.19
0.15
BALL TYP
0.05 C
0.5 TYP
C
SYMM
1
TYP
B
0.5
TYP
D: Max = 1.418 mm, Min =1.358 mm
E: Max = 0.918 mm, Min =0.858 mm
A
6X
0.015
0.25
0.21
C A
B
1
2
SYMM
4219524/A 06/2014
NanoFree Is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
TM
3. NanoFree package configuration.
www.ti.com
EXAMPLE BOARD LAYOUT
YZP0006
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
6X ( 0.225)
1
2
A
(0.5) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
( 0.225)
METAL
0.05 MAX
METAL
UNDER
MASK
0.05 MIN
( 0.225)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4219524/A 06/2014
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017).
www.ti.com
EXAMPLE STENCIL DESIGN
YZP0006
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
6X ( 0.25)
(R0.05) TYP
2
1
A
(0.5)
TYP
SYMM
B
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4219524/A 06/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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