Texas Instruments | SNx4LVC08A Quadruple 2-Input Positive-AND Gates (Rev. T) | Datasheet | Texas Instruments SNx4LVC08A Quadruple 2-Input Positive-AND Gates (Rev. T) Datasheet

Texas Instruments SNx4LVC08A Quadruple 2-Input Positive-AND Gates (Rev. T) Datasheet
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SN54LVC08A, SN74LVC08A
SCAS283T – JANUARY 1993 – REVISED AUGUST 2019
SNx4LVC08A Quadruple 2-Input Positive-AND Gates
1 Features
2 Applications
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
Latch-Up Performance Exceeds 250 mA
Per JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
– On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include
Testing of All Parameters.
SN74LVC04A Operates From 1.65 V to 3.6 V
SN54LVC04A Operates From 2.0 V to 3.6 V
SNx4LVC08A Specified From –40°C to +85°C
and –40°C to +125°C
SN54LVC08A Specified From –55°C to +125°C
Inputs Accept Voltages to 5.5 V
Max tpd of 4.1 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
Servers
LED Displays
Network Switches
I/O Expanders
Base Station Processor Board
3 Description
The SN54LVC08A
gate is designed for
the SN74LVC08A
gate is designed for
quadruple 2-input positive-AND
2.7-V to 3.6-V VCC operation, and
quadruple 2-input positive-AND
1.65-V to 3.6-V VCC operation.
The SNx4LVC08A devices perform the Boolean
function Y + A • B or Y + A ) B in positive logic.
Inputs can be driven from either 3.3-V or 5-V devices.
This feature allows the use of these devices as
translators in a mixed 3.3-V/5-V system environment.
Device Information(1)
PACKAGE
BODY SIZE (NOM)
SNJ54LVC08AW
PART NUMBER
CFP (14)
9.21 mm × 5.97 mm
SNJ54LVC08AJ
CDIP (14)
19.56 mm × 6.92 mm
SNJ54LVC08AFK
LCCC (20)
8.89 mm × 8.89 mm
SN74LVC08ARGY
VQFN (14)
3.50 mm × 3.50 mm
SN74LVC08APW
TSSOP (14)
5.00 mm × 4.40 mm
SN74LVC08ANS
SO (14)
10.30 mm × 5.30 mm
SN74LVC08AD
SOIC (14)
8.65 mm × 3.91 mm
SN74LVC08ADB
SSOP (14)
6.20 mm × 5.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram, Each Gate
(Positive Logic)
A
B
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54LVC08A, SN74LVC08A
SCAS283T – JANUARY 1993 – REVISED AUGUST 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1 Absolute Maximum Ratings ......................................
6.2 ESD Ratings..............................................................
6.3 Recommended Operating Conditions for
SN54LVC08A ............................................................
6.4 Recommended Operating Conditions for
SN74LVC08A.............................................................
6.5 Thermal Information ..................................................
6.6 Electrical Characteristics for SN54LVC08A ..............
6.7 Electrical Characteristics for SN74LVC08A ..............
6.8 Switching Characteristics for SN54LVC08A .............
6.9 Switching Characteristics for SN74LVC08A .............
6.10 Operating Characteristics........................................
6.11 Typical Characteristics ............................................
5
5
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
11
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 14
5
11.1 Layout Guidelines ................................................. 14
11.2 Layout Examples................................................... 14
6
6
7
7
7
8
8
8
12 Device and Documentation Support ................. 15
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
13 Mechanical, Packaging, and Orderable
Information ........................................................... 15
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Related Documentation.........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
15
15
15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision S (August 2015) to Revision T
Page
•
Changed the order and content of the Features list .............................................................................................................. 1
•
Deleted Ioff throughout data sheet........................................................................................................................................... 1
•
Deleted Device Options table, see Mechanical, Packaging, and Orderable Information at the end of the data sheet ......... 1
•
Added VO > VCC to Output clamp current ............................................................................................................................... 5
•
Changed MAX value for Output clamp current, IOK and Continuous output current, IO from: –50 to: ±50 ............................. 5
•
Changed values in the Thermal Information table to align with JEDEC standards. .............................................................. 6
•
Added Balanced High-Drive CMOS Push-Pull Outputs, Standard CMOS Inputs, Clamp Diodes, and Over-voltage
Tolerant Inputs...................................................................................................................................................................... 10
•
Deleted sentence referencing "Ioff support......." in the Feature Description section. .......................................................... 10
•
Changed Inputs and Output in Truth Table ......................................................................................................................... 11
•
Added figure: Trace Example in Layout Examples .............................................................................................................. 14
•
Added Related Documentation and Receiving Notification of Documentation Updates ...................................................... 15
Changes from Revision R (June 2015) to Revision S
•
Page
Added TJ junction temperature spec to Abs Max Ratings ..................................................................................................... 5
Changes from Revision Q (November 2010) to Revision R
Page
•
Updated document to new TI data sheet format - no specification changes. ........................................................................ 1
•
Added Applications, Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature
Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ...................................................................................................................... 1
2
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SCAS283T – JANUARY 1993 – REVISED AUGUST 2019
•
Added Military Disclaimer to Features.................................................................................................................................... 1
•
Added Thermal Information table ........................................................................................................................................... 6
Copyright © 1993–2019, Texas Instruments Incorporated
Product Folder Links: SN54LVC08A SN74LVC08A
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5 Pin Configuration and Functions
D, DB, NS, J, W, or PW Package
14-Pin SOIC, SSOP, SOP, CDIP, or TSSOP
Top View
3
12
4
11
5
10
6
9
7
8
VCC
4B
4A
4Y
3B
3A
3Y
1B
1Y
2A
2B
2Y
VCC
13
1
14
2
13 4B
3
12 4A
4
11 4Y
5
10 3B
9 3A
6
7
8
3Y
14
2
1A
1
GND
1A
1B
1Y
2A
2B
2Y
GND
RGY Package
14-Pin VQFN
Top View
1B
1A
NC
VCC
4B
FK Package
20-Pin LCCC
Top View
3 2
4
1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A
NC
4Y
NC
3B
2Y
GND
NC
3Y
3A
1Y
NC
2A
NC
2B
Pin Functions
PIN
SOIC, SSOP,
SOP, CDIP,
TSSOP
LCCC
1A
1
2
I
Channel 1 input A
1B
2
3
I
Channel 1 input B
1Y
3
4
O
Channel 1 output
2A
4
6
I
Channel 2 input A
2B
5
8
I
Channel 2 input B
2Y
6
9
O
Channel 2 output
3Y
8
12
O
Channel 3 output
3A
9
13
I
Channel 3 input A
3B
10
14
I
Channel 3 input B
4Y
11
16
O
Channel 4 output
4A
12
18
I
Channel 4 input A
4B
13
19
I
Channel 4 input B
GND
7
10
Ground
NAME
TYPE
DESCRIPTION
Ground
1
5
NC (1)
—
7
11
—
No connect
15
17
VCC
(1)
4
14
20
Power
Positive supply
NC – No internal connection
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
6.5
V
(2)
–0.5
6.5
V
–0.5
VCC + 0.5
V
VI
Input voltage
VO
Output voltage (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0 or VO > VCC
±50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
(4) (5)
Ptot
Power dissipation
500
mW
TJ
Junction temperature
–65
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
(4)
(5)
TA = –40°C to +125°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
For the D package: above 70°C, the value of Ptot derates linearly with 8 mW/K.
For the DB, NS, and PW packages: above 60°C, the value of Ptot derates linearly with 5.5 mW/K.
6.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Machine Model (MM) A115-A
(1)
(2)
UNIT
V
200
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions for SN54LVC08A
See (1)
SN54LVC08A
–55°C to +125°C
Operating
MIN
MAX
2
3.6
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VCC = 2.7 V to 3.6 V
VIL
Low-level input voltage
VCC = 2.7 V to 3.6 V
0.8
V
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
(1)
Data retention only
V
1.5
2
V
VCC = 2.7 V
–12
VCC = 3 V
–24
VCC = 2.7 V
12
VCC = 3 V
24
8
mA
mA
ns/V
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
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6.4 Recommended Operating Conditions for SN74LVC08A
See (1)
SN74LVC08A
TA = 25°C
VCC
Supply voltage
VIH
High-level
input voltage
Operating
Data retention only
VCC = 1.65 V to 1.95 V
–40°C to +125°C
UNIT
MAX
MIN
MAX
MIN
MAX
1.65
3.6
1.65
3.6
1.65
3.6
1.5
1.5
1.5
0.65 × VCC
0.65 × VCC
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
1.7
1.7
VCC = 2.7 V to 3.6 V
2
2
2
VCC = 1.65 V to 1.95 V
Low-level
input voltage
VIL
–40°C to +85°C
MIN
V
V
0.35 × VCC
0.35 × VCC
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
0.7
0.7
VCC = 2.7 V to 3.6 V
0.8
0.8
0.8
V
VI
Input voltage
0
5.5
0
5.5
0
5.5
V
VO
Output voltage
0
VCC
0
VCC
0
VCC
V
High-level
output current
IOH
VCC = 1.65 V
–4
–4
–4
VCC = 2.3 V
–8
–8
–8
VCC = 2.7 V
–12
–12
–12
VCC = 3 V
–24
–24
–24
4
4
4
VCC = 1.65 V
Low-level
output current
IOL
VCC = 2.3 V
8
8
8
VCC = 2.7 V
12
12
12
VCC = 3 V
24
24
24
8
8
8
Δt/Δv Input transition rise or fall rate
(1)
mA
mA
ns/V
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
6.5 Thermal Information
SN74LVC08A
THERMAL METRIC (1)
D
(SOIC)
DB
(SSOP)
NS
(SO)
PW
(TSSOP)
RGY
(LCCC)
UNIT
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
98.6
112.8
95.1
127.7
51.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
56.0
65.3
52.7
56.0
56.6
°C/W
RθJB
Junction-to-board thermal resistance
53.3
60.2
53.9
69.5
27.5
°C/W
ψJT
Junction-to-top characterization parameter
16.4
25.3
17.9
8.9
4.5
°C/W
ψJB
Junction-to-board characterization parameter
53.0
59.6
53.6
68.9
27.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
—
—
19.1
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.6 Electrical Characteristics for SN54LVC08A
over recommended operating free-air temperature range (unless otherwise noted)
SN54LVC08A
PARAMETER
TEST CONDITIONS
VCC
–55°C to +125°C
MIN
IOH = –100 μA
VOH
3V
2.4
IOH = –24 mA
3V
2.2
IOL = 100 μA
2.7 V to 3.6 V
IOL = 12 mA
2.7 V
0.4
IOL = 24 mA
3V
0.55
VI = 5.5 V or GND
ICC
VI = VCC or GND,
IO = 0
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VCC – 0.2
2.2
II
ΔICC
UNIT
MAX
2.7 V
IOH = –12 mA
VOL
(1)
2.7 V to 3.6 V
TYP (1)
V
0.2
3.6 V
V
±5
μA
3.6 V
10
μA
2.7 V to 3.6 V
500
μA
VI = VCC or GND
3.3 V
5
pF
TA = 25°C
6.7 Electrical Characteristics for SN74LVC08A
over recommended operating free-air temperature range (unless otherwise noted)
SN74LVC08A
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
MIN
IOH = –100 μA
VOH
1.65 V to 3.6 V
UNIT
MIN MAX
VCC – 0.2
VCC – 0.3
1.65 V
1.29
1.2
1.05
2.3 V
1.9
1.7
1.55
2.7 V
2.2
2.2
2.05
3V
2.4
2.4
2.25
IOH = –24 mA
3V
2.3
2.2
2
IOL = 100 μA
V
1.65 V to 3.6 V
0.1
0.2
IOL = 4 mA
1.65 V
0.24
0.45
0.6
IOL = 8 mA
2.3 V
0.3
0.7
0.75
IOL = 12 mA
2.7 V
0.4
0.4
0.6
IOL = 24 mA
3V
0.55
0.55
0.8
3.6 V
±1
±5
±20
μA
3.6 V
1
10
40
μA
500
500
5000
μA
VI = 5.5 V or GND
ICC
VI = VCC or GND,
IO = 0
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
MIN MAX
VCC – 0.2
IOH = –8 mA
II
ΔICC
TYP MAX
–40°C to +125°C
IOH = –4 mA
IOH = –12 mA
VOL
–40°C to +85°C
2.7 V to 3.6 V
VI = VCC or GND
3.3 V
0.3
5
V
pF
6.8 Switching Characteristics for SN54LVC08A
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN54LVC08A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
–55°C to
+125°C
MIN
tpd
A or B
Y
2.7 V
3.3 V ± 0.3 V
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UNIT
MAX
4.8
1
4.1
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7
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6.9 Switching Characteristics for SN74LVC08A
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN74LVC08A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
tpd
A or B
Y
tsk(o)
–40°C to
+85°C
TA = 25°C
TYP MAX
–40°C to
+125°C
UNIT
MIN
MAX
MIN
MAX
1.8 V ± 0.15 V
1
5
9.3
1
9.8
1
11.3
2.5 V ± 0.2 V
1
2.9
6.4
1
6.9
1
9
2.7 V
1
3
4.6
1
4.8
1
6
3.3 V ± 0.3 V
1
2.6
3.9
1
4.1
1
5.5
3.3 V ± 0.3 V
1
1.5
ns
ns
6.10 Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
Power dissipation capacitance per gate
f = 10 MHz
VCC
TYP
1.8 V
7
2.5 V
9.8
3.3 V
10
UNIT
pF
6.11 Typical Characteristics
10
14
12
VCC = 3 V,
TA = 25°C
tpd – Propagation Delay Time – ns
tpd – Propagation Delay Time – ns
VCC = 3 V,
TA = 25°C
One Output Switching
Four Outputs Switching
Eight Outputs Switching
10
8
6
4
6
4
2
2
0
50
100
150
200
250
300
CL – Load Capacitance – pF
Figure 1. Propagation Delay (Low to High Transition)
vs Load Capacitance
8
One Output Switching
Four Outputs Switching
Eight Outputs Switching
8
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0
50
100
150
200
250
300
CL – Load Capacitance – pF
Figure 2. Propagation Delay (High to Low Transition)
vs Load Capacitance
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
VM
0V
VLOAD/2
VM
tPZH
VOH
Output
VM
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + VD
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VM
VOH - VD
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
Copyright © 1993–2019, Texas Instruments Incorporated
Product Folder Links: SN54LVC08A SN74LVC08A
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9
SN54LVC08A, SN74LVC08A
SCAS283T – JANUARY 1993 – REVISED AUGUST 2019
www.ti.com
8 Detailed Description
8.1 Overview
The SN74LVC08 device contains four 2-input positive AND gate device and performs the Boolean function Y = A
× B. This device is useful when multiple AND function is used in the system.
8.2 Functional Block Diagram
A
Y
B
Figure 4. Logic Diagram, Each Gate (Positive Logic)
8.3 Feature Description
8.3.1 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and
damage due to over-current. The electrical and thermal limits defined the in the Absolute Maximum Ratings must
be followed at all times.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modelled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics for SN54LVC08A and Electrical Characteristics for
SN74LVC08A. The worst case resistance is calculated with the maximum input voltage, given in the Absolute
Maximum Ratings, and the maximum input leakage current, given in theElectrical Characteristics for
SN54LVC08A and Electrical Characteristics for SN74LVC08A, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating
Conditions for SN54LVC08A and Recommended Operating Conditions for SN74LVC08A to avoid excessive
currents and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should
be utilized to condition the input signal prior to the standard CMOS input.
8.3.3 Clamp Diodes
The inputs to this device have negative clamping diodes. The outputs to this device have both positive and
negative clamping diodes as shown in Figure 5.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
10
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Product Folder Links: SN54LVC08A SN74LVC08A
SN54LVC08A, SN74LVC08A
www.ti.com
SCAS283T – JANUARY 1993 – REVISED AUGUST 2019
Feature Description (continued)
VCC
Device
+IOK
Logic
Input
-IIK
Output
-IOK
GND
Figure 5. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.4 Over-voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Absolute Maximum Ratings.
8.4 Device Functional Modes
Table 1 lists the functional modes for the SN54LVC08A and SN74LVC08A devices.
Table 1. Truth Table
INPUTS
OUTPUT
A
B
Y
L
L
L
L
H
L
H
L
L
H
H
H
Copyright © 1993–2019, Texas Instruments Incorporated
Product Folder Links: SN54LVC08A SN74LVC08A
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SN54LVC08A, SN74LVC08A
SCAS283T – JANUARY 1993 – REVISED AUGUST 2019
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC08A is used to drive CMOS device and used for implementing AND logic. The LVC family can
support current drive of about 24 mA at 3-V VCC. The inputs for SN74LVC08A are 5.5-V tolerant allowing it to
translate down to VCC.
9.2 Typical Application
A
Y
B
R
C
Figure 6. Three Input AND Gate Implementation and Driving LED
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads
so routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
SN74LVC08A contains four AND gates in one package which can be used for individual AND function or to
implement complex Boolean logic. Figure 6 shows an example of implementing 3input AND function. AB are
inputs for AND gate which are connected to another AND gate. Z= A × B × C. SN74LVC08A support high drive
current of 24 mA which can be used to drive LEDs of even Drive low current signal FETs, an example is shown
in Figure 6 TI recommends to use a series resistance to limit the current. If VCC is 3 V, and LED current should
be 10 mA, and the forward-voltage of LED is 2.5 V, then R as shown in Figure 6 is calculated using Equation 1:
R = (VCC – VLED) / I
R = (3 – 2.5) / 0.01 = 50 Ω
12
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(1)
Copyright © 1993–2019, Texas Instruments Incorporated
Product Folder Links: SN54LVC08A SN74LVC08A
SN54LVC08A, SN74LVC08A
www.ti.com
SCAS283T – JANUARY 1993 – REVISED AUGUST 2019
Typical Application (continued)
9.2.3 Application Curves
60
100
80
TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
40
TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
20
I OH – mA
I OL – mA
60
40
0
–20
–40
20
–60
0
–80
–20
–0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VOL – V
Figure 7. Output Drive Current (IOL)
vs LOW-level Output Voltage (VOL)
1.6
–100
–1
–0.5 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VOH – V
Figure 8. Output Drive Current (IOH)
vs HIGH-level Output Voltage (VOH)
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table.
The VCC pin must have a good bypass capacitor to prevent power disturbance. TI recommends to use a 0.1-µF
capacitor. It is ok to parallel multiple bypass capacitors to reject different frequencies of noise. 0.1-µF and 1-µF
capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
Copyright © 1993–2019, Texas Instruments Incorporated
Product Folder Links: SN54LVC08A SN74LVC08A
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13
SN54LVC08A, SN74LVC08A
SCAS283T – JANUARY 1993 – REVISED AUGUST 2019
www.ti.com
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 9 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient.
Even low data rate digital signals can have high frequency signal components due to fast edge rates. When a
PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the
change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. Figure 10 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
11.2 Layout Examples
VCC
Input
Unused Input
Output
Output
Unused Input
Input
Figure 9. Proper Multi-Gate Input Termination Diagram
BETTER
BEST
2W
WORST
1W min.
W
Figure 10. Trace Example
14
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Product Folder Links: SN54LVC08A SN74LVC08A
SN54LVC08A, SN74LVC08A
www.ti.com
SCAS283T – JANUARY 1993 – REVISED AUGUST 2019
12 Device and Documentation Support
12.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 2. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54LVC08A
Click here
Click here
Click here
Click here
Click here
SN74LVC08A
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
Copyright © 1993–2019, Texas Instruments Incorporated
Product Folder Links: SN54LVC08A SN74LVC08A
Submit Documentation Feedback
15
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9753401Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629753401Q2A
SNJ54LVC
08AFK
5962-9753401QCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9753401QC
A
SNJ54LVC08AJ
5962-9753401QDA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9753401QD
A
SNJ54LVC08AW
SN74LVC08AD
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC08A
SN74LVC08ADBR
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC08A
SN74LVC08ADBRE4
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC08A
SN74LVC08ADBRG4
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC08A
SN74LVC08ADE4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC08A
SN74LVC08ADG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC08A
SN74LVC08ADR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LVC08A
SN74LVC08ADRE4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC08A
SN74LVC08ADRG3
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LVC08A
SN74LVC08ADRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC08A
SN74LVC08ADT
ACTIVE
SOIC
D
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC08A
SN74LVC08ANSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC08A
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
24-Aug-2018
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LVC08ANSRE4
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC08A
SN74LVC08APW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC08A
SN74LVC08APWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC08A
SN74LVC08APWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LC08A
SN74LVC08APWRE4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC08A
SN74LVC08APWRG3
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LC08A
SN74LVC08APWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC08A
SN74LVC08APWT
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC08A
SN74LVC08APWTG4
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC08A
SN74LVC08ARGYR
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LC08A
SN74LVC08ARGYRG4
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LC08A
SNJ54LVC08AFK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629753401Q2A
SNJ54LVC
08AFK
SNJ54LVC08AJ
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9753401QC
A
SNJ54LVC08AJ
SNJ54LVC08AW
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9753401QD
A
SNJ54LVC08AW
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54LVC08A, SN74LVC08A :
• Catalog: SN74LVC08A
• Automotive: SN74LVC08A-Q1, SN74LVC08A-Q1
• Enhanced Product: SN74LVC08A-EP, SN74LVC08A-EP
• Military: SN54LVC08A
NOTE: Qualified Version Definitions:
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jun-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LVC08ADR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74LVC08ADR
SOIC
D
14
2500
330.0
16.8
6.5
9.5
2.1
8.0
16.0
Q1
SN74LVC08ADR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74LVC08ADRG3
SOIC
D
14
2500
330.0
16.8
6.5
9.5
2.1
8.0
16.0
Q1
SN74LVC08ADRG4
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74LVC08ADRG4
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74LVC08ADT
SOIC
D
14
250
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74LVC08ANSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74LVC08APWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LVC08APWRG3
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LVC08APWRG4
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LVC08APWT
TSSOP
PW
14
250
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LVC08ARGYR
VQFN
RGY
14
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jun-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC08ADR
SOIC
D
14
2500
367.0
367.0
38.0
SN74LVC08ADR
SOIC
D
14
2500
364.0
364.0
27.0
SN74LVC08ADR
SOIC
D
14
2500
333.2
345.9
28.6
SN74LVC08ADRG3
SOIC
D
14
2500
364.0
364.0
27.0
SN74LVC08ADRG4
SOIC
D
14
2500
333.2
345.9
28.6
SN74LVC08ADRG4
SOIC
D
14
2500
367.0
367.0
38.0
SN74LVC08ADT
SOIC
D
14
250
210.0
185.0
35.0
SN74LVC08ANSR
SO
NS
14
2000
367.0
367.0
38.0
SN74LVC08APWR
TSSOP
PW
14
2000
367.0
367.0
35.0
SN74LVC08APWRG3
TSSOP
PW
14
2000
364.0
364.0
27.0
SN74LVC08APWRG4
TSSOP
PW
14
2000
367.0
367.0
35.0
SN74LVC08APWT
TSSOP
PW
14
250
367.0
367.0
35.0
SN74LVC08ARGYR
VQFN
RGY
14
3000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
J0014A
CDIP - 5.08 mm max height
SCALE 0.900
CERAMIC DUAL IN LINE PACKAGE
PIN 1 ID
(OPTIONAL)
A
4X .005 MIN
[0.13]
.015-.060 TYP
[0.38-1.52]
1
14
12X .100
[2.54]
14X .014-.026
[0.36-0.66]
14X .045-.065
[1.15-1.65]
.010 [0.25] C A B
.754-.785
[19.15-19.94]
8
7
B
.245-.283
[6.22-7.19]
.2 MAX TYP
[5.08]
C
.13 MIN TYP
[3.3]
SEATING PLANE
.308-.314
[7.83-7.97]
AT GAGE PLANE
.015 GAGE PLANE
[0.38]
0 -15
TYP
14X .008-.014
[0.2-0.36]
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
www.ti.com
EXAMPLE BOARD LAYOUT
J0014A
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE
(.300 ) TYP
[7.62]
SEE DETAIL A
SEE DETAIL B
1
14
12X (.100 )
[2.54]
SYMM
14X ( .039)
[1]
8
7
SYMM
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
.002 MAX
[0.05]
ALL AROUND
(.063)
[1.6]
METAL
( .063)
[1.6]
SOLDER MASK
OPENING
METAL
(R.002 ) TYP
[0.05]
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
DETAIL A
DETAIL B
SCALE: 15X
13X, SCALE: 15X
4214771/A 05/2017
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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