Texas Instruments | SN74LVC2G125 Dual Bus Buffer Gate With 3-State Outputs (Rev. Q) | Datasheet | Texas Instruments SN74LVC2G125 Dual Bus Buffer Gate With 3-State Outputs (Rev. Q) Datasheet

Texas Instruments SN74LVC2G125 Dual Bus Buffer Gate With 3-State Outputs (Rev. Q) Datasheet
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SN74LVC2G125
SCES204Q – APRIL 1999 – REVISED MARCH 2017
SN74LVC2G125 Dual Bus Buffer Gate With 3-State Outputs
1 Features
3 Description
•
The SN74LVC2G125 device is a dual bus buffer
gate, designed for 1.65-V to 5.5-V VCC operation.
This device features dual line drivers with 3-state
outputs. The outputs are disabled when the
associated output-enable (OE) input is high.
1
•
•
•
•
•
•
•
•
•
•
•
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 1000-V Charged-Device Model
Available in the Texas Instruments
NanoFree™ Package
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 4.3 ns at 3.3 V
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate
Inputs From a Max of 5.5 V Down
to the VCC Level
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
2 Applications
•
•
•
•
•
•
•
•
•
Cable Modem Termination Systems
High-Speed Data Acquisition and Generation
Military: Radars and Sonars
Motor Controls: High-Voltage
Power Line Communication Modems
SSDs: Internal or External
Video Broadcasting and Infrastructure: Scalable
Platforms
Video Broadcasting: IP-Based Multi-Format
Transcoders
Video Communications Systems
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
To ensure the high-impedance state during power up
or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE
SN74LVC2G125DCTR
SM8 (8)
2.95 mm × 2.80 mm
SN74LVC2G125DCUR
VSSOP (8)
2.30 mm × 2.00 mm
SN74LVC2G125YZPR
DSBGA (8)
1.91 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
1 OE
1A
1Y
2 OE
2A
2Y
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC2G125
SCES204Q – APRIL 1999 – REVISED MARCH 2017
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
5
5
6
6
7
7
7
8
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics: TA = –40°C to +85°C ......
Switching Characteristics: TA = –40°C to +125°C ....
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 11
9
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 14
12 Device and Documentation Support ................. 15
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
15
15
13 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision P (January 2016) to Revision Q
Page
•
Removed '200-V Machine Model' from Features for consistency with ESD ratings table. ................................................... 1
•
Added orderable part numbers associated with each package. Changed US8 to VSSOP. .................................................. 1
•
Updated YZP package drawing to match mechanical drawing pinout. ................................................................................. 4
•
Added YZP pin identifiers to Pin Function table. Added 'buffer #' to Description for pins 2, 3, 5, and 6. Changed
'Power pin' to 'Positive supply'................................................................................................................................................ 4
•
Added updated package thermal values based on new models. Changes: RθJA DCT 220 -> 199.0, DCU 227 ->
217.8, YZP 102 -> 99.8. Added: RθJCtop, RθJB, ψJT, ψJB........................................................................................................... 6
•
Added 'Balanced Push-Pull Outputs,' 'CMOS Inputs,' 'Clamp Diodes,' 'Partial Power Down, 'Over-voltage Tolerant
Inputs.' Removed bullet list................................................................................................................................................... 10
•
Added improved layout guidelines and trace example image. ............................................................................................ 13
•
Added Documentation Support section, Receiving Notification of Documentation Updates section, and Community
Resources section ................................................................................................................................................................ 15
Changes from Revision O (January 2015) to Revision P
Page
•
Added overbar for active low to 1OE and 2OE to the Simplified Schematic.......................................................................... 1
•
Added TJ Junction temperature to the Absolute Maximum Ratings ...................................................................................... 5
•
Added overbar for active low to 1OE and 2OE to the Functional Block Diagram................................................................ 10
Changes from Revision N (November 2013) to Revision O
•
2
Page
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
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Changes from Revision M (January 2007) to Revision N
Page
•
Updated Features. .................................................................................................................................................................. 1
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Removed Ordering Information table. .................................................................................................................................... 1
•
Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ......................................... 6
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5 Pin Configuration and Functions
DCT PACKAGE
(TOP VIEW)
DCU PACKAGE
(TOP VIEW)
1OE
1
8
VCC
1A
2
7
2OE
2Y
3
6
1Y
GND
4
5
2A
1OE
1A
2Y
GND
1
8
VCC
2
7
3
6
4
5
2OE
1Y
2A
See mechanical drawings for dimensions.
YZP Package
8-Pin DSBGA
Bottom View
1
2
D
GND
2A
C
2Y
1Y
B
1A
2OE
A
1OE
VCC
Not to scale
See mechanical drawings for dimensions.
Pin Functions
PIN
NAME
TYPE
DESCRIPTION
DCT, DCU
YZP
1A
2
B1
I
Input of buffer 1
2A
5
D2
I
Input of buffer 2
1OE
1
A1
I
Output Enable for buffer 1
2OE
7
B2
I
Output Enable for buffer 2
1Y
6
C2
O
Output of buffer 1
2Y
3
C1
O
Output of buffer 2
GND
4
D1
—
Ground
VCC
8
A2
—
Positive supply
4
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6 Specifications
6.1 Absolute Maximum Ratings
See (1)
VCC
Supply voltage
(2)
MIN
MAX
UNIT
–0.5
6.5
V
VI
Input voltage
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over recommended operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
MIN
MAX
Operating
1.65
5.5
Data retention only
1.5
VCC = 1.65 V to 1.95 V
VIH
1.7
VCC = 3 V to 3.6 V
0.7 × VCC
VCC = 1.65 V to 1.95 V
Low-level input voltage
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VCC = 4.5 V to 5.5 V
VI
Output voltage
0
5.5
High or low state
0
VCC
3-state
0
5.5
VCC = 1.65 V
High-level output current
VCC = 3 V
Low-level output current
Δt/Δv
TA
(1)
mA
–24
VCC = 4.5 V
–32
VCC = 1.65 V
4
8
16
VCC = 3 V
Input transition rise or fall rate
V
–8
–16
VCC = 2.3 V
IOL
V
–4
VCC = 2.3 V
IOH
V
0.3 × VCC
Input voltage
VO
V
2
VCC = 4.5 V to 5.5 V
VIL
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
High-level input voltage
UNIT
mA
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
5
Operating free-air temperature
–40
125
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
6.4 Thermal Information
SN74LVC2G125
THERMAL METRIC (1)
DCT (SM8)
DCU (VSSOP) YZP (DSBGA)
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
199.0
217.8
99.8
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
89.5
98.3
1.0
°C/W
RθJB
Junction-to-board thermal resistance
118.7
138.7
29.6
°C/W
ψJT
Junction-to-top characterization parameter
14.3
34.6
0.5
°C/W
ψJB
Junction-to-board characterization parameter
117.4
138.2
29.8
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
IOH = –8 mA
IOH = –16 mA
VCC – 0.1
1.2
1.2
1.8 V
1.4
2.3 V
1.9
1.9
2.4
2.4
2.3
2.3
3.8
MAX
UNIT
V
IOL = 100 µA
1.65 V to 5.5 V
0.1
0.1
1.65 V
0.45
0.45
1.8 V
0.45
2.3 V
0.3
0.3
0.4
0.4
0.55
0.55
0.55
0.75
0 to 5.5 V
±5
±5
µA
IOL = 16 mA
3.8
3V
IOL = 24 mA
IOL = 32 mA
II
VCC – 0.1
TYP (1)
4.5 V
IOL = 8 mA
A or OE
inputs
MIN
IOH = –32 mA
IOL = 4 mA
VOL
TA = –40°C to +125°C
MAX
1.65 V
3V
IOH = –24 mA
TYP (1)
MIN
1.65 V to 5.5 V
IOH = –4 mA
VOH
TA = –40°C to +85°C
VCC
4.5 V
VI = 5.5 V or GND
V
Ioff
VI or VO = 5.5 V
0
±10
±10
µA
IOZ
VO = 0 to 5.5 V
3.6 V
10
10
µA
ICC
VI = 5.5 V or GND,
1.65 V to 5.5 V
10
10
µA
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
3 V to 5.5 V
500
500
µA
Ci
Data inputs
Control inputs
Co
(1)
IO = 0
VI = VCC or GND
3.3 V
VO = VCC or GND
3.3 V
3.5
3.5
4
4
6.5
6.5
pF
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
6.6 Switching Characteristics: TA = –40°C to +85°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
TA = –40°C to +85°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tpd
A
Y
3.3
9.1
1.5
4.8
1.4
4.3
1
3.7
ns
ten
OE
Y
4
9.9
1.9
5.6
1.2
4.7
1.2
3.8
ns
tdis
OE
Y
1.5
11.6
1
5.8
1.4
4.6
1
3.4
ns
UNIT
6.7 Switching Characteristics: TA = –40°C to +125°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
TA = –40°C to +125°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tpd
A
Y
3.3
10.1
1.5
5.8
1.4
5.3
1
4.2
ns
ten
OE
Y
4
10.9
1.9
6.6
1.2
5.7
1.2
4.3
ns
tdis
OE
Y
1.5
12.6
1
6.8
1.4
5.6
1
3.9
ns
UNIT
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6.8 Operating Characteristics
TA = 25°
TEST
CONDITIONS
PARAMETER
Power dissipation
capacitance
Cpd
Outputs enabled
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
19
19
20
22
2
2
2
3
f = 10 MHz
Outputs disabled
UNIT
pF
6.9 Typical Characteristics
2.5
5
TPD
2
4
1.5
3
TPD - ns
TPD - ns
TPD
1
0.5
2
1
0
-100
0
-50
0
50
Temperature - °C
100
150
0
1
D001
Figure 1. TPD Across Temperature at 3.3 V VCC
8
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2
3
Vcc - V
4
5
6
D002
Figure 2. TPD Across VCC at 25°C
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
VM
VOL
tPHL
VM
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74LVC2G125 device contains dual buffer gate device with output enable control and performs the
Boolean function Y = A. This device is fully specified for partial-power-down applications using Ioff. The Ioff
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a
pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
8.2 Functional Block Diagram
1 OE
1A
1Y
2 OE
2A
2Y
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8.3 Feature Description
8.3.1 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and
damage due to over-current. The electrical and thermal limits defined the in the Absolute Maximum Ratings must
be followed at all times.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modelled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings , and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating
Conditions to avoid excessive currents and oscillations. If a slow or noisy input signal is required, a device with a
Schmitt-trigger input should be utilized to condition the input signal prior to the standard CMOS input.
8.3.3 Clamp Diodes
The inputs and outputs to this device have negative clamping diodes.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
10
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Feature Description (continued)
VCC
Device
Logic
Input
-IIK
Output
-IOK
GND
Figure 4. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.4 Partial Power Down (Ioff)
The inputs and outputs for this device enter a high impedance state when the supply voltage is 0 V. The
maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical
Characteristics.
8.3.5 Over-voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Absolute Maximum Ratings .
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74LVC2G125.
Table 1. Function Table
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC2G125 device is a high drive CMOS device that can be used as a output enabled buffer with a
high output drive, such as an LED application. It can produce 24 mA of drive current at 3.3 V making it Ideal for
driving multiple outputs and good for high speed applications up to 100 MHz. The inputs are 5.5-V tolerant
allowing it to translate down to VCC.
9.2 Typical Application
1.65 V to 5 V
SN74LVC2G125
Output 2 to long
PCB trace or
high-Z logic input
Input signal 1
from system
1OE
VCC
1A
2OE
2Y
1Y
GND
2A
0.1 μF
Input signal 2
from system
Output 1 to long
PCB trace or
high-Z logic input
Copyright © 2017, Texas Instruments Incorporated
Figure 5. Typical Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive also creates fast edges into light loads so
routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For rise time and fall time specifications, see (Δt/ΔV) in the Recommended Operating Conditions table.
– For specified high and low levels, see (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC.
2. Recommended Output Conditions:
– Load currents should not exceed (IO max) per output and should not exceed (Continuous current through
VCC or GND) total current for the part. These limits are located in the Absolute Maximum Ratings table.
– Outputs should not be pulled above VCC.
12
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Copyright © 1999–2017, Texas Instruments Incorporated
Product Folder Links: SN74LVC2G125
SN74LVC2G125
www.ti.com
SCES204Q – APRIL 1999 – REVISED MARCH 2017
Typical Application (continued)
9.2.3 Application Curve
10
VCC
VCC
VCC
VCC
9
8
1.8 V
2.5 V
3.3 V
5V
ICC (mA)
7
6
5
4
3
2
1
0
0
20
40
Frequency (MHz)
60
80
D003
Figure 6. ICC vs Frequency
10 Power Supply Recommendations
The power supply can be any voltage between the min and max supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply a 0.1-μF capacitor is recommended and if there are multiple VCC pins then a 0.01-μF or 0.022-μF
capacitor is recommended for each power pin. It is ok to parallel multiple bypass caps to reject different
frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be
installed as close to the power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient.
Even low data rate digital signals can have high frequency signal components due to fast edge rates. When a
PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the
change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. Figure 8 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
Submit Documentation Feedback
Copyright © 1999–2017, Texas Instruments Incorporated
Product Folder Links: SN74LVC2G125
13
SN74LVC2G125
SCES204Q – APRIL 1999 – REVISED MARCH 2017
www.ti.com
11.2 Layout Example
VCC
Input
Unused Input
Output
Output
Unused Input
Input
Figure 7. Proper multi-gate input termination diagram
BETTER
BEST
2W
WORST
1W min.
W
Figure 8. Trace Example
14
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Copyright © 1999–2017, Texas Instruments Incorporated
Product Folder Links: SN74LVC2G125
SN74LVC2G125
www.ti.com
SCES204Q – APRIL 1999 – REVISED MARCH 2017
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 1999–2017, Texas Instruments Incorporated
Product Folder Links: SN74LVC2G125
15
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
74LVC2G125DCTRE4
ACTIVE
SM8
DCT
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C25
(R, Z)
74LVC2G125DCTRE6
ACTIVE
SM8
DCT
8
3000
Pb-Free
(RoHS)
CU SNBI
Level-1-260C-UNLIM
-40 to 125
C25
Z
74LVC2G125DCTRG4
ACTIVE
SM8
DCT
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C25
(R, Z)
74LVC2G125DCURE4
ACTIVE
VSSOP
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C25R
74LVC2G125DCURG4
ACTIVE
VSSOP
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C25R
74LVC2G125DCUTG4
ACTIVE
VSSOP
DCU
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C25R
SN74LVC2G125DCT3
ACTIVE
SM8
DCT
8
3000
Pb-Free
(RoHS)
CU SNBI
Level-1-260C-UNLIM
-40 to 125
C25
Z
SN74LVC2G125DCTR
ACTIVE
SM8
DCT
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C25
(R, Z)
SN74LVC2G125DCU3
ACTIVE
VSSOP
DCU
8
3000
Pb-Free
(RoHS)
CU SNBI
Level-1-260C-UNLIM
-40 to 125
25
CZ
SN74LVC2G125DCUR
ACTIVE
VSSOP
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(25, C25Q, C25R)
CZ
SN74LVC2G125DCUT
ACTIVE
VSSOP
DCU
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(C25Q, C25R)
SN74LVC2G125YZPR
ACTIVE
DSBGA
YZP
8
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
(CM7, CMN)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2018
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC2G125 :
• Automotive: SN74LVC2G125-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Sep-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
74LVC2G125DCTRE6
SM8
DCT
8
3000
180.0
13.0
3.35
4.5
1.55
4.0
12.0
Q3
74LVC2G125DCURG4
VSSOP
DCU
8
3000
180.0
8.4
2.25
3.35
1.05
4.0
8.0
Q3
74LVC2G125DCUTG4
VSSOP
DCU
8
250
180.0
8.4
2.25
3.35
1.05
4.0
8.0
Q3
SN74LVC2G125DCT3
SM8
DCT
8
3000
180.0
13.0
3.35
4.5
1.55
4.0
12.0
Q3
SN74LVC2G125DCTR
SM8
DCT
8
3000
180.0
13.0
3.35
4.5
1.55
4.0
12.0
Q3
SN74LVC2G125DCUR
VSSOP
DCU
8
3000
180.0
9.0
2.05
3.3
1.0
4.0
8.0
Q3
SN74LVC2G125YZPR
DSBGA
YZP
8
3000
178.0
9.2
1.02
2.02
0.63
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Sep-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
74LVC2G125DCTRE6
SM8
DCT
8
3000
182.0
182.0
20.0
74LVC2G125DCURG4
VSSOP
DCU
8
3000
202.0
201.0
28.0
74LVC2G125DCUTG4
VSSOP
DCU
8
250
202.0
201.0
28.0
SN74LVC2G125DCT3
SM8
DCT
8
3000
182.0
182.0
20.0
SN74LVC2G125DCTR
SM8
DCT
8
3000
182.0
182.0
20.0
SN74LVC2G125DCUR
VSSOP
DCU
8
3000
182.0
182.0
20.0
SN74LVC2G125YZPR
DSBGA
YZP
8
3000
220.0
220.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
8
0,13 M
5
0,15 NOM
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
1
0,25
4
0° – 8°
3,15
2,75
0,60
0,20
1,30 MAX
Seating Plane
0,10
0,10
0,00
NOTES: A.
B.
C.
D.
4188781/C 09/02
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion
Falls within JEDEC MO-187 variation DA.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OUTLINE
YZP0008
DSBGA - 0.5 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.19
0.15
0.05 C
BALL TYP
0.5 TYP
D
C
SYMM
1.5
TYP
0.5
TYP
8X
0.015
D: Max = 1.918 mm, Min =1.858 mm
B
0.25
0.21
C A B
E: Max = 0.918 mm, Min =0.858 mm
A
1
2
SYMM
4223082/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YZP0008
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
8X ( 0.23)
2
1
A
(0.5) TYP
B
SYMM
C
D
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
SOLDER MASK
OPENING
0.05 MAX
( 0.23)
SOLDER MASK
OPENING
0.05 MIN
( 0.23)
METAL
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4223082/A 07/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YZP0008
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
8X ( 0.25)
(R0.05) TYP
1
2
A
(0.5)
TYP
B
SYMM
C
METAL
TYP
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4223082/A 07/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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