Texas Instruments | SN74LVC126A Quadruple Bus Buffer Gate With 3-State Outputs (Rev. S) | Datasheet | Texas Instruments SN74LVC126A Quadruple Bus Buffer Gate With 3-State Outputs (Rev. S) Datasheet

Texas Instruments SN74LVC126A Quadruple Bus Buffer Gate With 3-State Outputs (Rev. S) Datasheet
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SN74LVC126A
SCAS339S – MARCH 1994 – REVISED FEBRUARY 2017
SN74LVC126A Quadruple Bus Buffer Gate With 3-State Outputs
1 Features
3 Description
•
•
•
•
•
The SN74LVC126A device is a quadruple bus buffer
gate designed for 1.65-V to 3.6-V VCC operation.
1
•
•
Operates From 1.65 V to 3.6 V
Specified From –40°C to +125°C
Inputs Accept Voltages up to 5.5 V
Maximum tpd of 4.7 ns at 3.3 V
Typical VOLP (Output Ground Bounce),
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot),
>2 V at VCC = 3.3 V, TA = 25°C
Latch-Up Performance Exceeds 250 mA
Per JESD 17
The SN74LVC126A device features independent line
drivers with 3-state outputs. Each output is disabled
when the associated output-enable (OE) input is low.
To ensure the high-impedance state during power up
or power down, OE must be tied to GND through a
pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
2 Applications
•
•
•
•
•
•
•
•
•
•
•
AV Receivers
Audio Docks: Portable
Blu-ray Players and Home Theaters
MP3 Players or Recorders
Personal Digital Assistants (PDAs)
Power: Telecom, Server, and AC-DC Supplies
(Single-Controller, Analog, and Digital)
Solid State Drives (SSDs): Client and Enterprise
TVs: LCD, Digital, and High-Definition (HDTV)
Tablets: Enterprise
Video Analytics: Server
Wireless Headsets, Keyboards, and Mice
Inputs can be driven from either 3.3-V or 5-V devices.
This feature allows the use of this device as a
translator in a mixed 3.3-V and 5-V system
environment.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LVC126A-DR
SOIC (14)
8.65 mm × 3.91 mm
SN74LVC126A-DBR
SSOP (14)
6.20 mm × 5.30 mm
SN74LVC126A-DGVR
TVSOP (14)
3.60 mm × 4.40 mm
SN74LVC126A-NSR
SOP (14)
10.20 mm × 5.30 mm
SN74LVC126A-PWR
TSSOP (14)
5.00 mm × 4.40 mm
SN74LVC126A-RGYR
VQFN (14)
3.50 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
1OE
1A
2OE
2A
1
2
3OE
3
1Y
4
5
3A
4OE
6
2Y
4A
10
9
8
3Y
13
12
11
4Y
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC126A
SCAS339S – MARCH 1994 – REVISED FEBRUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
7
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description ................................................ 11
8.4 Device Functional Modes ....................................... 11
9
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application .................................................. 12
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example .................................................... 14
12 Device and Documentation Support ................. 15
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
15
15
13 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision R (October 2016) to Revision S
•
Page
Changed pin descriptions to match function in Pin Functions table....................................................................................... 3
Changes from Revision Q (July 2005) to Revision R
Page
•
Added Applications section, ESD Ratings table, Thermal Information table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ...... 1
•
Deleted Ordering Information table; see POA at the end of the data sheet........................................................................... 1
•
Changed temperature rating for VQFN package From: –40°C to 85°C To: –40°C to +125°C throughout the data sheet .... 1
•
Changed values in the Thermal Information table: 86 to 98.4 for (D), 96 to 112.2 for (DB), 127 to 140.9 for (DGV),
76 to 93.9 for (NS), 113 to 127.7 for (PW), 47 to 35 for (RGY) ............................................................................................. 5
2
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SCAS339S – MARCH 1994 – REVISED FEBRUARY 2017
5 Pin Configuration and Functions
D, DB, DGV, NS, or PW Package
14-Pin SOIC, SSOP, TVSOP, SOP, or TSSOP
Top View
13
3
12
4
11
5
10
6
9
7
8
VCC
4OE
4A
4Y
3OE
3A
3Y
1A
1Y
2OE
2A
2Y
VCC
2
1
14
2
13 4OE
3
12 4A
4
11 4Y
5
10 3OE
9 3A
6
7
8
3Y
14
1OE
1
GND
1OE
1A
1Y
2OE
2A
2Y
GND
RGY Package
14-Pin VQFN With Thermal Pad
Top View
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
1OE
I
Output enable 1
2
1A
I
Gate 1 input
3
1Y
O
Gate 1 output
4
2OE
I
Output enable 2
5
2A
I
Gate 2 input
6
2Y
O
Gate 2 output
7
GND
—
Ground pin
8
3Y
O
Gate 3 output
9
3A
I
Gate 3 input
10
3OE
I
Output enable 3
11
4Y
O
Gate 4 output
12
4A
I
Gate 4 input
13
4OE
I
Output Enable 4
14
VCC
—
Power pin
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage, VCC
Input voltage, VI
(2)
Output voltage, VO (2) (3)
MIN
MAX
UNIT
–0.5
6.5
V
–0.5
6.5
V
–0.5
VCC + 0.5
V
Input clamp current, IIK
VI < 0
–50
mA
Output clamp current, IOK
VO < 0
–50
mA
Continuous output current, IO
±50
mA
Continuous current through VCC or GND
±100
mA
500
mW
150
°C
150
°C
Power dissipation, Ptot
TA = –40°C to +125°C
(4) (5)
Maximum junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
(3)
(4)
(5)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in Recommended Operating Conditions.
For the D package: above 70°C, the value of Ptot derates linearly with 8 mW/K.
For the DB, NS, and PW packages: above 60°C, the value of Ptot derates linearly with 5.5 mW/K.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. This rating was
tested on the D (SOIC) package.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. This rating was
tested on the D (SOIC) package.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VCC
Supply voltage
VIH
High-level input voltage
Operating
Data retention only
VCC = 1.65 V to 1.95 V
1.65
Low-level input voltage
MAX
3.6
1.5
UNIT
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
VCC = 1.65 V to 1.95 V
VIL
NOM
V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
0.8
V
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
VCC = 1.65 V
IOH
(1)
4
High-level output current
–4
VCC = 2.3 V
–8
VCC = 2.7 V
–12
VCC = 3 V
–24
mA
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs.
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)(1)
MIN
NOM
MAX
VCC = 1.65 V
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
UNIT
4
VCC = 2.3 V
8
VCC = 2.7 V
12
VCC = 3 V
24
–40
mA
10
ns/V
125
°C
6.4 Thermal Information
SN74LVC126A
THERMAL METRIC (1)
D (SOIC)
DB (SSOP)
DGV (TVSOP)
NS (SOP)
PW (TSSOP)
RGY (VQFN)
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
(2)
(2)
RθJA
Junction-to-ambient thermal
resistance
RθJC(top)
Junction-to-case (top) thermal
resistance
58.2
64.2
59.9
51.7
RθJB
Junction-to-board thermal
resistance
52.6
59.6
70.2
ψJT
Junction-to-top characterization
parameter
24.1
28.3
ψJB
Junction-to-board
characterization parameter
52.4
59.1
(1)
(2)
(3)
98.4
(2)
112.2
35 (3)
°C/W
56
43.6
°C/W
52.7
69.5
11.6
°C/W
9.1
20.7
8.9
0.4
°C/W
69.5
52.3
68.9
11.8
°C/W
140.9
93.9
(2)
127.7
(2)
UNIT
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The package thermal impedance is calculated in accordance with JESD 51-7.
The package ther mal impedance is calculated in accordance with JESD 51-5.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA, VCC = 1.65 V to 3.6 V
MIN
TA = 25°C
VCC – 0.2
TA = –40°C to +125°C
VCC – 0.3
TA = 25°C
IOH = –4 mA, VCC = 1.65 V
VOH
VCC = 2.7 V
1.2
TA = –40°C to +125°C
1.05
IOH = –12 mA
VCC = 3 V
IOH = –24 mA, VCC = 3 V
1.7
TA = –40°C to +125°C
1.55
TA = –40°C to +125°C
TA = 25°C
TA = –40°C to +125°C
2.2
2.4
2.25
2.3
TA = –40°C to +85°C
2.2
2
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V
2.05
TA = 25°C
TA = –40°C to +125°C
UNIT
1.9
TA = –40°C to +85°C
TA = 25°C
MAX
1.29
TA = –40°C to +85°C
TA = 25°C
IOH = –8 mA, VCC = 2.3 V
TYP
5
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Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOL = 100 µA, VCC = 1.65 V to 3.6 V
IOL = 4 mA, VCC = 1.65 V
VOL
IOL = 8 mA, VCC = 2.3 V
TYP
0.1
TA = –40°C to +85°C
0.2
TA = –40°C to +125°C
0.3
TA = 25°C
0.24
TA = –40°C to +85°C
0.45
TA = –40°C to +125°C
0.6
TA = 25°C
0.3
TA = –40°C to +85°C
0.7
TA = –40°C to +125°C
0.75
0.55
TA = –40°C to +125°C
0.8
TA = 25°C
±1
TA = –40°C to +85°C
±5
TA = –40°C to +125°C
±20
TA = 25°C
IOZ
VO = VCC or GND, VCC = 3.6 V
VI = VCC or GND, IO = 0, VCC = 3.6 V
ΔICC
One input at VCC – 0.6 V, other inputs at VCC or
GND, VCC = 2.7 V to 3.6 V
Ci
VI = VCC or GND, VCC = 3.3 V
Co
VO = VCC or GND, VCC = 3.3 V
Cpd
6
Power
dissipation
capacitance
per gate
Outputs
enabled
f = 10 MHz, TA = 25°C
Outputs
disabled
TA = –40°C to +85°C
±10
TA = –40°C to +125°C
±20
µA
1
TA = –40°C to +85°C
10
TA = –40°C to +125°C
40
TA = 25°C
500
TA = –40°C to +125°C
5000
µA
µA
4.5
pF
7
pF
VCC = 1.8 V
20
VCC = 2.5 V
21
VCC = 3.3 V
22
VCC = 1.8 V
2
VCC = 2.5 V
3
VCC = 3.3 V
4
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µA
±1
TA = 25°C
ICC
V
0.6
TA = 25°C
VI = 5.5 V or GND, VCC = 3.6 V
UNIT
0.4
TA = –40°C to +125°C
IOL = 24 mA, VCC = 3 V
MAX
TA = 25°C
TA = 25°C
IOL = 12 mA, VCC = 2.7 V
II
MIN
pF
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6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted; see Parameter Measurement Information)
PARAMETER
TEST CONDITIONS
TA = 25°C
VCC = 1.8 V ± 0.15 V
tpd
From A (input) to Y (output)
ten
From OE (input) to Y (output)
2.7
9.3
1
2.9
5
TA = –40°C to
+85°C
5.2
TA = –40°C to
+125°C
6.5
1
2.5
4.7
TA = –40°C to
+125°C
6
4.8
9.5
TA = –40°C to
+85°C
10
TA = –40°C to
+125°C
11.5
1
2.8
7.8
TA = –40°C to
+85°C
8.3
TA = –40°C to
+125°C
10.4
1
3.1
6.1
TA = –40°C to
+85°C
6.3
TA = –40°C to
+125°C
8
1
2.5
5.7
TA = –40°C to
+125°C
7.5
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ns
5.5
TA = –40°C to
+85°C
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ns
4.5
TA = –40°C to
+85°C
1
UNIT
6.7
TA = –40°C to
+125°C
TA = 25°C
VCC = 3.3 V ± 0.3 V
1
7.2
TA = 25°C
VCC = 2.7 V
9.3
TA = –40°C to
+85°C
TA = 25°C
VCC = 2.5 V ± 0.2 V
4.2
11.3
TA = 25°C
VCC = 1.8 V ± 0.15 V
1
TA = –40°C to
+125°C
TA = 25°C
VCC = 3.3 V ± 0.3 V
MAX
9.8
TA = 25°C
VCC = 2.7 V
TYP
TA = –40°C to
+85°C
TA = 25°C
VCC = 2.5 V ± 0.2 V
MIN
7
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Switching Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted; see Parameter Measurement Information)
PARAMETER
TEST CONDITIONS
TA = 25°C
VCC = 1.8 V ± 0.15 V
tdis
From OE (input) to Y (output)
tsk(o)
8
VCC = 3.3 V ± 0.3 V
1
4.4
12.1
TA = –40°C to
+125°C
14.1
1
2.7
8.7
TA = –40°C to
+125°C
10.8
1
2.7
6.5
TA = –40°C to
+85°C
6.7
TA = –40°C to
+125°C
8.5
1.3
2.3
ns
5.8
TA = –40°C to
+85°C
6
TA = –40°C to
+125°C
7.5
TA = –40°C to
+85°C
1
TA = –40°C to
+125°C
1.5
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UNIT
8.2
TA = –40°C to
+85°C
TA = 25°C
VCC = 3.3 V ± 0.3 V
MAX
12.6
TA = 25°C
VCC = 2.7 V
TYP
TA = –40°C to
+85°C
TA = 25°C
VCC = 2.5 V ± 0.2 V
MIN
ns
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6.7 Typical Characteristics
TA = 25°C
8
7
6
TPD (ns)
5
4
3
2
1
TPD
0
1.5
2.0
2.5
3.0
3.5
4.0
VCC Input (V)
C001
Figure 1. TPD vs VCC
7 Parameter Measurement Information
VLOAD
From Output
Under Test
CL
(see Note A)
S1
RL
Open
GND
RL
Figure 2. Load Circuit
Table 1. Timing Test Conditions
TEST
S1
tPLH and tPHL
Open
tPLZ and tPZL
VLOAD
tPHZ and tPZH
GND
Table 2. Electrical Characteristics Test Conditions
VCC
INPUTS
VM
VLOAD
CL
≤2 ns
VCC/2
2 × VCC
≤2 ns
VCC/2
2 × VCC
2.7 V
≤2.5 ns
1.5 V
2.7 V
≤2.5 ns
1.5 V
VI
tr/tf
1.8 V ± 0.15 V
VCC
2.5 V ± 0.2 V
VCC
2.7 V
3.3 V ± 0.3 V
RL
VΔ
30 pF
1 kΩ
0.15 V
30 pF
500 Ω
0.15 V
6V
50 pF
500 Ω
0.3 V
6V
50 pF
500 Ω
0.3 V
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tw
VI
Input
VM
Figure 3. Voltage Waveforms,
Pulse Duration
VI
Timing Input
VM
0V
t su
th
0V
VM
t PZL
Output
Waveform 1
S1 at VLOAD
(see Note B)
VM
VOH - VD
VOH
≈0 V
C.
All input pulses are supplied by generators
having the following characteristics: PRR ≤
10 MHz, ZO = 50 Ω.
D.
The outputs are measured one at a time,
with one transition per measurement.
E.
tPLZ and tPHZ are the same as tdis.
F.
tPZL and tPZH are the same as ten.
G.
tPLH and tPHL are the same as tpd.
H.
VOH
All parameters and waveforms are not
applicable to all devices.
VOL
Figure 6. Voltage Waveforms, Enable and Disable
Times Low- and High-Level Enabling
t PHL
VOH
VM
VOL
t PLH
VM
t PHZ
Waveform 1 is for an output with internal
conditions such that the output is low,
except when disables by the output control.
Waveform 2 is for an output with internal
conditions such that the output is high,
except when disabled by the output control.
0V
t PHL
VOL
CL includes probe and jig capacitance.
VI
VM
VOL + VD
B.
VM
VM
t PLH
VLOAD /2
t PZH
Figure 4. Voltage Waveforms,
Setup and Hold Times
VM
t PLZ
VM
Output
Waveform 2
S1 at GND
(see Note B)
0V
Output
VM
A.
VI
Data Input
Output
VM
VM
0V
Input
VI
Output
Control
VM
Figure 5. Voltage Waveforms, Propagation Delay
Times Inverting and Noninverting Outputs
10
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8 Detailed Description
8.1 Overview
The SN74LVC126A quadruple buffer is designed for 1.65-V to 3.6-V VCC operation and features tri-state outputs.
The SN74LVC126A devices perform the Boolean function Y = A in positive logic.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as downtranslators in a mixed 3.3-V or 5-V system environment.
8.2 Functional Block Diagram
1OE
1A
2OE
2A
1
3OE
2
3
1Y
3A
4
4OE
5
6
2Y
4A
10
9
8
3Y
13
12
11
4Y
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8.3 Feature Description
The SN74LVC126A device features four independent buffers with 3-state outputs, and is designed to operate
from a VCC of 1.65 V to 3.6 V. When the output enable (OE) input is low, the corresponding output is disabled
and enters a high-impedance state. This device also features high-tolerance inputs, allowing for voltage
translation in mixed voltage systems. Wide operating temperature range enables this device to be used in any
application, including rugged or extreme environments.
8.4 Device Functional Modes
The SN74LVC126A's 3-state outputs allow the outputs to be disabled using the output enable (OE) pin. To
ensure the high-impedance state during power up and power down, OE must be tied to GND through a pulldown
resistor. The minimum value of the resistor is determined by the current-sourcing capability of the driver.
Table 3. Function Table
(Each Buffer)
INPUTS
OUTPUT
OE
A
Y
H
H
H
H
L
L
L
X
Hi-Z
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC126A device is a high-drive, CMOS device that can be used for a multitude of buffer-type
functions. It can produce 24 mA of drive current at 3 V. Therefore, this device is ideal for driving multiple inputs
and for high-speed applications up to 100 MHz. The inputs and outputs are 5.5-V tolerant allowing the device to
translate up to 5.5 V or down to VCC.
9.2 Typical Application
1.65-V to 3.6-V VCC
1OE
1A
System Inputs/MCU
1Y
System Outputs/MCU
4OE
4A
4Y
Copyright © 2016, Texas Instruments Incorporated
Figure 7. Typical Buffer Application and Supply Voltage
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive also creates fast edges into light loads;
therefore, routing and load conditions must be considered to prevent ringing.
12
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SN74LVC126A
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SCAS339S – MARCH 1994 – REVISED FEBRUARY 2017
Typical Application (continued)
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– Rise time and fall time specifications: See (Δt/ΔV) in Recommended Operating Conditions.
– Specified high and low levels: See (VIH and VIL) in Recommended Operating Conditions.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommended Output Conditions
– Load currents must not exceed 25 mA per output and 50 mA total for the part.
– Outputs must not be pulled above 5.5 V.
9.2.3 Application Curve
Figure 8. Supply Current vs Input Frequency
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating in the
Recommended Operating Conditions.
Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply,
0.1 µF is recommended; if there are multiple VCC pins, then 0.01 µF or 0.022 µF is recommended for each power
pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 µF and a 1 µF
are commonly used in parallel. The bypass capacitor must be installed as close to the power pin as possible for
best results.
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SCAS339S – MARCH 1994 – REVISED FEBRUARY 2017
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11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs must never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input and gate are used, or only 3 of the 4 buffer gates are used. Such input pins must not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Figure 9 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that must be
applied to any particular unused input depends on the function of the device. Generally they are tied to GND or
VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs, unless the
part is a transceiver.
11.2 Layout Example
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 9. Layout Diagram
14
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SN74LVC126A
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SCAS339S – MARCH 1994 – REVISED FEBRUARY 2017
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
TI application report, Implications of Slow or Floating CMOS Inputs (SCBA004)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: SN74LVC126A
15
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LVC126AD
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC126A
SN74LVC126ADBR
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC126A
SN74LVC126ADE4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC126A
SN74LVC126ADG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC126A
SN74LVC126ADGVR
ACTIVE
TVSOP
DGV
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC126A
SN74LVC126ADGVRE4
ACTIVE
TVSOP
DGV
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC126A
SN74LVC126ADR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC126A
SN74LVC126ADRE4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC126A
SN74LVC126ADRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC126A
SN74LVC126ADT
ACTIVE
SOIC
D
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC126A
SN74LVC126ADTG4
ACTIVE
SOIC
D
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC126A
SN74LVC126ANSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC126A
SN74LVC126APW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC126A
SN74LVC126APWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC126A
SN74LVC126APWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC126A
SN74LVC126APWRE4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC126A
SN74LVC126APWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC126A
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
17-Mar-2017
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LVC126APWT
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC126A
SN74LVC126ARGYR
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LC126A
SN74LVC126ARGYRG4
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LC126A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC126A :
• Automotive: SN74LVC126A-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jun-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LVC126ADGVR
TVSOP
DGV
14
2000
330.0
12.4
6.8
4.0
1.6
8.0
12.0
Q1
SN74LVC126ADR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74LVC126ADT
SOIC
D
14
250
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74LVC126ANSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74LVC126APWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LVC126APWT
TSSOP
PW
14
250
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LVC126ARGYR
VQFN
RGY
14
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jun-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC126ADGVR
TVSOP
DGV
14
2000
367.0
367.0
35.0
SN74LVC126ADR
SOIC
D
14
2500
367.0
367.0
38.0
SN74LVC126ADT
SOIC
D
14
250
210.0
185.0
35.0
SN74LVC126ANSR
SO
NS
14
2000
367.0
367.0
38.0
SN74LVC126APWR
TSSOP
PW
14
2000
367.0
367.0
35.0
SN74LVC126APWT
TSSOP
PW
14
250
367.0
367.0
35.0
SN74LVC126ARGYR
VQFN
RGY
14
3000
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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