Texas Instruments | SNx4HCT14 Hex Schmitt-Trigger Inverters (Rev. G) | Datasheet | Texas Instruments SNx4HCT14 Hex Schmitt-Trigger Inverters (Rev. G) Datasheet

Texas Instruments SNx4HCT14 Hex Schmitt-Trigger Inverters (Rev. G) Datasheet
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SN54HCT14, SN74HCT14
SCLS225G – JULY 1995 – REVISED NOVEMBER 2016
SNx4HCT14 Hex Schmitt-Trigger Inverters
1 Features
3 Description
•
•
•
•
•
•
•
The SNx4HCT14 devices contain six independent
inverters. The devices perform the Boolean function
Y = A in positive logic.
1
Operating Voltage Range of 4.5 V to 5.5 V
Outputs Can Drive Up to 10 LSTTL Loads
Low Power Consumption: 20-µA Maximum ICC
Typical tpd = 18 ns
±4-mA Output Drive at 5 V
Maximum Low Input Current of 1 µA Maximum
Inputs Are TTL-Voltage Compatible
Device Information(1)
PART NUMBER
SN54HCT14
PACKAGE
BODY SIZE (NOM)
CFP (14)
9.21 mm × 5.97 mm
CDIP (14)
19.56 mm × 6.67 mm
LCCC (20)
8.89 mm × 8.89 mm
2 Applications
SOIC (14)
8.65 mm × 3.91 mm
•
•
•
•
•
•
TVSOP (14)
3.60 mm × 4.40 mm
PDIP (14)
19.30 mm × 6.35 mm
TSSOP (14)
5.00 mm × 4.40 mm
UPS
White Goods
Computer Peripherals
Printers
AC Servo Drives
Desktop Computers
SN74HCT14
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
A
Y
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54HCT14, SN74HCT14
SCLS225G – JULY 1995 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
6
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes.......................................... 8
9
Application and Implementation .......................... 9
9.1 Application Information.............................................. 9
9.2 Typical Application .................................................... 9
10 Power Supply Recommendations ..................... 10
11 Layout................................................................... 10
11.1 Layout Guidelines ................................................. 10
11.2 Layout Example .................................................... 10
12 Device and Documentation Support ................. 11
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
11
11
11
11
11
11
11
13 Mechanical, Packaging, and Orderable
Information ........................................................... 11
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (October 2010) to Revision G
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Deleted Ordering Information table; see Package Option Addendum at the end of the data sheet ...................................... 1
•
Changed Package thermal impedance, RθJA, values in Thermal Information table From: 86 To: 90.9 (D), From: 96
To: 105 (DB), From: 127 To: 132.2 (DGV), From: 80 To: 55.3 (N), and From: 113 To: 120.2 (PW)..................................... 4
2
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SCLS225G – JULY 1995 – REVISED NOVEMBER 2016
5 Pin Configuration and Functions
D, DB, DGV, J, N, PW, or W Package
X-Pin SOIC, SSOP, TVSOP, CDIP, PDIP, TSSOP, or CFP
Top View
5A
3A
5
10
5Y
3Y
6
9
4A
GND
7
8
4Y
6A
11
19
4
2A
4
18
6Y
NC
5
17
NC
2Y
6
16
5A
NC
7
15
NC
3A
8
14
5Y
13
2Y
VCC
6Y
20
12
12
3
NC
2A
1
6A
11
13
1A
2
2
1Y
10
VCC
1Y
14
3
1
9
1A
FK Package
X-Pin LCCC
Top View
4A
4Y
NC
GND
3Y
Not to scale
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
SOIC, SSOP, TVSOP, CDIP,
PDIP, TSSOP, CFP
LCCC
1A
1
2
I
Channel 1 input
1Y
2
3
O
Channel 1 output
2A
3
4
I
Channel 2 input
2Y
4
6
O
Channel 2 output
3A
5
8
I
Channel 3 input
3Y
6
9
O
Channel 3 output
4A
9
13
I
Channel 4 input
4Y
8
12
O
Channel 4 output
5A
11
16
I
Channel 5 input
5Y
10
14
O
Channel 5 output
6A
13
19
I
Channel 6 input
6Y
12
18
O
Channel 6 output
GND
7
10
—
Ground
NC
—
1, 5, 7, 11, 15, 17
—
No internal connection
VCC
14
20
—
Power supply
NAME
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage, VCC
Input voltage, VI
(2)
Output voltage, VO (2)
MIN
MAX
UNIT
–0.5
7
V
–0.5
VCC + 0.5
V
–0.5
VCC + 0.5
V
Input clamp current, IIK
VI < 0 or VI > VCC
±20
mA
Output clamp current, IOK
VO < 0 or VO > VCC
±20
mA
Continuous output current, IO
VO = 0 to VCC
±25
mA
±50
mA
150
°C
150
°C
Continuous current through VCC or GND
Operating junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
see (1)
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
TA
Operating free-air temperature
SN54HCT14
–55
125
SN74HCT14
–40
85
(1)
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
6.4 Thermal Information
SN74HCT14
THERMAL METRIC (1)
D
(SOIC)
DB
(SSOP)
DGV
(TVSOP)
N
(PDIP)
PW
(TSSOP)
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
90.9
105
132.2
55.3
120.2
°C/W
51
57
51.7
42.5
48.9
°C/W
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
45.2
52.4
61.4
35.1
61.9
°C/W
ψJT
Junction-to-top characterization parameter
18.4
22.2
5.5
27.2
5.7
°C/W
ψJB
Junction-to-board characterization parameter
44.9
51.8
60.7
35
61.3
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC = 4.5 V
VT+
Positive-going threshold
VCC = 5.5 V
VCC = 4.5 V
VT–
Negative-going threshold
VCC = 5.5 V
VCC = 4.5 V
Hysteresis (VT+ – VT–)
ΔVT
VCC = 5.5 V
IOH = –20 µA and VCC = 4.5 V
VOH
MIN
TYP
MAX
TA = 25°C
1.2
1.5
1.9
SN54HCT14
1.2
SN74HCT14
1.2
TA = 25°C
1.4
SN54HCT14
1.4
SN74HCT14
1.4
TA = 25°C
0.5
SN54HCT14
0.5
SN74HCT14
0.5
TA = 25°C
0.6
SN54HCT14
0.6
SN74HCT14
0.6
TA = 25°C
0.4
SN54HCT14
0.4
SN74HCT14
0.4
TA = 25°C
0.4
SN54HCT14
0.4
SN74HCT14
0.4
TA = 25°C
4.4
SN54HCT14
4.4
SN74HCT14
High-level output voltage
TA = 25°C
IOH = –4 mA and VCC = 4.5 V
SN54HCT14
3.7
SN74HCT14
3.84
TA = 25°C
IOL = 20 µA and VCC = 4.5 V
VOL
Low-level output voltage
II
Input current
VI = VCC or GND and VCC = 5.5 V
1.9
1.7
ICC
Supply current
ΔICC
(1)
Change in supply current
One input at 0.5 V or 2.4 V, other
inputs at GND or VCC, and
VCC = 5.5 V
2.1
0.9
1.2
1.2
1
(1)
Input capacitance
VI = VCC or GND and VCC = 5 V
1.4
V
1.4
1.4
0.6
1.4
1.4
1.4
0.65
1.5
V
1.5
1.5
4.49
V
4.3
0.001
0.1
0.1
0.1
0.17
0.26
SN54HCT14
0.4
SN74HCT14
0.33
TA = 25°C
±0.1
SN54HCT14
±1
SN74HCT14
±1
V
µA
2
SN54HCT14
40
SN74HCT14
20
0.2
3
SN74HCT14
2.9
3
µA
2.4
SN54HCT14
TA = 25°C
Ci
1.2
SN74HCT14
TA = 25°C
V
2.1
TA = 25°C
VI = VCC or GND, IO = 0, and
VCC = 5.5 V
2.1
SN54HCT14
TA = 25°C
IOL = 4 mA and VCC = 4.5 V
1.9
4.4
3.98
UNIT
mA
10
SN54HCT14
10
SN74HCT14
10
pF
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
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6.6 Switching Characteristics
over recommended operating free-air temperature range and CL = 50 pF (unless otherwise noted; see Figure 5)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
TEST CONDITIONS
MIN
TA = 25°C
VCC = 4.5 V
tpd
Propagation
(delay) time
A
Y
tt
—
20
32
48
SN74HCT14
40
18
30
SN54HCT14
45
SN74HCT14
38
TA = 25°C
VCC = 4.5 V
MAX
SN54HCT14
TA = 25°C
VCC = 5.5 V
TYP
7
22
SN74HCT14
19
TA = 25°C
VCC = 5.5 V
ns
15
SN54HCT14
Y
UNIT
6
14
SN54HCT14
20
SN74HCT14
17
ns
6.7 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
TYP
No load
10
UNIT
pF
6.8 Typical Characteristics
VCC = 4.5 V
VCC = 5.5 V
0.45
0.45
0.4
0.3
VI = 0 to VCC
0.25
VI = VCC to 0
0.2
0.15
I CC − Supply Current − mA
I CC − Supply Current − mA
0.4
0.35
VI = VCC to 0
0.3
0.25
0.2
0.15
0.1
0.1
0.05
0.05
0
0
0.45
0.9 1.35 1.8 2.26 2.7
3.16 3.61 4
VI = 0 to VCC
0.35
0
0
0.55 1.1 1.66
VI − Input Voltage − V
Figure 1. Supply Current vs Input Voltage
6
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2.2 2.76 3.3
3.86 4.4 4.97
VI − Input Voltage − V
Figure 2. Supply Current vs Input Voltage
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Typical Characteristics (continued)
6
6
VCC = 4.5 V
VCC = 5.5 V
5
VO − Output
Voltage − V
−
VO − Output
Voltage − V
−
5
4
VI = Down
3
VI = Up
2
1
0
4
VI = Down
3
VI = Up
2
1
0
−1
−1
0
0.75
3
1.5
2.27
VI – Input Voltage – V
3.77
0
Figure 3. Output Voltage vs Input Voltage
3.68
1.84
2.76
VI – Input Voltage − V
0.92
4.6
Figure 4. Output Voltage vs Input Voltage
7 Parameter Measurement Information
From Output
Under Test
3V
Test
Point
Input
1.3 V
1.3 V
0V
CL = 50 pF
(see Note A)
tPLH
In-Phase
Output
LOAD CIRCUIT
tPHL
90%
1.3 V
10%
90%
tr
Input 1.3 V
10%
90%
tPHL
VCC
90%
1.3 V
10% 0 V
tr
Out-of-Phase
Output
tPLH
90%
1.3 V
10%
1.3 V
10%
90%
tf
tf
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
VOH
1.3 V
10% V
OL
tf
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
A.
CL includes probe and test-fixture capacitance.
B.
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having
the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C.
The outputs are measured one at a time with one input transition per measurement.
D.
tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SNx4HCT14 Schmitt-Trigger devices contain six independent inverters. They perform the Boolean function
Y = A in positive logic.
Schmitt-Trigger inputs are designed to provide a minimum separation between positive and negative switching
thresholds. This allows for noisy or slow inputs that would cause problems such as oscillation or excessive
current draw with normal CMOS inputs.
8.2 Functional Block Diagram
A
Y
Copyright © 2016, Texas Instruments Incorporated
8.3 Feature Description
The wide operating range of these devices allow them to be used in a variety of systems that use different logic
levels. The outputs can drive up to 10 LSTTL loads each. The balanced drive outputs can source or sink 8 mA at
5-V VCC. This device is also input TTL compatible.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SNx4HCT14.
Table 1. Function Table
INPUT A
8
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OUTPUT Y
H
L
L
H
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74HCT14 device is a Schmitt-Trigger input CMOS device that can be used for a multitude of inverting
buffer type functions. The application shown here takes advantage of the Schmitt-Trigger inputs to produce a
delay for a logic input.
9.2 Typical Application
Copyright © 2016, Texas Instruments Incorporated
Figure 6. Simplified Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology. Take care to avoid bus contention, because it can drive currents that would
exceed maximum limits. Parallel output drive can create fast edges into light loads, so consider routing and load
conditions to prevent ringing.
9.2.2 Detailed Design Procedure
This circuit is designed around an RC network that produces a slow input to the second inverter. The RC time
constant, τ, is calculated from: τ = RC.
The delay time for this circuit is from tdelay(min) = –ln |1 – VT+(min) / VCC| τ to tdelay(max) = –ln |1 – VT+(max) / VCC| τ. It
must be noted that the delay is consistent for each device, but because the switching threshold is only ensured
between the minimum and maximum value, the output pulse length varies between devices. These values must
be calculated by using the minimum and maximum ensured VT+ values in the Electrical Characteristics.
The resistor value must be chosen such that the maximum current to and from the SN74HCT14 is 8 mA at
5-V VCC.
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Typical Application (continued)
9.2.3 Application Curve
VCC
Voltage
VT+(max)
VT+
VT+ Typical
VT+(min)
tdelay (max)
ln | 1
t delay (min)
ln | 1
VT
(max)
VCC
VT (min)
VCC
|W
VC
|W
VOUT
t0 + 42
t0 + 52
0.0
t0
t0 + 2
t0 + 22
t0 + 32
Time
Figure 7. Ideal Capacitor Voltage and Output Voltage With Positive Switching Threshold
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. The VCC terminal must have a good bypass capacitor to prevent power
disturbance. TI recommends using a 0.1-µF capacitor on the VCC terminal, and must be placed as close as
possible to the pin for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs must never float. In many cases, functions or parts of functions of
digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only
three of the four buffer gates are used. Such inputs must not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that must be
applied to any particular unused input depends on the function of the device. Generally they are tied to GND or
VCC, whichever makes more sense or is more convenient. Floating outputs are generally acceptable, unless the
part is a transceiver.
11.2 Layout Example
Vcc
Unused Input
Input
Output
Output
Unused Input
Input
Figure 8. Layout Diagram
10
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs (SCBA004)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54HCT14
Click here
Click here
Click here
Click here
Click here
SN74HCT14
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-86890012A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
596286890012A
SNJ54HCT
14FK
5962-8689001CA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8689001CA
SNJ54HCT14J
5962-8689001DA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8689001DA
SNJ54HCT14W
SN74HCT14D
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT14
SN74HCT14DBR
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT14
SN74HCT14DE4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT14
SN74HCT14DG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT14
SN74HCT14DGVR
ACTIVE
TVSOP
DGV
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT14
SN74HCT14DR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
HCT14
SN74HCT14DRE4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT14
SN74HCT14DRG3
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
HCT14
SN74HCT14DRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT14
SN74HCT14DT
ACTIVE
SOIC
D
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT14
SN74HCT14DTG4
ACTIVE
SOIC
D
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT14
SN74HCT14N
ACTIVE
PDIP
N
14
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SN74HCT14N
SN74HCT14NE4
ACTIVE
PDIP
N
14
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SN74HCT14N
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
24-Aug-2018
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74HCT14PWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
HT14
SN74HCT14PWRE4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT14
SN74HCT14PWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT14
SN74HCT14PWT
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT14
SN74HCT14PWTG4
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT14
SNJ54HCT14FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
596286890012A
SNJ54HCT
14FK
SNJ54HCT14J
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8689001CA
SNJ54HCT14J
SNJ54HCT14W
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8689001DA
SNJ54HCT14W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HCT14, SN74HCT14 :
• Catalog: SN74HCT14
• Automotive: SN74HCT14-Q1, SN74HCT14-Q1
• Military: SN54HCT14
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Aug-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74HCT14DGVR
TVSOP
DGV
14
2000
330.0
12.4
6.8
4.0
1.6
8.0
12.0
Q1
SN74HCT14DR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74HCT14DR
SOIC
D
14
2500
330.0
16.8
6.5
9.5
2.1
8.0
16.0
Q1
SN74HCT14DRG3
SOIC
D
14
2500
330.0
16.8
6.5
9.5
2.1
8.0
16.0
Q1
SN74HCT14DRG4
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74HCT14DT
SOIC
D
14
250
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74HCT14PWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74HCT14PWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74HCT14PWRG4
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74HCT14PWT
TSSOP
PW
14
250
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Aug-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74HCT14DGVR
TVSOP
DGV
14
2000
367.0
367.0
35.0
SN74HCT14DR
SOIC
D
14
2500
333.2
345.9
28.6
SN74HCT14DR
SOIC
D
14
2500
364.0
364.0
27.0
SN74HCT14DRG3
SOIC
D
14
2500
364.0
364.0
27.0
SN74HCT14DRG4
SOIC
D
14
2500
333.2
345.9
28.6
SN74HCT14DT
SOIC
D
14
250
210.0
185.0
35.0
SN74HCT14PWR
TSSOP
PW
14
2000
364.0
364.0
27.0
SN74HCT14PWR
TSSOP
PW
14
2000
367.0
367.0
35.0
SN74HCT14PWRG4
TSSOP
PW
14
2000
367.0
367.0
35.0
SN74HCT14PWT
TSSOP
PW
14
250
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OUTLINE
J0014A
CDIP - 5.08 mm max height
SCALE 0.900
CERAMIC DUAL IN LINE PACKAGE
PIN 1 ID
(OPTIONAL)
A
4X .005 MIN
[0.13]
.015-.060 TYP
[0.38-1.52]
1
14
12X .100
[2.54]
14X .014-.026
[0.36-0.66]
14X .045-.065
[1.15-1.65]
.010 [0.25] C A B
.754-.785
[19.15-19.94]
8
7
B
.245-.283
[6.22-7.19]
.2 MAX TYP
[5.08]
C
.13 MIN TYP
[3.3]
SEATING PLANE
.308-.314
[7.83-7.97]
AT GAGE PLANE
.015 GAGE PLANE
[0.38]
0 -15
TYP
14X .008-.014
[0.2-0.36]
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
www.ti.com
EXAMPLE BOARD LAYOUT
J0014A
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE
(.300 ) TYP
[7.62]
SEE DETAIL A
SEE DETAIL B
1
14
12X (.100 )
[2.54]
SYMM
14X ( .039)
[1]
8
7
SYMM
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
.002 MAX
[0.05]
ALL AROUND
(.063)
[1.6]
METAL
( .063)
[1.6]
SOLDER MASK
OPENING
METAL
(R.002 ) TYP
[0.05]
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
DETAIL A
DETAIL B
SCALE: 15X
13X, SCALE: 15X
4214771/A 05/2017
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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