Texas Instruments | SNx4AHC125 Quadruple Bus Buffer Gates With 3-State Outputs (Rev. L) | Datasheet | Texas Instruments SNx4AHC125 Quadruple Bus Buffer Gates With 3-State Outputs (Rev. L) Datasheet

Texas Instruments SNx4AHC125 Quadruple Bus Buffer Gates With 3-State Outputs (Rev. L) Datasheet
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SN54AHC125, SN74AHC125
SCLS256L – DECEMBER 1995 – REVISED NOVEMBER 2016
SNx4AHC125 Quadruple Bus Buffer Gates With 3-State Outputs
1 Features
3 Description
•
•
The SNx4AHC125 devices are quadruple bus buffer
gates featuring independent line drivers with 3-state
outputs. Each output is disabled when the associated
output-enable (OE) input is high. When OE is low, the
respective gate passes the data from the A input to
its Y output.
1
•
•
Operating Range: 2 V to 5.5 V
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Four Individual Output Enable Pins
All Inputs Have Schmitt-Trigger Action
To ensure the high-impedance state during power up
or power down, OE must be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
2 Applications
•
•
•
•
•
Flow Meters
Programmable Logic Controllers
Power Over Ethernet (PoE)
Motor Drives and Controls
Electronic Point-of-Sale
Device Information(1)
PART NUMBER
PACKAGE (PINS)
BODY SIZE (NOM)
SNx4AHC125FK
LCCC (20)
8.89 mm 8.89 mm
SNx4AHC125DB
SSOP (14)
6.20 mm 5.30 mm
SNx4AHC125D
SOIC (14)
8.65 mm × 3.91 mm
SNx4AHC125NS
SO (14)
10.30 mm × 5.30 mm
SNx4AHC125W
CFP (14)
9.21 mm × 5.97 mm
SNx4AHC125DGV TVSOP (14)
3.60 mm × 4.40 mm
SNx4AHC125PW
TSSOP (14)
5.00 mm × 4.40 mm
SNx4AHC125N
PDIP (14)
19.30 mm × 6.35 mm
SNx4AHC125RGY VQFN (14)
3.50 mm × 3.50 mm
SNx4AHC125J
19.56 mm × 6.67 mm
CDIP (14)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
1
10
1OE
1A
3OE
2
3
1Y
3A
4
8
3Y
13
2OE
2A
9
4OE
5
6
2Y
4A
12
11
4Y
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54AHC125, SN74AHC125
SCLS256L – DECEMBER 1995 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
7
8
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
Switching Characteristics: VCC = 3.3 V ±0.3 V ......... 8
Switching Characteristics: VCC = 5 V ±0.5 V ............ 9
Noise Characteristics .............................................. 10
Operating Characteristics........................................ 10
Typical Characteristics .......................................... 10
Parameter Measurement Information ................ 11
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 12
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application .................................................. 13
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 15
12 Device and Documentation Support ................. 16
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
16
16
13 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (June 2013) to Revision L
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted Ordering Information table; see Package Option Addendum at the end of the data sheet ...................................... 1
•
Changed Package thermal impedance, RθJA, value in Thermal Information table From: 86°C/W To: 92.6°C/W (D),
From: 96°C/W To: 107.3°C/W (DB), From: 127°C/W To: 134.6°C/W (DGV), From: 80°C/W To: 56.3°C/W (N), From:
76°C/W To: 89.9°C/W (NS), and From: 113°C/W To: 121.5°C/W (PW) ................................................................................ 6
Changes from Revision J (December 1995) to Revision K
Page
•
Changed document format from Quicksilver to DocZone ...................................................................................................... 1
•
Extended operating temperature range to 125°C................................................................................................................... 5
2
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Product Folder Links: SN54AHC125 SN74AHC125
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SCLS256L – DECEMBER 1995 – REVISED NOVEMBER 2016
5 Pin Configuration and Functions
D, DB, DGV, N, NS, J, W, or PW Package
14-Pin SOIC, SSOP, TVSOP, PDIP, SO, CDIP, CFP, or TSSOP
Top View
1A
2
13
4OE
1Y
3
12
1A
1Y
2OE
2A
2Y
4A
2OE
4
11
4Y
2A
5
10
3OE
2Y
6
9
3A
GND
7
8
3Y
VCC
VCC
1
14
2
13 4OE
3
12 4A
4Y
4
11
5
10 3OE
9 3A
6
7
8
3Y
14
1OE
1
GND
1OE
RGY Package
14-Pin VQFN
Top View
Not to scale
1A
1OE
NC
VCC
4OE
3
2
1
20
19
FK Package
20-Pin LCCC
Top View
5
17
NC
2OE
6
16
4Y
NC
7
15
NC
2A
8
14
3OE
3A
3Y
NC
GND
2Y
13
NC
12
4A
11
18
10
4
9
1Y
Not to scale
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3
SN54AHC125, SN74AHC125
SCLS256L – DECEMBER 1995 – REVISED NOVEMBER 2016
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Pin Functions
PIN
I/O
DESCRIPTION
SOIC, SSOP, TVSOP, PDIP,
SO, CDIP, CFP, TSSOP, VQFN
LCCC
1OE
1
2
I
Output enable for gate 1
1A
2
3
I
Gate 1 input
1Y
3
4
O
Gate 1 output
2OE
4
6
I
Output enable for gate 2
2A
5
8
I
Gate 2 input
NAME
2Y
6
9
O
Gate 2 output
3OE
10
14
I
Output enable for gate 3
3A
9
13
I
Gate 3 input
3Y
8
12
O
Gate 3 output
4OE
13
19
I
Output enable for gate 4
4A
12
18
I
Gate 4 input
4Y
11
16
O
Gate 4 output
GND
7
10
—
Ground pin
NC
—
1, 5, 7,
11, 15, 17
—
No internal connection
VCC
14
20
—
Power pin
4
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SCLS256L – DECEMBER 1995 – REVISED NOVEMBER 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply voltage
–0.5
7
V
(2)
–0.5
7
V
–0.5
VCC + 0.5
V
Input voltage
Output voltage (2)
Input clamp current
VI < 0
–20
mA
Output clamp current
VO < 0 or VO > VCC
±20
mA
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
150
°C
150
°C
Continuous current through VCC or GND
Virtual operating junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
VIH
Supply voltage
High-level input voltage
MIN
MAX
2
5.5
VCC = 2 V
1.5
VCC = 3V
2.1
VCC = 5.5 V
UNIT
V
V
3.85
VCC = 2 V
0.5
VCC = 3 V
0.9
VIL
Low-level Input voltage
VI
Input voltage
0
5.5
VO
Output voltage
0
VCC
V
–50
µA
VCC = 5.5 V
1.65
VCC = 2 V
IOH
IOL
High-level output current
Low-level output current
Δt/Δv
Input Transition rise or fall rate
TA
Operating free-air temperature
VCC = 3.3 V ±0.3 V
–4
VCC = 5 V ±0.5 V
–8
VCC = 2 V
50
VCC = 3.3 V ±0.3 V
4
VCC = 5 V ±0.5 V
8
VCC = 3.3 V ±0.3 V
100
VCC = 5 V ±0.5 V
20
–40
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V
125
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V
mA
µA
mA
ns/V
°C
5
SN54AHC125, SN74AHC125
SCLS256L – DECEMBER 1995 – REVISED NOVEMBER 2016
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6.4 Thermal Information
SNx4AHC125
THERMAL METRIC (1)
D (SOIC)
DB (SSOP)
NS (SO)
DGV (TVSOP)
PW (TSSOP)
N (PDIP)
RGY (VQFN)
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
Junction-toambient thermal
resistance
92.6
107.3
89.9
134.6
121.5
56.3
55.1
°C/W
Junction-to-case
RθJC(top) (top) thermal
resistance
52.7
59.3
47.7
53.9
50.2
43.9
52.3
°C/W
RθJA
UNIT
RθJB
Junction-toboard thermal
resistance
46.8
54.7
48.6
63.8
63.2
36.1
30.9
°C/W
ψJT
Junction-to-top
characterization
parameter
19.7
24
17.5
6.3
6.1
29.2
2.4
°C/W
ψJB
Junction-toboard
characterization
parameter
46.6
54.1
48.3
63.2
62.7
36
31
°C/W
—
—
—
—
—
—
12.7
°C/W
Junction-to-case
RθJC(bot) (bottom) thermal
resistance
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC = 2 V
IOH = –50 µA
VCC = 3 V
VOH
VCC = 4.5 V
IOH = –4 mA and VCC = 3 V
IOH = –8 mA and VCC = 4.5 V
6
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MIN
TYP
TA = 25°C
1.9
2
TA = –55°C to 125°C (SN54AHC125)
1.9
TA = –40°C to 85°C (SN74AHC125)
1.9
TA = –40°C to 125°C
(recommended SN74AHC125)
1.9
TA = 25°C
2.9
TA = –55°C to 125°C (SN54AHC125)
2.9
TA = –40°C to 85°C (SN74AHC125)
2.9
TA = –40°C to 125°C
(recommended SN74AHC125)
2.9
TA = 25°C
4.4
TA = –55°C to 125°C (SN54AHC125)
4.4
TA = –40°C to 85°C (SN74AHC125)
4.4
TA = –40°C to 125°C
(recommended SN74AHC125)
4.4
TA = 25°C
2.58
TA = –55°C to 125°C (SN54AHC125)
2.48
TA = –40°C to 85°C (SN74AHC125)
2.48
TA = –40°C to 125°C
(recommended SN74AHC125)
2.48
TA = 25°C
3.94
TA = –55°C to 125°C (SN54AHC125)
3.8
TA = –40°C to 85°C (SN74AHC125)
3.8
TA = –40°C to 125°C
(recommended SN74AHC125)
3.8
MAX
UNIT
3
4.5
V
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Product Folder Links: SN54AHC125 SN74AHC125
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SCLS256L – DECEMBER 1995 – REVISED NOVEMBER 2016
Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC = 2 V
IOL = 50 µA
VCC = 3 V
VOL
VCC = 4.5 V
MIN
TYP
0.1
TA = –55°C to 125°C (SN54AHC125)
0.1
TA = –40°C to 85°C (SN74AHC125)
0.1
TA = –40°C to 125°C
(recommended SN74AHC125)
0.1
TA = 25°C
0.1
TA = –55°C to 125°C (SN54AHC125)
0.1
TA = –40°C to 85°C (SN74AHC125)
0.1
TA = –40°C to 125°C
(recommended SN74AHC125)
0.1
TA = 25°C
0.1
TA = –55°C to 125°C (SN54AHC125)
0.1
TA = –40°C to 85°C (SN74AHC125)
0.1
TA = –40°C to 125°C
(recommended SN74AHC125)
0.1
TA = 25°C
IOH = 4 mA and VCC = 3 V
0.5
TA = –40°C to 85°C (SN74AHC125)
0.44
0.36
TA = –55°C to 125°C (SN54AHC125)
0.5
TA = –40°C to 85°C (SN74AHC125)
0.44
TA = –40°C to 125°C
(recommended SN74AHC125)
VI = 5.5 V or GND and VCC = 0 V to 5.5 V
0.5
TA = 25°C
±0.1
TA = –55°C to 125°C (SN54AHC125)
±1 (1)
TA = –40°C to 85°C (SN74AHC125)
±1
TA = –40°C to 125°C
(recommended SN74AHC125)
±1
TA = 25°C
IOZ
VO = VCC or GND and VCC = 5.5 V
Ci
(1)
VI = VCC or GND, IO = 0, and VCC = 5.5 V
VI = VCC or GND and VCC = 5 V
µA
±0.25
TA = –55°C to 125°C (SN54AHC125)
±2.5
TA = –40°C to 85°C (SN74AHC125)
±2.5
TA = –40°C to 125°C
(recommended SN74AHC125)
±2.5
TA = 25°C
ICC
V
0.5
TA = 25°C
II
UNIT
0.36
TA = –55°C to 125°C (SN54AHC125)
TA = –40°C to 125°C
(recommended SN74AHC125)
IOH = 8 mA and VCC = 4.5 V
MAX
TA = 25°C
µA
4
TA = –55°C to 125°C (SN54AHC125)
40
TA = –40°C to 85°C (SN74AHC125)
40
TA = –40°C to 125°C
(recommended SN74AHC125)
40
TA = 25°C
4
TA = –40°C to 85°C (SN74AHC125)
10
10
µA
pF
On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
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6.6 Switching Characteristics: VCC = 3.3 V ±0.3 V
over recommended operating free-air temperature range and VCC = 3.3 V ±0.3 V (unless otherwise noted; see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
MIN
TA = 25°C
tPHL, tPLH
A
Y
CL = 15 pF
OE
Y
CL = 15 pF
OE
Y
CL = 15 pF
A
Y
CL = 50 pF
TA = –40°C to 85°C (SN74AHC125)
1
9.5
TA = –40°C to 125°C
(recommended SN74AHC125)
1
9.5
5.4 (1)
TA = –55°C to 125°C
(SN54AHC125)
1 (1)
OE
Y
CL = 50 pF
tPLZ, tPHZ
tsk(o)
(1)
(2)
8
OE
OE
Y
Y
CL = 50 pF
CL = 50 pF
TA = –40°C to 125°C
(recommended SN74AHC125)
9.5
7.0 (1)
1 (1)
11.5 (1)
TA = –40°C to 85°C (SN74AHC125)
1 (1)
11.5 (1)
TA = –40°C to 125°C
(recommended SN74AHC125)
1 (1)
11.5 (1)
8.1
1
13
TA = –40°C to 85°C (SN74AHC125)
1
13
TA = –40°C to 125°C
(recommended SN74AHC125)
1
13
1
13
TA = –40°C to 85°C (SN74AHC125)
1
13
TA = –40°C to 125°C
(recommended SN74AHC125)
1
13
ns
13.2
TA = –55°C to 125°C
(SN54AHC125)
1
15
TA = –40°C to 85°C (SN74AHC125)
1
15
TA = –40°C to 125°C
(recommended SN74AHC125)
1
15
1.5 (2)
TA = –40°C to 85°C (SN74AHC125)
ns
11.5
TA = –55°C to 125°C
(SN54AHC125)
9.5
ns
11.5
TA = –55°C to 125°C
(SN54AHC125)
7.9
ns
9.7 (1)
TA = –55°C to 125°C
(SN54AHC125)
TA = 25°C
ns
9.5 (1)
9.5
TA = 25°C
UNIT
8 (1)
TA = –40°C to 85°C (SN74AHC125)
TA = 25°C
tPZL, tPZH
8
9.5 (1)
1
TA = 25°C
tPHL, tPLH
(1)
(1)
TA = 25°C
tPLZ, tPHZ
MAX
(1)
5.6
TA = –55°C to 125°C
(SN54AHC125)
TA = 25°C
tPZL, tPZH
TYP
1.5
ns
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
On products compliant to MIL-PRF-38535, this parameter does not apply.
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6.7 Switching Characteristics: VCC = 5 V ±0.5 V
over recommended operating free-air temperature range and VCC = 5 V ±0.5 V (unless otherwise noted; see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
MIN
TA = 25°C
TA = –55°C to 125°C
(SN54AHC125)
tPLH, tPHL
A
Y
CL = 15 pF
Y
CL = 15 pF
3.8
OE
Y
CL = 15 pF
1
6.5
TA = –40°C to 125°C
(recommended SN74AHC125)
1
6.5
3.6 (1)
6 (1)
TA = –40°C to 85°C
(SN74AHC125)
1
6
TA = –40°C to 125°C
(recommended SN74AHC125)
1
6
4.6 (1)
A
Y
CL = 50 pF
1 (1)
8 (1)
TA = –40°C to 85°C
(SN74AHC125)
1 (1)
8 (1)
TA = –40°C to 125°C
(recommended SN74AHC125)
1 (1)
8 (1)
1
8.5
TA = –40°C to 85°C
(SN74AHC125)
1
8.5
TA = –40°C to 125°C
(recommended SN74AHC125)
1
8.5
tPZH, tPZL
OE
Y
CL = 50 pF
5.1
1
8
TA = –40°C to 85°C
(SN74AHC125)
1
8
TA = –40°C to 125°C
(recommended SN74AHC125)
1
8
tPHZ, tPLZ
OE
Y
CL = 50 pF
(1)
(2)
OE
Y
CL = 50 pF
1
10
TA = –40°C to 85°C
(SN74AHC125)
1
10
TA = –40°C to 125°C
(recommended SN74AHC125)
1
10
TA = –40°C to 85°C
(SN74AHC125)
ns
ns
8.8
TA = –55°C to 125°C
(SN54AHC125)
TA = 25°C
tsk(o)
6.1
ns
7.1
TA = –55°C to 125°C
(SN54AHC125)
TA = 25°C
ns
7.5
TA = –55°C to 125°C
(SN54AHC125)
TA = 25°C
ns
6.8 (1)
TA = –55°C to 125°C
(SN54AHC125)
5.3
UNIT
5.1 (1)
1 (1)
TA = 25°C
tPLH, tPHL
5.5
TA = –40°C to 85°C
(SN74AHC125)
1
TA = 25°C
tPHZ, tPLZ
(1)
6.5 (1)
TA = –55°C to 125°C
(SN54AHC125)
OE
MAX
(1)
(1)
TA = 25°C
tPZH, tPZL
TYP
ns
1 (2)
1
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
On products compliant to MIL-PRF-38535, this parameter does not apply.
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Product Folder Links: SN54AHC125 SN74AHC125
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9
SN54AHC125, SN74AHC125
SCLS256L – DECEMBER 1995 – REVISED NOVEMBER 2016
www.ti.com
6.8 Noise Characteristics
VCC = 5 V, CL = 50 pF, and TA = 25°C (1)
PARAMETER
MIN
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic (VOL)
0.8
V
VOL(V)
Quiet output, minimum dynamic (VOL)
–0.8
V
VOH(V)
Quiet output, minimum dynamic (VOH)
4.4
V
VIH(D)
High-level dynamic input voltage
3.5
V
VIL(D)
Low-level dynamic input voltage
(1)
1.5
V
Characteristics are for surface-mount packages only.
6.9 Operating Characteristics
VCC = 5 V and TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load and f = 1 MHz
TYP
UNIT
9.5
pF
6.10 Typical Characteristics
Figure 1 shows ICC for varying VIN values when VCC is 5 V ±0.5 V and TA = 25°C.
3.6
3.3
3
2.7
ICC (mA)
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
0
0.5
1
1.5
2
2.5
3
VIN (V)
3.5
4
4.5
5
5.5
D001
Figure 1. VIN vs ICC
10
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Product Folder Links: SN54AHC125 SN74AHC125
SN54AHC125, SN74AHC125
www.ti.com
SCLS256L – DECEMBER 1995 – REVISED NOVEMBER 2016
7 Parameter Measurement Information
From Output
Under Test
Test
Point
RL = 1 kΩ
From Output
Under Test
CL
(see Note A)
S1
VCC
Open
TEST
GND
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
CL
(see Note A)
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
Input
VCC
50% VCC
50% VCC
0V
th
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
0V
tPHL
tPLH
In-Phase
Output
50% VCC
Output
Waveform 1
S1 at VCC
(see Note B)
50% VCC
VOH
50% VCC
VOL
50% VCC
tPLZ
tPZL
≈VCC
50% VCC
VOL + 0.3 V
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
0V
tPZH
tPLH
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
VCC
Output
Control
50% VCC
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the
output control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf
≤ 3 ns.
D.
The outputs are measured one at a time with one input transition per measurement.
E.
All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
Copyright © 1995–2016, Texas Instruments Incorporated
Product Folder Links: SN54AHC125 SN74AHC125
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SN54AHC125, SN74AHC125
SCLS256L – DECEMBER 1995 – REVISED NOVEMBER 2016
www.ti.com
8 Detailed Description
8.1 Overview
The SNx4AHC125 devices have four integrated bus buffer gates. Each gate can be individually controlled from
their respective output enable pins or tied together and controlled simultaneously. This allows for control of up to
four different lines from one device. Often times a microcontroller have multiple function options for a single pin.
By using GPIO pins to enable specific buffers, the SNx4AHC125 can act as a multiplexer to select a specific data
line depending on what pin function is selected on the microcontroller. At the same time, the lines that are not
selected are isolated from the pin.
8.2 Functional Block Diagram
1
10
1OE
1A
3OE
2
3
1Y
3A
4
8
3Y
13
2OE
2A
9
4OE
5
6
2Y
4A
12
11
4Y
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.
8.3 Feature Description
Each buffer has its own output enable. This allows for control of each buffer individually. When the output enable
is LOW, the input is passed to the output. When the output enable is HIGH, the output is high impedance. This
feature is useful in applications that might require isolation.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SNx4AHC125.
Table 1. Function Table
(Each Buffer)
INPUTS
12
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OUTPUT
OE
A
Y
L
H
H
L
L
L
H
X
Z
Copyright © 1995–2016, Texas Instruments Incorporated
Product Folder Links: SN54AHC125 SN74AHC125
SN54AHC125, SN74AHC125
www.ti.com
SCLS256L – DECEMBER 1995 – REVISED NOVEMBER 2016
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The wide operating range of the SNx4AHC125 devices allows for implementation into a variety of applications. In
addition to the wide operating range, these devices differentiate from similar devices because they have four
buffers that can be individually controlled through their independent output enable (OE) pins. Each buffer is either
enabled and passes data from A to Y, or disabled and set to a high-impedance state.
9.2 Typical Application
UART Select
SPI Select
1
Vcc
2
GPIO
1OE
1A
UART TX/ SPI Out
1Y
MCU
UART RX/ SPI In
1
14
2
13
3
12
4A
4
2Y
SPI IN
4Y
2OE
2A
4OE
SN74AHC125
11
3OE
5
10
6
9
7
8
3A
UART RX
3Y
GND
SPI OUT
UART TX
Copyright © 2016, Texas Instruments Incorporated
Figure 3. Digital MUX
9.2.1 Design Requirements
It is best to set VCC for the SN74AHC125 to the same level as the microcontroller logic levels. This allows for
optimal performance. The SN74AHC125 can safely handle input levels from –0.5 V to 7 V. However, if the logic
levels that are being received vary from the VCC level of the device then errors can occur. For example, if VCC is
5.5 V then the minimum high-level input voltage (VIH) level is 3.85 V. This means if the microcontroller is sending
a HIGH signal, but HIGH = 3.3 V, it would be too low a level for the SNx4AHC125 to register it as what it must
be. In this case VCC would need to be lowered in order to lower the VIH minimum. The opposite is also true for
low-level input voltage (VIL). If VCC is set to 2 V, then VIL maximum is 0.5 V. Depending on the microcontroller
logic levels, a LOW signal may not go low enough for the SNx4AHC125 to register it.
Copyright © 1995–2016, Texas Instruments Incorporated
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SN54AHC125, SN74AHC125
SCLS256L – DECEMBER 1995 – REVISED NOVEMBER 2016
www.ti.com
Typical Application (continued)
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For VIH and VIL levels at varying VCC, see Recommended Operating Conditions.
– Be mindful of rise time and fall time specifications for the output enable pins to ensure that the right
buffers are enabled and the others are disabled in time. This minimizes interference on the
microcontroller pin and to exterior circuitry. See Switching Characteristics: VCC = 3.3 V ±0.3 V and
Switching Characteristics: VCC = 5 V ±0.5 V table for more details.
2. Recommended Output Conditions:
– Load currents must not exceed IO maximum per output and must not exceed continuous current through
VCC or GND total current for the part. These limits are located in the Absolute Maximum Ratings.
– Outputs must not be pulled above VCC.
9.2.3 Application Curves
Typical device at 25°C
5.05
0.25
5
0.225
4.95
0.2
0.175
VOL (V)
VOH (V)
4.9
4.85
4.8
4.75
0.15
0.125
0.1
0.075
4.7
0.05
4.65
0.025
4.6
-10
0
-9
-8
-7
-6
-5
-4
IOH (mA)
-3
-2
-1
0
0
1
2
D001
Figure 4. IOH vs VOH
14
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3
4
5
6
IOL (mA)
7
8
9
10
D001
Figure 5. IOL vs VOL
Copyright © 1995–2016, Texas Instruments Incorporated
Product Folder Links: SN54AHC125 SN74AHC125
SN54AHC125, SN74AHC125
www.ti.com
SCLS256L – DECEMBER 1995 – REVISED NOVEMBER 2016
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions.
Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply,
a 0.1-µF capacitor is recommended and if there are multiple VCC pins then a 0.01-µF or 0.022-µF capacitor is
recommended for each power pin. It is ok to parallel multiple bypass capacitors to reject different frequencies of
noise. 0.1-µF and 1-µF capacitors are commonly used in parallel. The bypass capacitor must be installed as
close to the power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs must not ever float. In many cases, functions or parts of functions of
digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3
of the 4 buffer gates are used. Such input pins must not be left unconnected because the undefined voltages at
the outside connections result in undefined operational states. Specified below are the rules that must be
observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low
bias to prevent them from floating. The logic level that must be applied to any particular unused input depends on
the function of the device. Generally, they are tied to GND or VCC (whichever make more sense or is more
convenient).
11.2 Layout Example
VCC
Input
Unused Input
Output
Unused Input
Output
Input
Figure 6. Layout Diagram
Copyright © 1995–2016, Texas Instruments Incorporated
Product Folder Links: SN54AHC125 SN74AHC125
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SN54AHC125, SN74AHC125
SCLS256L – DECEMBER 1995 – REVISED NOVEMBER 2016
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs (SCBA004)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54AHC125
Click here
Click here
Click here
Click here
Click here
SN74AHC125
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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Copyright © 1995–2016, Texas Instruments Incorporated
Product Folder Links: SN54AHC125 SN74AHC125
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9686801Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629686801Q2A
SNJ54AHC
125FK
5962-9686801QCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9686801QC
A
SNJ54AHC125J
5962-9686801QDA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9686801QD
A
SNJ54AHC125W
SN74AHC125D
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC125
SN74AHC125DBR
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA125
SN74AHC125DG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC125
SN74AHC125DGVR
ACTIVE
TVSOP
DGV
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA125
SN74AHC125DR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC125
SN74AHC125DRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC125
SN74AHC125N
ACTIVE
PDIP
N
14
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 125
SN74AHC125N
SN74AHC125NE4
ACTIVE
PDIP
N
14
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 125
SN74AHC125N
SN74AHC125NSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC125
SN74AHC125PW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA125
SN74AHC125PWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA125
SN74AHC125PWRE4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA125
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
24-Aug-2018
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74AHC125PWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA125
SN74AHC125RGYR
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HA125
SN74AHC125RGYRG4
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HA125
SNJ54AHC125FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629686801Q2A
SNJ54AHC
125FK
SNJ54AHC125J
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9686801QC
A
SNJ54AHC125J
SNJ54AHC125W
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9686801QD
A
SNJ54AHC125W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54AHC125, SN74AHC125 :
• Catalog: SN74AHC125
• Automotive: SN74AHC125-Q1, SN74AHC125-Q1
• Enhanced Product: SN74AHC125-EP, SN74AHC125-EP
• Military: SN54AHC125
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74AHC125DGVR
TVSOP
DGV
14
2000
330.0
12.4
6.8
4.0
1.6
8.0
12.0
Q1
SN74AHC125DR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74AHC125DR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74AHC125NSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74AHC125PWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AHC125DGVR
TVSOP
DGV
14
2000
367.0
367.0
35.0
SN74AHC125DR
SOIC
D
14
2500
333.2
345.9
28.6
SN74AHC125DR
SOIC
D
14
2500
367.0
367.0
38.0
SN74AHC125NSR
SO
NS
14
2000
367.0
367.0
38.0
SN74AHC125PWR
TSSOP
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
J0014A
CDIP - 5.08 mm max height
SCALE 0.900
CERAMIC DUAL IN LINE PACKAGE
PIN 1 ID
(OPTIONAL)
A
4X .005 MIN
[0.13]
.015-.060 TYP
[0.38-1.52]
1
14
12X .100
[2.54]
14X .014-.026
[0.36-0.66]
14X .045-.065
[1.15-1.65]
.010 [0.25] C A B
.754-.785
[19.15-19.94]
8
7
B
.245-.283
[6.22-7.19]
.2 MAX TYP
[5.08]
C
.13 MIN TYP
[3.3]
SEATING PLANE
.308-.314
[7.83-7.97]
AT GAGE PLANE
.015 GAGE PLANE
[0.38]
0 -15
TYP
14X .008-.014
[0.2-0.36]
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
www.ti.com
EXAMPLE BOARD LAYOUT
J0014A
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE
(.300 ) TYP
[7.62]
SEE DETAIL A
SEE DETAIL B
1
14
12X (.100 )
[2.54]
SYMM
14X ( .039)
[1]
8
7
SYMM
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
.002 MAX
[0.05]
ALL AROUND
(.063)
[1.6]
METAL
( .063)
[1.6]
SOLDER MASK
OPENING
METAL
(R.002 ) TYP
[0.05]
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
DETAIL A
DETAIL B
SCALE: 15X
13X, SCALE: 15X
4214771/A 05/2017
www.ti.com
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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