Texas Instruments | SN74LVC244A Octal Buffer or Driver With 3-State Outputs (Rev. AB) | Datasheet | Texas Instruments SN74LVC244A Octal Buffer or Driver With 3-State Outputs (Rev. AB) Datasheet

Texas Instruments SN74LVC244A Octal Buffer or Driver With 3-State Outputs (Rev. AB) Datasheet
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SN74LVC244A
SCAS414AB – NOVEMBER 1992 – REVISED NOVEMBER 2016
SN74LVC244A Octal Buffer or Driver With 3-State Outputs
1 Features
2 Applications
•
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1
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Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Specified From –40°C to +85°C and
–40°C to +125°C
Maximum tpd of 5.9 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input or Output Voltage With
3.3-V VCC)
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate
Inputs From a Maximum of 5.5 V Down
to the VCC Level
Available in Ultra Small Logic QFN Package (0.5
mm Maximum Height)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 1000-V Charged-Device Model
Servers
LED Displays
Network Switches
Telecom Infrastructure
Motor Drivers
I/O Expanders
3 Description
These octal bus buffers are designed for 1.65-V to
3.6-V VCC operation. The SN74LVC244A devices
are designed for asynchronous communication
between data buses.
Device Information
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LVC244AN
PDIP (20)
25.40 mm × 6.35 mm
SN74LVC244ANS
SO (20)
12.60 mm × 5.30 mm
SN74LVC244ADB
SSOP (20)
7.50 mm × 5.30 mm
SN74LVC244ADGV
TVSOP (20)
5.00 mm × 4.40 mm
SN74LVC244ADW
SOIC (20)
12.80 mm × 7.50 mm
SN74LVC244ARGY
VQFN (20)
4.50 mm × 3.50 mm
SN74LVC244AZQN
BGA (20)
3.00 mm × 4.00 mm
SN74LVC244APW
TSSOP (20)
6.50 mm × 4.40 mm
SN74LVC244ARWP
X1QFN (20)
2.50 mm × 3.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
1OE
1A1
1A2
1A3
1A4
1
2OE
2
18
4
16
6
14
8
12
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
19
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
Pin numbers shown are for the DB, DGV, DW, N, NS, PW, and RGY packages.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC244A
SCAS414AB – NOVEMBER 1992 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
5
5
5
6
6
7
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes.......................................... 9
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
10 Power Supply Recommendations ..................... 11
11 Layout................................................................... 11
11.1 Layout Guidelines ................................................. 11
11.2 Layout Example .................................................... 11
12 Device and Documentation Support ................. 12
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
12
12
12
12
12
13 Mechanical, Packaging, and Orderable
Information ........................................................... 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision AA (June 2016) to Revision AB
Page
•
Changed A2 to A4 for 2OE in Pin Functions table ................................................................................................................. 4
•
Added ambient temperature, TA for BGA package and all other packages in Recommended Operating Conditions........... 5
•
Added Receiving Notification of Documentation Updates section ....................................................................................... 12
Changes from Revision Z (January 2015) to Revision AA
Page
•
Updated Device Information table to show all available packages ........................................................................................ 1
•
Added RWP Package ............................................................................................................................................................ 3
•
Deleted GQN package from Pin Functions table ................................................................................................................... 4
•
Added RWP thermal information to Thermal Information table and updated all thermal information for existing packages . 5
•
Updated all values for ZQN column in Thermal Information table ......................................................................................... 5
•
Added package type in Thermal Information table................................................................................................................. 5
•
Added RWP thermal information to Thermal Information table and updated all thermal information for existing packages . 6
•
Updated all values for ZQN column in Thermal Information table ......................................................................................... 6
•
Added package type in Thermal Information table................................................................................................................. 6
Changes from Revision Y (September 2010) to Revision Z
Page
•
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted Ordering Information table, see Mechanical, Packaging, and Orderable Information at the end of the datasheet.. 1
•
Updated Features. .................................................................................................................................................................. 1
2
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Copyright © 1992–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVC244A
SN74LVC244A
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SCAS414AB – NOVEMBER 1992 – REVISED NOVEMBER 2016
5 Pin Configuration and Functions
ZQN Package
20-Pin BGA
Top View
A
B
1
2
3
4
1A1
1OE
VCC
2OE
1A2
C
2A4
1A3
D
2Y3
1A4
E
DB, DGV, DW, N, NS, and PW Packages
20-Pin SSOP, TVSOP, SOIC, PDIP, SO, and TSSOP
Front View
2A2
GND
2Y1
2Y4
2A3
2Y2
2A1
1Y1
1Y2
1Y3
1OE
1
20
VCC
1A1
2
19
2OE
2Y4
3
18
1Y1
1A2
4
17
2A4
2Y3
5
16
1Y2
1A3
6
15
2A3
2Y2
7
14
1Y3
1A4
8
13
2A2
2Y1
9
12
1Y4
GND
10
11
2A1
Not to scale
1Y4
Not to scale
2
Thermal
Pad
16
2A4
15
1Y2
14
13
2A3
1Y3
5
12
2A2
2Y2
7
14
1Y3
2Y2
6
11
1Y4
1A4
8
13
2A2
2Y1
9
12
1Y4
Not to scale
11
2A1
10
GND
10
1A3
2A1
2A3
2A4
8
9
1Y2
15
17
2Y1
GND
16
6
Thermal
Pad
7
5
1A3
4
1A4
2Y3
1A2
2Y3
1A2
3
4
1Y1
1
2Y4
17
1A1
1Y1
VCC
2OE
2OE
18
19
18
19
1OE
RWP Package
20-Pin X1QFN
Top View
20
VCC
3
20
2
2Y4
1OE
1A1
1
RGY Package
20-Pin VQFN
Top View
Not to scale
TI recommends to connect the exposed thermal pad to ground for best thermal performance. Must not be connected
to any other pin than ground.
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SN74LVC244A
SCAS414AB – NOVEMBER 1992 – REVISED NOVEMBER 2016
www.ti.com
Pin Functions
PIN
DB, DGV,
DW, N, NS,
PW, and
RGY
ZQN
RWP
1A1
2
A1
1
I
Port 1 A1 input
1A2
4
B1
3
I
Port 1 A2 input
1A3
6
C1
5
I
Port 1 A3 input
1A4
8
D1
7
I
Port 1 A4 input
1OE
1
A2
20
I
Output enable
1Y1
18
B4
17
O
Port 1 Y1 output
1Y2
16
C4
15
O
Port 1 Y2 output
1Y3
14
D4
13
O
Port 1 Y3 output
1Y4
12
E4
11
O
Port 1 Y4 output
2A1
11
E3
10
I
Port 2 A1 input
2A2
13
D2
12
I
Port 2 A2 input
2A3
15
C3
14
I
Port 2 A3 input
2A4
17
B2
16
I
Port 2 A4 input
2OE
19
A4
18
I
Output enable
2Y1
9
E2
8
O
Port 2 Y1 output
2Y2
7
D3
6
O
Port 2 Y2 output
2Y3
5
C2
4
O
Port 2 Y3 output
2Y4
3
B3
2
O
Port 2 Y4 output
GND
10
E1
9
—
Ground
VCC
20
A3
19
—
Power pin
NAME
TYPE
DESCRIPTION
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VCC
Supply voltage
–0.5
6.5
V
VI
Input voltage (2)
–0.5
6.5
V
–0.5
6.5
V
–0.5
VCC + 0.5
(2)
UNIT
VO
Voltage range applied to any output in the high-impedance or power-off state
VO
Voltage range applied to any output in the high or low state (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
Ptot
Power dissipation
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
(4)
(5)
4
TA = –40°C to +125°C (4) (5)
–65
V
±100
mA
500
mW
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
For the DW package: above 70°C the value of Ptot derates linearly with 8 mW/K.
For the DB, DGV, N, NS, and PW packages: above 60°C the value of Ptot derates linearly with 5.5 mW/K.
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SCAS414AB – NOVEMBER 1992 – REVISED NOVEMBER 2016
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over recommended operating free-air temperature range (unless otherwise noted) (1)
TA = 25°C
VCC Supply voltage
Operating
VIH
MAX
MIN
MAX
MIN
MAX
1.65
3.6
1.65
3.6
1.65
3.6
1.5
1.5
1.5
0.65 × VCC
0.65 × VCC
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
1.7
1.7
VCC = 2.7 V to 3.6 V
2
2
2
VCC = 1.65 V to 1.95 V
VIL
Low-level
input voltage
VI
Input voltage
VO
Output voltage
IOL
TA
(1)
High-level
output current
Low-level
output current
Ambient
temperature
UNIT
V
V
0.35 × VCC
0.35 × VCC
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
0.7
0.7
VCC = 2.7 V to 3.6 V
0.8
0.8
0.8
V
0
5.5
0
5.5
0
5.5
V
0
VCC
0
VCC
0
VCC
V
VCC = 1.65 V
IOH
–40 TO +125°C
MIN
Data retention only
VCC = 1.65 V to 1.95 V
High-level
input voltage
–40 TO +85°C
–4
–4
–4
VCC = 2.3 V
–8
–8
–8
VCC = 2.7 V
–12
–12
–12
VCC = 3 V
–24
–24
–24
VCC = 1.65 V
4
4
4
VCC = 2.3 V
8
8
8
VCC = 2.7 V
12
12
12
VCC = 3 V
24
24
24
BGA package
–40
85
All other packages
–40
125
mA
mA
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
6.4 Thermal Information
SN74LVC244A
THERMAL METRIC
(1)
DB (2)
(SSOP)
DGV (2)
(TVSOP)
DW (2)
(SOIC)
ZQN (2)
(BGA)
N (2)
(PDIP)
NS (2)
(SO)
PW (2)
(TSSOP)
RGY (3)
(VQFN)
RWP (3)
(X1QFN)
UNIT
20 PINS
RθJA
Junction-to-ambient
thermal resistance
108.1
128.7
90.9
198.7
61.6
90.1
114.7
50.3
79.9
°C/W
RθJC(top)
Junction-to-case (top)
thermal resistance
70.2
43.7
55.3
106.8
46.5
56.4
48.4
58.4
63.2
°C/W
RθJB
Junction-to-board
thermal resistance
63.3
70.2
58.8
143.1
42.5
57.7
65.6
28.3
46.4
°C/W
ψJT
Junction-to-top
characterization parameter
30.6
3.1
29.1
24.1
34.6
28.4
6.8
4.9
2.6
°C/W
ψJB
Junction-to-board
characterization parameter
62.9
69.5
58.3
119.6
42.4
57.2
65.1
28.4
46.3
°C/W
(1)
(2)
(3)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The package thermal impedance is calculated in accordance with JESD 51-7.
The package thermal impedance is calculated in accordance with JESD 51-5.
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Thermal Information (continued)
SN74LVC244A
DB (2)
(SSOP)
THERMAL METRIC (1)
DGV (2)
(TVSOP)
DW (2)
(SOIC)
ZQN (2)
(BGA)
N (2)
(PDIP)
NS (2)
(SO)
PW (2)
(TSSOP)
RGY (3)
(VQFN)
RWP (3)
(X1QFN)
UNIT
—
—
22.7
27.3
°C/W
20 PINS
RθJC(bot)
Junction-to-case (bottom)
thermal resistance
—
—
—
n/a
—
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
VCC
–40 TO +85°C
TYP
MAX
MIN
–40 TO +125°C
MAX
MIN
MAX
IOH = –100 µA
1.65 V
to
3.6 V
VCC – 0.2
VCC – 0.2
VCC – 0.3
IOH = –4 mA
1.65 V
1.29
1.2
1.05
IOH = –8 mA
2.3 V
1.9
1.7
1.55
2.7 V
2.2
2.2
2.05
3V
2.4
2.4
2.25
IOH = –24 mA
3V
2.3
2.2
2
IOL = 100 µA
1.65 V
to
3.6 V
0.1
0.2
IOL = 4 mA
1.65 V
0.24
0.45
0.6
IOL = 8 mA
2.3 V
0.3
0.7
0.75
IOL = 12 mA
2.7 V
0.4
0.4
0.6
IOL = 24 mA
3V
0.55
0.55
0.8
IOH = –12 mA
VOL
TA = 25°C
MIN
UNIT
V
0.3
V
II
VI = 5.5 V or GND
3.6 V
±1
±5
±20
µA
Ioff
VI or VO = 5.5 V
0
±1
±10
±20
µA
IOZ
VO = 0 to 5.5 V
3.6 V
±1
±10
±20
µA
1
10
40
1
10
40
500
500
5000
VI = VCC or GND
ICC
IO = 0
3.6 V
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
2.7 V
to
3.6 V
Ci
VI = VCC or GND
3.3 V
4
pF
Co
VO = VCC or GND
3.3 V
5.5
pF
(1)
3.6 V ≤ VI ≤ 5.5 V (1)
µA
µA
This applies in the disabled state only.
6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
Y
VCC
–40 TO +85°C
–40 TO +125°C
TYP
MAX
MIN
MAX
MIN
MAX
1.5 V
1
7
14.4
1
14.9
1
16.4
1.8 V ± 0.15 V
1
5.9
10.4
1
10.9
1
12.4
2.5 V ± 0.2 V
1
4.2
7.4
1
7.9
1
10
2.7 V
1
4.2
6.7
1
6.9
1
8.2
1.5
3.9
5.7
1.5
5.9
1.5
7.2
3.3 V ± 0.3 V
6
TA = 25°C
MIN
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UNIT
ns
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SCAS414AB – NOVEMBER 1992 – REVISED NOVEMBER 2016
Switching Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
FROM
(INPUT)
PARAMETER
ten
TO
(OUTPUT)
OE
TA = 25°C
VCC
Y
OE
Y
MAX
MIN
MAX
MIN
MAX
1.5 V
1
8.3
17.8
1
18.3
1
19.8
1
6.4
12.1
1
12.6
1
14.1
2.5 V ± 0.2 V
1
4.6
9.1
1
9.6
1
11.7
2.7 V
1
5
8.4
1
8.6
1
10.3
1.5
4.5
7.4
1.5
7.6
1.5
9.4
1.5 V
1
7.2
15.6
1
16.1
1
17.6
1.8 V ± 0.15 V
1
5.8
11.6
1
12.1
1
13.6
2.5 V ± 0.2 V
1
3.7
7.3
1
7.8
1
9.9
2.7 V
1
3.8
6.6
1
6.8
1
8.6
1.5
3.8
6.3
1.5
6.5
1.5
3.3 V ± 0.3 V
tsk(o)
–40 TO +125°C
TYP
1.8 V ± 0.15 V
3.3 V ± 0.3 V
tdis
–40 TO +85°C
MIN
3.3 V ± 0.3 V
UNIT
ns
ns
8
1
1.5
ns
6.7 Operating Characteristics
TA = 25°C
PARAMETER
TEST CONDITIONS
Outputs enabled
Cpd
f = 10 MHz
Power dissipation capacitance per buffer/driver
Outputs disabled
f = 10 MHz
VCC
TYP
1.8 V
43
2.5 V
43
3.3 V
44
1.8 V
1
2.5 V
1
3.3 V
2
UNIT
pF
6.8 Typical Characteristics
10
14
12
VCC = 3 V,
TA = 25°C
tpd – Propagation Delay Time – ns
tpd – Propagation Delay Time – ns
VCC = 3 V,
TA = 25°C
One Output Switching
Four Outputs Switching
Eight Outputs Switching
10
8
6
4
One Output Switching
Four Outputs Switching
Eight Outputs Switching
8
6
4
2
2
0
50
100
150
200
250
300
CL – Load Capacitance – pF
Figure 1. Propagation Delay (Low to High Transition)
vs Load Capacitance
0
50
100
150
200
250
300
CL – Load Capacitance – pF
Figure 2. Propagation Delay (High to Low Transition)
vs Load Capacitance
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.5 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
2 × VCC
6V
6V
15 pF
30 pF
30 pF
50 pF
50 pF
2 kΩ
1 kΩ
500 Ω
500 Ω
500 Ω
0.1 V
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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Product Folder Links: SN74LVC244A
SN74LVC244A
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SCAS414AB – NOVEMBER 1992 – REVISED NOVEMBER 2016
8 Detailed Description
8.1 Overview
The SN74LVC244A device is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs.
The device passes data from the A inputs to the Y outputs when OE is low. The outputs are in the highimpedance state when OE is high. OE should be tied to VCC through a pullup resistor to ensure the highimpedance state during power up or power down; the minimum value of the resistor is determined by the currentsinking capability of the driver.
8.2 Functional Block Diagram
1OE
1A1
1A2
1A3
1A4
1
19
2OE
2
18
4
16
6
14
8
12
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
Pin numbers shown are for the DB, DGV, DW, N, NS, PW, and RGY packages.
Figure 4. Logic Diagram (Positive Logic)
8.3 Feature Description
•
•
•
Allows down voltage translation
– 5 V to 3.3 V
– 5 V or 3.3 V to 1.8 V
Inputs accept voltage levels up to 5.5 V
It is available in ultra small logic 20 pin QFN package at 0.5 mm max height with 0.4 mm pitch.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74LVC244A.
Table 1. Function Table
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Hi-Z
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9
SN74LVC244A
SCAS414AB – NOVEMBER 1992 – REVISED NOVEMBER 2016
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
SN74LVC244A is a high drive CMOS device that can be used for a multitude of bus interface type applications
where output drive or PCB trace length is a concern. The inputs can accept voltages to 5.5 V at any valid VCC
making it ideal for down translation.
9.2 Typical Application
Regulated 3 V
SN74LVC244A
1OE
A1
uC or
System
Logic
VCC
Y1
uC
System Logic
LEDs
A4
Y4
GND
Figure 5. Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Avoid bus contention because it can drive
currents in excess of maximum limits. The high drive will also create fast edges into light loads, so consider
routing and load conditions to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For rise time and fall time specification, see (Δt/ΔV) in the Recommended Operating Conditions table.
– For specified high and low levels, see (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC.
2. Recommended maximum Output Conditions:
– Load currents should not exceed (IO max) per output and should not exceed (Continuous current through
VCC or GND) total current for the part. These limits are located in the Absolute Maximum Ratings table.
– Outputs should not be pulled above VCC.
10
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SN74LVC244A
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SCAS414AB – NOVEMBER 1992 – REVISED NOVEMBER 2016
Typical Application (continued)
9.2.3 Application Curves
60
100
80
TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
40
TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
20
I OH – mA
I OL – mA
60
40
0
–20
–40
20
–60
0
–80
–20
–0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
–100
–1
–0.5 0.0
VOL – V
Figure 6. Output Drive Current (IOL)
vs LOW-level Output Voltage (VOL)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VOH – V
Figure 7. Output Drive Current (IOH)
vs HIGH-level Output Voltage (VOH)
10 Power Supply Recommendations
The power supply may be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1 μF capacitor is
recommended for devices with a single supply. If there are multiple VCC terminals, then 0.01 μF or 0.022 μF
capacitors are recommended for each power terminal. It is permissible to parallel multiple bypass capacitors to
reject different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies
of noise. The bypass capacitor should be installed as close to the power terminal as possible for the best results.
11 Layout
11.1 Layout Guidelines
Inputs should not float when using multiple bit logic devices. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples include situations when only two inputs of a triple-input AND
gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected
because the undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 8 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally, they will be tied to GND
or VCC, whichever makes more sense or is more convenient.
11.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
Figure 8. Layout Diagram
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11
SN74LVC244A
SCAS414AB – NOVEMBER 1992 – REVISED NOVEMBER 2016
www.ti.com
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
12
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Product Folder Links: SN74LVC244A
PACKAGE OPTION ADDENDUM
www.ti.com
27-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LVC244ADBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244ADBRE4
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244ADBRG4
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244ADGVR
ACTIVE
TVSOP
DGV
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244ADW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC244A
SN74LVC244ADWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC244A
SN74LVC244ADWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC244A
SN74LVC244ADWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LVC244A
SN74LVC244ADWRG4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC244A
SN74LVC244AN
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 125
SN74LVC244AN
SN74LVC244ANSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC244A
SN74LVC244APW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244APWE4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244APWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244APWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244APWRE4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244APWRG3
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LC244A
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
27-Dec-2019
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LVC244APWRG4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244APWT
ACTIVE
TSSOP
PW
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244APWTE4
ACTIVE
TSSOP
PW
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244APWTG4
ACTIVE
TSSOP
PW
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244ARGYR
ACTIVE
VQFN
RGY
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LC244A
SN74LVC244ARGYRG4
ACTIVE
VQFN
RGY
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LC244A
SN74LVC244ARWPR
ACTIVE
X1QFN
RWP
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244AZQNR
NRND
BGA
MICROSTAR
JUNIOR
ZQN
20
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
LC244A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Dec-2019
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC244A :
• Automotive: SN74LVC244A-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
8.2
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
7.5
2.5
12.0
16.0
Q1
SN74LVC244ADBR
SSOP
DB
20
2000
330.0
16.4
SN74LVC244ADGVR
TVSOP
DGV
20
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LVC244ADWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74LVC244ADWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74LVC244ADWRG4
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74LVC244ANSR
SO
NS
20
2000
330.0
24.4
8.4
13.0
2.5
12.0
24.0
Q1
SN74LVC244APWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.0
1.4
8.0
16.0
Q1
SN74LVC244APWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74LVC244APWRG3
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74LVC244APWRG4
TSSOP
PW
20
2000
330.0
16.4
6.95
7.0
1.4
8.0
16.0
Q1
SN74LVC244APWT
TSSOP
PW
20
250
330.0
16.4
6.95
7.0
1.4
8.0
16.0
Q1
SN74LVC244ARGYR
VQFN
RGY
20
3000
330.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
SN74LVC244ARWPR
X1QFN
RWP
20
2000
178.0
13.5
2.85
3.65
0.75
8.0
12.0
Q1
SN74LVC244AZQNR
BGA MI
CROSTA
R JUNI
OR
ZQN
20
1000
330.0
12.4
3.3
4.3
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Dec-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC244ADBR
SSOP
DB
20
2000
367.0
367.0
38.0
SN74LVC244ADGVR
TVSOP
DGV
20
2000
367.0
367.0
35.0
SN74LVC244ADWR
SOIC
DW
20
2000
367.0
367.0
45.0
SN74LVC244ADWR
SOIC
DW
20
2000
364.0
361.0
36.0
SN74LVC244ADWRG4
SOIC
DW
20
2000
367.0
367.0
45.0
SN74LVC244ANSR
SO
NS
20
2000
367.0
367.0
45.0
SN74LVC244APWR
TSSOP
PW
20
2000
367.0
367.0
38.0
SN74LVC244APWR
TSSOP
PW
20
2000
364.0
364.0
27.0
SN74LVC244APWRG3
TSSOP
PW
20
2000
364.0
364.0
27.0
SN74LVC244APWRG4
TSSOP
PW
20
2000
367.0
367.0
38.0
SN74LVC244APWT
TSSOP
PW
20
250
367.0
367.0
38.0
SN74LVC244ARGYR
VQFN
RGY
20
3000
355.0
350.0
50.0
SN74LVC244ARWPR
X1QFN
RWP
20
2000
189.0
185.0
36.0
SN74LVC244AZQNR
BGA MICROSTAR
JUNIOR
ZQN
20
1000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGY 20
VQFN - 1 mm max height
PLASTIC QUAD FGLATPACK - NO LEAD
3.5 x 4.5, 0.5 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225264/A
www.ti.com
PACKAGE OUTLINE
RGY0020A
VQFN - 1 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
3.65
3.35
A
B
PIN 1 INDEX AREA
4.65
4.35
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
2.05 0.1
2X 1.5
(0.2) TYP
10
11
9
EXPOSED
THERMAL PAD
12
14X 0.5
2X
3.5
21
SYMM
3.05 0.1
2
PIN 1 ID
19
20X
20
1
SYMM
0.30
0.18
0.1
0.05
0.5
20X
0.3
C A B
4225320/A 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGY0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.05)
SYMM
1
20
20X (0.6)
2
19
20X (0.24)
(1.275)
(4.3)
21
SYMM
(3.05)
14X (0.5)
(0.775)
9
12
(R0.05) TYP
( 0.2) TYP
VIA
11
10
(0.75) TYP
(3.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4225320/A 09/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGY0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
4X (0.92)
(R0.05) TYP
20
1
20X (0.6)
2
19
20X (0.24)
4X
(1.33)
21
SYMM
(4.3)
(0.77)
14X (0.5)
(0.56)
9
12
METAL
TYP
11
10
(0.75)
TYP
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 21
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4225320/A 09/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
RWP0020A
X1QFN - 0.5 mm max height
SCALE 4.200
PLASTIC QUAD FLATPACK - NO LEAD
2.6
2.4
A
B
PIN 1 INDEX AREA
3.4
3.2
0.5 MAX
C
SEATING PLANE
0.05
0.00
0.08
4X (0.36)
2X 1.2
16X 0.4
6
(0.15) TYP
EXPOSED
THERMAL PAD
10
7
11
2X
2
1.9±0.05
1.14±0.05
1
PIN 1 ID
(OPTIONAL)
16
17
20
(0.1) TYP
20X
20X
0.25
0.15
0.1
0.05
C A
B
0.5
0.3
4221912/A 03/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RWP0020A
X1QFN - 0.5 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.14)
SYMM
20
17
20X (0.6)
1
16
20X (0.2)
(0.7)
SYMM
(3.1)
(1.9)
16X (0.4)
6
11
( 0.2) TYP
VIA
10
7
(R0.05)
TYP
(2.3)
LAND PATTERN EXAMPLE
SCALE:20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221912/A 03/2015
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RWP0020A
X1QFN - 0.5 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(R0.05) TYP
2X (1.07)
20
17
20X (0.6)
1
16
20X (0.2)
2X
(0.85)
SYMM
(3.1)
(0.525)
16X (0.4)
METAL
TYP
11
6
7
SYMM
10
(2.3)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4221912/A 03/2015
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DB0020A
SSOP - 2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
C
8.2
TYP
7.4
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
18X 0.65
20
1
2X
7.5
6.9
NOTE 3
5.85
10
11
20X
B
5.6
5.0
NOTE 4
SEE DETAIL A
(0.15) TYP
0.38
0.22
0.1
C A B
2 MAX
0.25
GAGE PLANE
0 -8
0.95
0.55
0.05 MIN
DETAIL A
A 15
TYPICAL
4214851/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.85)
(R0.05) TYP
1
20
20X (0.45)
SYMM
18X (0.65)
11
10
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4214851/B 08/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
20X (1.85)
SYMM
(R0.05) TYP
1
20
20X (0.45)
SYMM
18X (0.65)
10
11
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214851/B 08/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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