Texas Instruments | SNx4LV374A Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs (Rev. J) | Datasheet | Texas Instruments SNx4LV374A Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs (Rev. J) Datasheet

Texas Instruments SNx4LV374A Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs (Rev. J) Datasheet
Product
Folder
Sample &
Buy
Technical
Documents
Support &
Community
Tools &
Software
SN54LV374A, SN74LV374A
SCLS408J – APRIL 1998 – REVISED OCTOBER 2016
SNx4LV374A Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs
1 Features
3 Description
•
•
•
The SNx4LV374A devices are octal edge-triggered
D-type flip-flops designed for 2-V to 5.5-V VCC
operation.
1
•
•
•
•
•
2-V to 5.5-V VCC Operation
Maximum tpd of 9.5 ns at 5 V
Typical VOLP (Output Ground Bounce) <0.8 V at
VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) >2.3 V at
VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on All
Ports
Ioff Supports Partial-Power-Down Mode Operation
Latch-up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LV374ADB
SSOP (20)
7.20 mm × 5.30 mm
SN74LV374ADW
SOIC (20)
12.80 mm × 7.50 mm
SN74LV374ANS
SO (20)
12.60 mm × 5.30 mm
SN74LV374APW
TSSOP (20)
6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
2 Applications
•
•
•
•
•
Programmable Logic Controller (PLC)
DCS and PAC: Analog Input Module
Trains, Trams, and Subway Carriages
AC Inverter Drives
Printers
Pin numbers shown are for the DB, DW,
FK, J, NS, PW, RGY, and W packages.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54LV374A, SN74LV374A
SCLS408J – APRIL 1998 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
4
4
5
5
6
6
7
7
7
8
8
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics: VCC = 2.5 V ± 0.2 V ........
Switching Characteristics: VCC = 3.3 V ± 0.3 V ........
Switching Characteristics: VCC = 5 V ± 0.5 V ...........
Timing Requirements ...............................................
Noise Characteristics ..............................................
Operating Characteristics, TA = 25°C .....................
Typical Characteristics ............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
10
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application .................................................. 11
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
14
14
14
13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (March 2015) to Revision J
Page
•
Added Junction temperature, TJ ............................................................................................................................................ 4
•
Deleted "VCC × 0.3" from MIN and added "VCC × 0.3" to MAX for SN54LV374A and SN74LV374A..................................... 5
•
Changed "SN54LV384A" to "SN54LV374A" in Electrical Characteristics table ..................................................................... 6
•
Added Related Links section, Receiving Notification of Documentation Updates section, and Community Resources
section .................................................................................................................................................................................. 14
Changes from Revision H (April 2005) to Revision I
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Submit Documentation Feedback
Copyright © 1998–2016, Texas Instruments Incorporated
SN74LV374A
SN54LV374A, SN74LV374A
www.ti.com
SCLS408J – APRIL 1998 – REVISED OCTOBER 2016
5 Pin Configuration and Functions
DB, DW, NS, or PW Package
20-PIN SSOP, SOIC, SO, or TSSOP
Top View
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
OE
I
Enable pin
2
1Q
O
Output 1
3
1D
I
Input 1
4
2D
I
Input 2
5
2Q
O
Output 2
6
3Q
O
Output 3
7
3D
I
Input 3
8
4D
I
Input 4
9
4Q
O
Output 4
10
GND
–
Ground pin
11
CLK
I
Clock pin
12
5Q
O
Output 5
13
5D
I
Input 5
14
6D
I
Input 6
15
6Q
O
Output 6
16
7Q
O
Output 7
17
7D
I
Input 7
18
8D
I
Input 8
19
8Q
O
Output 8
20
VCC
–
Power pin
Submit Documentation Feedback
Copyright © 1998–2016, Texas Instruments Incorporated
SN74LV374A
3
SN54LV374A, SN74LV374A
SCLS408J – APRIL 1998 – REVISED OCTOBER 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VCC
(1)
Supply voltage
(2)
MIN
MAX
UNIT
−0.5
7
V
−0.5
7
V
−0.5
7
V
−0.5
VCC + 0.5
V
VI
Input voltage
VO
Voltage applied to any output in the high-impedance or power-off state
VO
Output voltage (2) (3)
IIK
Input clamp current, (VI < 0)
–20
mA
IOK
Output clamp current, (VO < 0)
–50
mA
IO
Continuous output current, (VO = 0 to VCC)
±35
mA
(2)
Continuous current through VCC or GND
±70
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5 V maximum.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
2000
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Submit Documentation Feedback
Copyright © 1998–2016, Texas Instruments Incorporated
SN74LV374A
SN54LV374A, SN74LV374A
www.ti.com
SCLS408J – APRIL 1998 – REVISED OCTOBER 2016
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
(1)
SN54LV374A (2)
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
SN74LV374A
MIN
MAX
2
5.5
Low-level input voltage
VI
Output voltage
High-level output current
VCC × 0.7
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
Δt/Δv
0.5
VCC = 2.3 V to 2.7 V
VCC × 0.3
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC × 0.3
VCC = 4.5 V to 5.5 V
VCC × 0.3
VCC × 0.3
0
5.5
0
5.5
High or low state
0
VCC
0
VCC
3-state
0
5.5
0
5.5
–50
−50
VCC = 2.3 V to 2.7 V
–2
–2
VCC = 3 V to 3.6 V
–8
–8
–16
–16
50
50
VCC = 2.3 V to 2.7 V
2
2
VCC = 3 V to 3.6 V
8
8
VCC = 4.5 V to 5.5 V
16
16
VCC = 2.3 V to 2.7 V
200
200
100
100
20
20
Input transition rise or fall rate VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
TA
(1)
(2)
Operating free-air temperature
V
VCC × 0.77
VCC = 2 V
Low-level output current
UNIT
V
0.5
VCC = 4.5 V to 5.5 V
IOL
5.5
VCC = 2.3 V to 2.7 V
VCC = 2 V
IOH
2
1.5
Input voltage
VO
MAX
1.5
VCC = 2 V
VIL
MIN
–55
125
–40
125
V
V
V
μA
mA
μA
mA
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
PRODUCT PREVIEW
6.4 Thermal Information
SN74LV374A
THERMAL METRIC
(1)
DB (SSOP)
DW (SOIC)
NS (SO)
PW (TSSOP)
20 PINS
20 PINS
20 PINS
20 PINS
94.5
79.2
76.7
102.4
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
56.4
43.7
43.2
36.5
°C/W
RθJB
Junction-to-board thermal resistance
49.7
47
44.2
53.6
°C/W
ψJT
Junction-to-top characterization parameter
18.5
18.6
16.8
2.4
°C/W
ψJB
Junction-to-board characterization parameter
49.3
46.5
43.8
52.9
°C/W
RθJA
(1)
Junction-to-ambient thermal resistance
UNIT
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
Copyright © 1998–2016, Texas Instruments Incorporated
SN74LV374A
5
SN54LV374A, SN74LV374A
SCLS408J – APRIL 1998 – REVISED OCTOBER 2016
www.ti.com
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
VOH
IOH = −50 µA
2 V to 5.5 V
IOH = −2 mA
2.3 V
IOH = –8 mA
IOH = −16 mA
VOL
SN74LV374A
–40°C to +85°C
SN54LV374A (1)
TYP
MAX
MIN TYP
SN74LV374A
–40°C to +125°C
MAX
MIN
VCC−0.1
VCC−0.1
2
2
2
3V
2.48
2.48
2.48
4.5 V
3.8
TYP
UNIT
MAX
VCC−0.1
3.8
V
3.8
IOL = 50 µA
2 V to 5.5 V
0.1
0.1
IOL = 2 mA
2.3 V
0.4
0.4
0.4
IOL = 8 mA
3V
0.44
0.44
0.44
4.5 V
0.55
0.55
0.55
±1
±1
±1
µA
IOL = 16 mA
0.1
V
II
VI = 5.5 V or GND
0 to 5.5 V
IOZ
VO = VCC or GND
5.5 V
±5
±5
±5
µA
ICC
VI = VCC or GND , IO = 0
5.5 V
20
20
20
µA
Ioff
VI or VO = 0 to 5.5 V
0
5
5
5
µA
Ci
VI = VCC or GND
(1)
3.3 V
2.9
2.9
2.9
pF
PRODUCT PREVIEW
6.6 Switching Characteristics: VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
TA = 25°C
MIN
CL = 15 pF
fmax
CL = 50 pF
tpd
CLK
Q
ten
OE
Q
CL = 15 pF
TYP
SN54LV374A
MAX
60 (1) 105 (1)
50
85
MIN
MAX
SN74LV374A
–40°C to
+85°C
MIN
MAX
SN74LV374A
–40°C to +125°C
MIN
50 (1)
50
50
40
40
40
MHz
9.7 (1)
16.3 (1)
1 (1)
19 (1)
1
19
1
20.5
8.9 (1)
15.9 (1)
1 (1)
19 (1)
1
19
1
20.5
(1)
(1)
(1)
(1)
tdis
OE
Q
1
15
1
16.5
tpd
CLK
Q
11.8
19.3
1
23
1
23
1
24.5
ten
OE
Q
10.9
18.8
1
22
1
22
1
23.5
tdis
OE
Q
8.2
17.3
1
19
1
19
1
20.5
tsk(o)
(1)
6
6.3
CL = 50 pF
12.6
1
2
15
UNIT
MAX
ns
ns
2
On products compliant to MIL-PRF-38535, this parameter is not production tested.
Submit Documentation Feedback
Copyright © 1998–2016, Texas Instruments Incorporated
SN74LV374A
SN54LV374A, SN74LV374A
www.ti.com
SCLS408J – APRIL 1998 – REVISED OCTOBER 2016
6.7 Switching Characteristics: VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
CL = 15 pF
fmax
CL = 50 pF
tpd
CLK
Q
ten
OE
Q
tdis
OE
tpd
ten
tdis
TA = 25°C
MIN
SN54LV374A
TYP
MAX
80 (1) 150 (1)
55
110
6.8
(1)
MIN
MAX
MIN
70 (1)
70
70
50
50
50
15
(1)
MHz
1
15
1
1 (1)
13 (1)
1
13
1
14
Q
4.7 (1)
10.5 (1)
1 (1)
12.5 (1)
1
12.5
1
13.5
CLK
Q
8.3
16.2
1
18.5
1
18.5
1
19.5
OE
Q
7.7
14.5
1
16.5
1
16.5
1
17.5
OE
Q
5.9
14
1
16
1
16
1
17
CL = 50 pF
1
(1)
UNIT
MAX
11 (1)
tsk(o)
(1)
MAX
SN74LV374A
–40°C to +125°C
6.3 (1)
CL = 15 pF
12.7
(1)
MIN
SN74LV374A
–40°C to +85°C
1.5
16
ns
ns
1.5
On products compliant to MIL-PRF-38535, this parameter is not production tested.
6.8 Switching Characteristics: VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
fmax
tpd
CLK
TA = 25°C
SN54LV374A
MAX
MIN
MAX
SN74LV374A
–40°C to
+85°C
MIN
MAX
SN74LV374A
–40°C to +125°C
MIN
TYP
CL = 15 pF
130 (1)
205 (1)
110 (1)
110
MIN
110
CL = 50 pF
85
1705
75
75
75
UNIT
MAX
MHz
Q
4.9 (1)
8.1 (1)
1 (1)
9.5 (1)
1
9.5
1
10.5
(1)
(1)
(1)
9 (1)
1
9
1
10
ten
OE
Q
CL = 15 pF
tdis
OE
Q
3.4 (1)
6.8 (1)
1 (1)
8 (1)
1
8
1
9
tpd
CLK
Q
5.9
10.1
1
11.5
1
11.5
1
12.5
ten
OE
Q
5.5
9.6
1
11
1
11
1
12
tdis
OE
Q
4
8.8
1
10
1
10
1
11
CL = 50 pF
4.6
tsk(o)
(1)
7.6
1
1
ns
ns
1
On products compliant to MIL-PRF-38535, this parameter is not production tested.
6.9 Timing Requirements
over recommended operating free-air temperature range, (unless otherwise noted) (see Figure 3)
TA = 25°C
MIN
MAX
SN54LV374A
(1)
MIN
MAX
SN74LV374A
–40°C to
+85°C
MIN
MAX
SN74LV374A
–40°C to +125°C
MIN
UNIT
MAX
VCC = 2.5 V ± 0.2 V
tw
Pulse duration, CLK high or low
6
7
7
7
ns
tsu
Setup time, data before CLK↑
5
5.5
5.5
6
ns
th
Hold time, data after CLK↑
2.5
2.5
2.5
3
ns
VCC = 3.3 V ± 0.3 V
tw
Pulse duration, CLK high or low
tsu
Setup time, data before CLK↑
th
Hold time, data after CLK↑
5
5.5
5.5
5.5
ns
4.5
45
4.5
5
ns
2
2
2
2.5
ns
VCC = 5 V ± 0.5 V
tw
Pulse duration, CLK high or low
5
5
5
5
ns
tsu
Setup time, data before CLK↑
3
3
3
3.5
ns
th
Hold time, data after CLK↑
2
2
2
2.5
ns
(1)
PRODUCT PREVIEW
Submit Documentation Feedback
Copyright © 1998–2016, Texas Instruments Incorporated
SN74LV374A
7
SN54LV374A, SN74LV374A
SCLS408J – APRIL 1998 – REVISED OCTOBER 2016
www.ti.com
6.10 Noise Characteristics
VCC = 3.3 V, CL = 50 pF, TA = 25°C
(1)
SN74LV374A
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.6
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
−0.5
−0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
2.9
2.9
V
2.31
V
0.99
V
Characteristics are for surface-mount packages only.
6.11 Operating Characteristics, TA = 25°C
PARAMETER
Cpd Power dissipation capacitance
TEST CONDITIONS
Outputs enabled
CL = 50 pF, f = 10 MHz
VCC
TYP
3.3 V
21.1
5V
22.8
UNIT
pF
6.12 Typical Characteristics
8
6
7
5
6
TPD (ns)
TPD (ns)
4
3
5
4
3
2
2
1
0
-100
1
0
-50
0
50
Temperature
100
150
D001
Figure 1. TPD vs. Temperature at 5 V
8
0
1
2
3
VCC
4
5
6
D002
Figure 2. TPD vs. VCC at 25°C
Submit Documentation Feedback
Copyright © 1998–2016, Texas Instruments Incorporated
SN74LV374A
SN54LV374A, SN74LV374A
www.ti.com
SCLS408J – APRIL 1998 – REVISED OCTOBER 2016
7 Parameter Measurement Information
Figure 3. Load Circuit and Voltage Waveforms
Submit Documentation Feedback
Copyright © 1998–2016, Texas Instruments Incorporated
SN74LV374A
9
SN54LV374A, SN74LV374A
SCLS408J – APRIL 1998 – REVISED OCTOBER 2016
www.ti.com
8 Detailed Description
8.1 Overview
The SNx4LV374A devices are octal edge-triggered D-type flip-flops designed for 2-V to 5.5-V VCC operation.
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively lowimpedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bi-directional bus
drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the
logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight
outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased
drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect
internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the
high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to
VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The output of the device is unknown until the first valid rising clock edge occurs while VCC is within the
Recommended Operating Conditions range.
8.2 Functional Block Diagram
Figure 4. Logic Diagram (Positive Logic)
8.3 Feature Description
The device’s wide operating range allows it to be used in a variety of systems that use different logic levels. The
low propagation delay allows fast switching and higher speeds of operation. In addition, the low ground bounce
stabilizes the performance of non-switching outputs while another output is switching.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SNx4LV374A devices.
Table 1. Function Table (Each Flip-Flop)
INPUTS
10
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
L
X
Q0
H
X
X
Z
Submit Documentation Feedback
Copyright © 1998–2016, Texas Instruments Incorporated
SN74LV374A
SN54LV374A, SN74LV374A
www.ti.com
SCLS408J – APRIL 1998 – REVISED OCTOBER 2016
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LV374A is a low drive CMOS device that can be used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. The inputs accept voltages up to 5.5 V allowing down translation to the VCC level.
9.2 Typical Application
Figure 5 shows how the slower edges can reduce ringing on the output compared to higher drive parts like AC.
Figure 5. Typical Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads
so consider routing and load conditions to prevent ringing.
Submit Documentation Feedback
Copyright © 1998–2016, Texas Instruments Incorporated
SN74LV374A
11
SN54LV374A, SN74LV374A
SCLS408J – APRIL 1998 – REVISED OCTOBER 2016
www.ti.com
Typical Application (continued)
9.2.2 Detailed Design Procedure
• Recommended Input conditions:
– Rise time and fall time specs see (Δt/ΔV) in Recommended Operating Conditions.
– Specified High and low levels. See (VIH and VIL) in Recommended Operating Conditions.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
• Recommended output conditions:
– Load currents should not exceed 35 mA per output and 70 mA total for the part.
– Outputs should not be pulled above VCC.
9.2.3 Application Curve
Figure 6. Switching Characteristics Comparison
12
Submit Documentation Feedback
Copyright © 1998–2016, Texas Instruments Incorporated
SN74LV374A
SN54LV374A, SN74LV374A
www.ti.com
SCLS408J – APRIL 1998 – REVISED OCTOBER 2016
10 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. For devices with a single supply, TI recommends a 0.1-μF capacitor and if there are multiple VCC
terminals then TI recommends a 0.01-μF or 0.022-μF capacitor for each power terminal. Multiple bypass
capacitors can be paralleled to reject different frequencies of noise. Frequencies of 0.1 μF and 1 μF are
commonly used in parallel. The bypass capacitor should be installed as close as possible to the power terminal
for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only
three of the four buffer gates are used. Such input pins should not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. Specified below are the rules that must
be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or
low bias to prevent them from floating. The logic level that should be applied to any particular unused input
depends on the function of the device. Generally they will be tied to GND or VCC whichever make more sense or
is more convenient. Floating outputs is generally acceptable, unless the part is a transceiver. If the transceiver
has an output enable pin it will disable the outputs section of the part when asserted. This will not disable the
input section of the I.O’s so they also cannot float when disabled.
11.2 Layout Example
Figure 7. Layout Example
Submit Documentation Feedback
Copyright © 1998–2016, Texas Instruments Incorporated
SN74LV374A
13
SN54LV374A, SN74LV374A
SCLS408J – APRIL 1998 – REVISED OCTOBER 2016
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54LV374A
Click here
Click here
Click here
Click here
Click here
SN74LV374A
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
Submit Documentation Feedback
Copyright © 1998–2016, Texas Instruments Incorporated
SN74LV374A
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LV374ADBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV374A
SN74LV374ADW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV374A
SN74LV374ADWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV374A
SN74LV374ADWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV374A
SN74LV374ANSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
74LV374A
SN74LV374APW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV374A
SN74LV374APWE4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV374A
SN74LV374APWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV374A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV374A :
• Automotive: SN74LV374A-Q1
• Enhanced Product: SN74LV374A-EP
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LV374ADBR
SSOP
DB
20
2000
330.0
16.4
8.2
7.5
2.5
12.0
16.0
Q1
SN74LV374ADWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74LV374ANSR
SO
NS
20
2000
330.0
24.4
8.4
13.0
2.5
12.0
24.0
Q1
SN74LV374APWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.0
1.4
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV374ADBR
SN74LV374ADWR
SSOP
DB
20
2000
367.0
367.0
38.0
SOIC
DW
20
2000
367.0
367.0
45.0
SN74LV374ANSR
SO
NS
20
2000
367.0
367.0
45.0
SN74LV374APWR
TSSOP
PW
20
2000
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
DB0020A
SSOP - 2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
C
8.2
TYP
7.4
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
18X 0.65
20
1
2X
7.5
6.9
NOTE 3
5.85
10
11
20X
B
5.6
5.0
NOTE 4
SEE DETAIL A
(0.15) TYP
0.38
0.22
0.1
C A B
2 MAX
0.25
GAGE PLANE
0 -8
0.95
0.55
0.05 MIN
DETAIL A
A 15
TYPICAL
4214851/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.85)
(R0.05) TYP
1
20
20X (0.45)
SYMM
18X (0.65)
11
10
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4214851/B 08/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
20X (1.85)
SYMM
(R0.05) TYP
1
20
20X (0.45)
SYMM
18X (0.65)
10
11
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214851/B 08/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising