Texas Instruments | SN74GTL2003 8-Bit Bidirectional Low-Voltage Translator (Rev. C) | Datasheet | Texas Instruments SN74GTL2003 8-Bit Bidirectional Low-Voltage Translator (Rev. C) Datasheet

Texas Instruments SN74GTL2003 8-Bit Bidirectional Low-Voltage Translator (Rev. C) Datasheet
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SN74GTL2003
SCDS305C – FEBRUARY 2011 – REVISED SEPTEMBER 2016
SN74GTL2003 8-Bit Bidirectional Low-Voltage Translator
1 Features
•
1
•
•
•
•
•
•
•
•
•
3 Description
The SN74GTL2003 device provides eight NMOS
pass transistors (Sn and Dn) with a common gate
(GREF) and a reference transistor (SREF and
DREF). The low ON-state resistance of the switch
allows connections to be made with minimal
propagation delay. With no direction control pin
required, the device allows bidirectional voltage
translations any voltage (0.95 V to 5 V) to any
voltage (0.95 V to 5 V).
All transistors in the SN74GTL2003 have the
same electrical characteristics, and there is
minimal deviation from one output to another in
voltage or propagation delay. This offers superior
matching over discrete transistor voltagetranslation solutions where the fabrication of the
transistors is not symmetrical. With all transistors
being
identical,
the
reference
transistor
(SREF/DREF) can be located on any of the other
eight matched Sn/Dn transistors, allowing for
easier board layout. The translator transistors
with integrated ESD circuitry provides excellent
ESD protection.
Provides Bidirectional Voltage Translation With No
Direction Control Required
Allows Voltage Level Translation From 0.95 V Up
to 5 V
Provides Direct Interface With GTL, GTL+,
LVTTL/TTL, and 5-V CMOS Levels
Supports 50 MHz Up/Down Translation at <=20pF
Cap Load
Low ON-State Resistance Between Input and
Output Pins (Sn/Dn)
Supports Hot Insertion
No Power Supply Required – Will Not Latch Up
5-V-Tolerant Inputs
Low Standby Current
Flow-Through Pinout for Ease of Printed Circuit
Board Trace Routing
2 Applications
•
•
•
•
•
•
•
Bidirectional or Unidirectional Applications
Requiring Voltage-Level Translation From Any
Voltage (0.95 V to 5 V) to Any Voltage (0.95 V to
5 V)
Low Voltage Processor I2C Port Translation to
3.3-V or 5-V I2C Bus Signal Levels
GTL/GTL+ Translation to LVTTL/TTL Signal
Levels
HPC Server
Dialysis Machines
Service Router
Servers
Device Information(1)
PART NUMBER
SN74GTL2003
PACKAGE
BODY SIZE (NOM)
TSSOP (20)
6.50 mm × 4.40 mm
VQFN (20)
4.50 mm × 2.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Clamp Schematic
DREF
SREF
GREF
D1
D8
S1
S8
SA00647
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74GTL2003
SCDS305C – FEBRUARY 2011 – REVISED SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
5
5
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 6
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes.......................................... 9
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Applications ................................................ 10
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example .................................................... 15
12 Device and Documentation Support ................. 16
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
13 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2015) to Revision C
Page
•
Updated Features ................................................................................................................................................................... 1
•
Updated pinout images to new format.................................................................................................................................... 3
•
Added Receiving Notification of Documentation Updates section ....................................................................................... 16
Changes from Revision A (March 2013) to Revision B
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
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SCDS305C – FEBRUARY 2011 – REVISED SEPTEMBER 2016
5 Pin Configuration and Functions
PW Package
20-Pin TSSOP
Top View
GND
1
20
GREF
SREF
2
19
DREF
S1
3
18
D1
S2
4
17
D2
S3
5
16
D3
S4
6
15
D4
S5
7
14
D5
S6
8
13
D6
S7
9
12
D7
S8
10
11
D8
20
1
GREF
GND
RKS Package
20-Pin VQFN
Top View
SREF
2
19
DREF
S1
3
18
D1
S2
4
17
D2
S3
5
16
D3
S4
6
15
D4
S5
7
14
D5
S6
8
13
D6
S7
9
12
D7
Thermal
11
10
Pad
D8
S8
Not to scale
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
D1
18
I/O
GTL drain port
D2
17
I/O
GTL drain port
D3
16
I/O
GTL drain port
D4
15
I/O
GTL drain port
D5
14
I/O
GTL drain port
D6
13
I/O
GTL drain port
D7
12
I/O
GTL drain port
D8
11
I/O
GTL drain port
DREF
19
—
Drain of reference transistor, tie directly to GREF and pull up to reference voltage through a 200kΩ resistor
GND
1
—
Ground
GREF
20
—
Gate of reference transistor, tie directly to DREF and pull up to reference voltage through a 200kΩ resistor
S1
3
I/O
LVTTL/TTL source port
S2
4
I/O
LVTTL/TTL source port
S3
5
I/O
LVTTL/TTL source port
S4
6
I/O
LVTTL/TTL source port
S5
7
I/O
LVTTL/TTL source port
S6
8
I/O
LVTTL/TTL source port
S7
9
I/O
LVTTL/TTL source port
S8
10
I/O
LVTTL/TTL source port
SREF
2
—
Source of reference transistor
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VSREF
DC source reference voltage
–0.5
7
V
VDREF
DC drain reference voltage
–0.5
7
V
VGREF
DC gate reference voltage
–0.5
7
V
VSn
DC voltage port Sn
–0.5
7
V
VDn
DC voltage port Dn
7
V
IREFK
DC diode current on reference pins
VI < 0 V
–50
mA
ISK
DC diode current port Sn
VI < 0V
–50
mA
IDK
DC diode current port Dn
VI < 0 V
–50
mA
IMAX
DC clamp current per channel
Channel is ON state
±128
mA
Tstg
Storage temperature
150
°C
(1)
–0.5
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VI/O
Input/output voltage (Sn, Dn)
0
5.5
V
VSREF
DC source reference voltage (1)
0
5.5
V
VDREF
DC drain reference voltage
0
5.5
V
VGREF
DC gate reference voltage
0
5.5
V
IPASS
Pass transistor current
64
mA
TA
Operating ambient temperature (in free air)
85
ºC
(1)
–40
UNIT
VSREF = VDREF – 1.5 V for best results in level-shifting applications.
6.4 Thermal Information
SN74GTL2003
THERMAL METRIC (1)
PW (TSSOP)
RKS (VQFN)
20 PINS
20 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
83
81
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
32
36
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
MIN TYP (1)
MAX
UNIT
260
350
mV
VOL
Low-level output voltage
VDD = 3 V, VSREF = 1.365 V, VSn or VDn = 0.175 V,
Iclamp = 15.2 mA
VIK
Input clamp voltage
II = –18 mA
VGREF = 0 V
–1.2
V
IIH
Gate input leakage
VI = 5 V
VGREF = 0 V
5
µA
CI(GREF)
Gate capacitance
VI = 3 V or 0 V
56
pF
CIO(OFF)
OFF capacitance
VO = 3 V or 0 V
VGREF = 0 V
7.4
pF
CIO(ON)
ON capacitance
VO = 3 V or 0 V
VGREF = 3 V
18.6
pF
VI = 0 V
ron (2)
3.5
5
VGREF = 3 V
4.4
7
VGREF = 2.3 V
IO = 64 mA
5.5
9
67
105
IO = 30 mA
9
15
7
10
IO = 15 mA
58
80
50
70
VGREF = 1.5 V
ON-state resistance
VGREF = 1.5 V,
VGREF = 4.5 V
VI = 2.4 V
VGREF = 3 V
VI = 1.7 V
(1)
(2)
VGREF = 4.5 V
VGREF = 2.3 V
Ω
All typical values are measured at TA = 25°C.
Measured by the voltage drop between the Sn and the Dn terminals at the indicated current through the switch. ON-state resistance is
determined by the lowest voltage of the two (Sn or Dn) terminals.
6.6 Switching Characteristics
VREF = 1.365 V to 1.635 V, VDD1 = 3 V to 3.6 V, VDD2 = 2.36 V to 2.64 V, GND = 0 V, tr = tf ≤ 3 ns, TA = –40°C to +85°C
(see Figure 6) (1)
PARAMETER
tPLH
tPD
(1)
(2)
(3)
(4)
(3)
Propagation delay (Sn to Dn, Dn to Sn)
Propagation delay (4)
MIN
TYP (2)
MAX
0.5
1.5
5.5
UNIT
250
ns
ps
CON(max) of 30 pF and a COFF(max) of 15 pF is specified by design.
All typical values are measured at VDD1 = 3.3 V, VDD2 = 2.5 V, VREF = 1.5 V and TA = 25°C.
Propagation delay specified by characterization.
This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical ON-state
resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
6.7 Typical Characteristics
70
On-State Resistance ( )
60
50
40
30
20
Vi = 0V
Vi = 2.4V
Vi = 1.7V
10
0
0
1
2
3
4
5
6
7
GREF (V)
8
9
10
C001
Figure 1. ON-Resistance vs GREFTypical Curves
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7 Parameter Measurement Information
CL = Load Capacitance, includes jig and probe capacitance (see Electrical Characteristics for value)
AC Waveforms
Vm = 1.5 V, VIN = GND to 3 V
VI
Input
VM
VM
tPHL0
tPLH0
GND
VDD2
VM
Low-to-High
VOL
VM
tPHL
tPLH
tPHL1
VDD2
tPLH1
VM
Low-to-High
VOL
VM
Figure 2. Input (Sn) to Output (Dn) Propagation Delays
VDD2
VDD2
200
150
VDD2
VDD2
150
150
DUT
DREF GREF
D1 . . . D8
SREF
S1 . . . S8
Test
Jig
VREF
Pulse
Generator
Figure 3. Load Circuit
6
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Parameter Measurement Information (continued)
AC Waveforms
3V
Input
1.5 V
1.5 V
tPLH
tPHL
0V
VOH
1.5 V
Output
1.5 V
VOL
Figure 4. Input (Sn) to Output (Dn) Propagation Delays
From Ouput
Under Test
CL = 50 pF
500
S1
7V
500
Figure 5. Load Circuit
Table 1. Test Conditions
TEST
S1
tpd
Open
tPLZ/tPZL
7V
TPHZ/TPZH
Open
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8 Detailed Description
8.1 Overview
The SN74GTL2003 device provides eight NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a
reference transistor (SREF and DREF). The low ON-state resistance of the switch allows connections to be made
with minimal propagation delay. With no direction control pin required, the device allows bidirectional voltage
translations any voltage (0.95 V to 5 V) to any voltage (0.95 V to 5 V).
When the Sn or Dn port is LOW, the clamp is in the ON state and a low-resistance connection exists between
the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is HIGH, the voltage on
the Sn port is limited to the voltage set by the reference transistor (SREF). When the Sn port is HIGH, the Dn port
is pulled to VCC by the pullup resistors.
8.2 Functional Block Diagram
20
GREF
SREF
2
19 D
REF
S1
3
18 D
1
4
17
5
16
S2
S3
D2
D3
8.3 Feature Description
8.3.1 Provides Bidirectional Voltage Translation With No Direction Control Required
Because the circuit acts essentially as a pass transistor, no direction pin is needed, as data is allowed to flow
both ways.
8.3.2 Flow Through Pinout
Allocated pins for input and output A on right side and input and output B on left side. Reduces the need for
multi-layer board layout or long traces through system.
8
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8.4 Device Functional Modes
Table 2. High to Low Translation
(Assuming Dn is at the Higher Voltage Level) (1)
(1)
(2)
(3)
(4)
(5)
GREF (2)
DREF
H
H
0V
H
H
VTT (3)
H
H
VTT
L
L
0 – VTT
SREF
INPUTS
D8–D1
OUTPUT
S8–S1
TRANSISTOR
X
X
Off
H
VTT (4)
On
L
L (5)
On
X
X
Off
H = HIGH voltage level, L = LOW voltage level, X = don't care.
GREF should be at least 1.5 V higher than SREF for best translator operation.
VTT is equal to the SREF voltage.
Sn is not pulled up or pulled down.
Sn follows the Dn input LOW.
Table 3. Low to High Translation
(Assuming Dn is at the Higher Voltage Level) (1)
(1)
(2)
(3)
(4)
(5)
INPUTS
D8–D1
OUTPUT
S8–S1
GREF (2)
DREF
H
H
0V
X
X
Off
H
H
VTT (3)
VTT
H (4)
Nearly Off
H
H
VTT
L
L (5)
On
L
L
0 – VTT
X
X
Off
SREF
TRANSISTOR
H = HIGH voltage level, L = LOW voltage level, X = don't care.
GREF should be at least 1.5 V higher than SREF for best translator operation.
VTT is equal to the SREF voltage.
Dn is pulled up to VCC through an external resistor.
Dn follows the Sn input LOW.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
SN74GTL2003 is a GTL/GTL+ to LVTTL/TTL bidirectional voltage level translator. This device can be used in
both unidirectional applications and bidirectional. Please find the reference schematics and recommended values
for passive components in the Typical Applications.
9.2 Typical Applications
9.2.1 Bidirectional Translation
For the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage),
the GREF input must be connected to DREF and both pins pulled to HIGH-side VCC through a pullup resistor
(typically 200 kΩ). TI recommends a filter capacitor on DREF. The processor output can be totem pole or open
drain (pullup resistors) and the chipset output can be totem pole or open drain (pullup resistors are required to
pull the Dn outputs to VCC). However, if either output is totem pole, data must be unidirectional or the outputs
must be 3-statable, and the outputs must be controlled by some direction-control mechanism to prevent HIGH-toLOW contentions in either direction. If both outputs are open drain, no direction control is needed. The opposite
side of the reference transistor (SREF) is connected to the processor core power-supply voltage. When DREF is
connected through a 200-kΩ resistor to a 3.3-V to 5.5-V VCC supply and SREF is set from 1 V to VCC 1.5 V, the
output of each Sn has a maximum output voltage equal to SREF, and the output of each Dn has a maximum
output voltage equal to VCC.
VDPU = 5 V
200K Ω
VREF = 1.8V
GTL2003
GREF
RPU
RPU
RPU
DREF
SREF
RPU
S1
D1
SW
CPU I/O
Chipset
I/O
S2
D2
SW
VDPU = 3.3V
RPU
S7
D7
S8
D8
RPU
Chipset
I/O
GND
Figure 6. Bidirectional Translation to Multiple Higher Voltage Levels
(Such as an I2C or SMBus Applications)
10
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Typical Applications (continued)
9.2.1.1 Design Requirements
•
•
•
•
SN74GTL2003 requires industry standard GTL and LVTTL/TTL voltage levels.
Place pullup resistors of ~200kΩ in all inputs/outputs to the GTL/TTL voltage levels.
Place 0.1-μF bypass capacitors close to the power supply pins to reduce errors coupling in from noisy or
high-impedance power supplies.
Comply to the parameters in the Recommended Operating Conditions.
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Sizing Pullup Resistors
The pullup resistor value should limit the current through the pass transistor when it is in the on state to about 15
mA. This ensures a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher than
15 mA, the pass voltage also is higher in the on state. To set the current through each pass transistor at 15 mA,
the pullup resistor value is calculated as:
Pullup voltage (V ) - 0.35 V
Resistor value (W ) =
0.015 A
(1)
Table 4 shows resistor values for various reference voltages and currents at 15 mA, 10 mA, and 3 mA. The
resistor value shown in the +10% column, or a larger value, should be used to ensure that the pass voltage of
the transistor would be 350 mV or less. The external driver must be able to sink the total current from the
resistors on both sides of the GTL device at 0.175 V, although the 15 mA only applies to current flowing through
the SN74GTL2003.
Table 4. Pullup Resistor Values (1) (2) (3)
PULLUP RESISTOR VALUE (Ω)
VOLTAGE
(1)
(2)
(3)
15 mA
10 mA
3 mA
NOMINAL
+10%
NOMINAL
+10%
NOMINAL
+10%
5.0 V
310
341
465
512
1550
1705
3.3 V
197
217
295
325
983
1082
2.5 V
143
158
215
237
717
788
1.8 V
97
106
145
160
483
532
1.5 V
77
85
115
127
383
422
1.2 V
57
63
85
94
283
312
Calculated for VOL = 0.35 V
Assumes output driver VOL = 0.175 V at stated current
+10% to compensate for VDD range and resistor tolerance
9.2.1.3 Application Curve
6
Voltage (V)
5
4
3
2
1
CPU I/O
Chipset I/O
0
0
100 200 300 400 500 600 700 800 900 1000
Time (ps)
C001
Figure 7. Signal Voltage vs Time (ps) (Simulated Design Results)
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9.2.2 Unidirectional Down Translation
For unidirectional clamping (higher voltage to lower voltage), the GREF input must be connected to DREF and both
pins pulled to the higher-side VCC through a pullup resistor (typically 200 kΩ). TI recommends a filter capacitor on
DREF. Pullup resistors are required if the chipset I/Os are open drain. The opposite side of the reference
transistor (SREF) is connected to the processor core power supply voltage. When DREF is connected through a
200-kΩ resistor to a 3.3-V to 5.5-V VCC supply and SREF is set from 1 V to VCC – 1.5 V, the output of each Sn has
a maximum output voltage equal to SREF.
VDPU = 5 V
200K Ω
GTL2003
VREF = 1.8V
DREF
SREF
S1
GREF
SW
D1
CPU I/O
S2
D2
Chipset
I/O
SW
Sn
Dn
GND
Figure 8. Unidirectional Down Translation to Protect Low-Voltage Processor Pins
9.2.2.1 Design Requirements
•
•
•
•
SN74GTL2003 requires industry standard GTL and LVTTL/TTL voltage levels.
Place pullup resistors of approximately 200 kΩ in all inputs/outputs to the GTL/TTL voltage levels.
Place 0.1-μF bypass capacitors close to the power supply pins to reduce errors coupling in from noisy or
high-impedance power supplies.
Comply to the parameters in the Recommended Operating Conditions.
9.2.2.2 Detailed Design Procedure
9.2.2.2.1 Sizing Pullup Resistors
The pullup resistor value should limit the current through the pass transistor when it is in the on state to about 15
mA. This ensures a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher than
15 mA, the pass voltage also is higher in the on state. To set the current through each pass transistor at 15 mA,
the pullup resistor value is calculated as:
Pullup voltage (V ) - 0.35 V
Resistor value (W ) =
0.015 A
(2)
Table 5 shows resistor values for various reference voltages and currents at 15 mA, 10 mA, and 3 mA. The
resistor value shown in the +10% column, or a larger value, should be used to ensure that the pass voltage of
the transistor would be 350 mV or less. The external driver must be able to sink the total current from the
resistors on both sides of the GTL device at 0.175 V, although the 15 mA only applies to current flowing through
the SN74GTL2003.
12
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Table 5. Pullup Resistor Values (1) (2) (3)
PULLUP RESISTOR VALUE (Ω)
VOLTAGE
(1)
(2)
(3)
15 mA
10 mA
3 mA
NOMINAL
+10%
NOMINAL
+10%
NOMINAL
+10%
5.0 V
310
341
465
512
1550
1705
3.3 V
197
217
295
325
983
1082
2.5 V
143
158
215
237
717
788
1.8 V
97
106
145
160
483
532
1.5 V
77
85
115
127
383
422
1.2 V
57
63
85
94
283
312
Calculated for VOL = 0.35 V
Assumes output driver VOL = 0.175 V at stated current
+10% to compensate for VDD range and resistor tolerance
9.2.3 Unidirectional Up Translation
For unidirectional up translation (lower voltage to higher voltage), the reference transistor is connected the same
as for a down translation. A pullup resistor is required on the higher voltage side (Dn or Sn) to get the full HIGH
level, because the GTL device only passes the reference source (SREF) voltage as a HIGH when doing an up
translation. The driver on the lower voltage side only needs pullup resistors if it is open drain.
VDPU = 5 V
200K Ω
GTL2003
VREF = 1.8V
GREF
RPU
RPU
RPU
DREF
SREF
RPU
S1
SW
D1
CPU I/O
Chipset
I/O
S2
SW
Sn
D2
Dn
GND
Figure 9. Unidirectional Up Translation to Higher-Voltage Chipsets
9.2.3.1 Design Requirements
•
•
•
•
SN74GTL2003 requires industry standard GTL and LVTTL/TTL voltage levels.
Place pullup resistors of ~200kΩ in all inputs/outputs to the GTL/TTL voltage levels.
Place 0.1-μF bypass capacitors close to the power supply pins to reduce errors coupling in from noisy or
high-impedance power supplies.
Comply to the parameters in the Recommended Operating Conditions
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SCDS305C – FEBRUARY 2011 – REVISED SEPTEMBER 2016
www.ti.com
9.2.3.2 Detailed Design Procedure
9.2.3.2.1 Sizing Pullup Resistors
The pullup resistor value should limit the current through the pass transistor when it is in the on state to about 15
mA. This ensures a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher than
15 mA, the pass voltage also is higher in the on state. To set the current through each pass transistor at 15 mA,
the pullup resistor value is calculated as:
Pullup voltage (V ) - 0.35 V
Resistor value (W ) =
0.015 A
(3)
Table 6 shows resistor values for various reference voltages and currents at 15 mA, 10 mA, and 3 mA. The
resistor value shown in the +10% column, or a larger value, should be used to ensure that the pass voltage of
the transistor would be 350 mV or less. The external driver must be able to sink the total current from the
resistors on both sides of the GTL device at 0.175 V, although the 15 mA only applies to current flowing through
the SN74GTL2003.
Table 6. Pullup Resistor Values (1) (2) (3)
PULLUP RESISTOR VALUE (Ω)
VOLTAGE
(1)
(2)
(3)
15 mA
10 mA
3 mA
NOMINAL
+10%
NOMINAL
+10%
NOMINAL
+10%
5.0 V
310
341
465
512
1550
1705
3.3 V
197
217
295
325
983
1082
2.5 V
143
158
215
237
717
788
1.8 V
97
106
145
160
483
532
1.5 V
77
85
115
127
383
422
1.2 V
57
63
85
94
283
312
Calculated for VOL = 0.35 V
Assumes output driver VOL = 0.175 V at stated current
+10% to compensate for VDD range and resistor tolerance
10 Power Supply Recommendations
Place 0.1-μF bypass capacitors close to the power supply pins to reduce errors coupling in from noisy or highimpedance power supplies.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance.
14
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SCDS305C – FEBRUARY 2011 – REVISED SEPTEMBER 2016
Layout Guidelines (continued)
•
•
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
11.2 Layout Example
Minimize trace
as possible
Minimize stub
as possible
GND 1
20 GREF
SREF 2
19 DREF
S1
3
18 D1
S2
4
17 D2
S3
5
VDD
16 D3
SN74GTL2003
S4
6
15 D4
S5
7
14 D5
S6
8
13 D6
S7
9
12 D7
S8
10
11 D8
Figure 10. Layout Example for GTL Trace
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SN74GTL2003
SCDS305C – FEBRUARY 2011 – REVISED SEPTEMBER 2016
www.ti.com
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Aug-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74GTL2003PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
GK2003
SN74GTL2003PWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
GK2003
SN74GTL2003RKSR
ACTIVE
VQFN
RKS
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
GK2003
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-Aug-2016
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74GTL2003PWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.0
1.4
8.0
16.0
Q1
SN74GTL2003RKSR
VQFN
RKS
20
3000
177.8
12.4
2.73
4.85
1.03
4.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74GTL2003PWR
SN74GTL2003RKSR
TSSOP
PW
20
2000
367.0
367.0
38.0
VQFN
RKS
20
3000
202.0
201.0
28.0
Pack Materials-Page 2
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