Texas Instruments | SN74LV373A Octal Transparent D-Type Latches With 3-State Outputs (Rev. L) | Datasheet | Texas Instruments SN74LV373A Octal Transparent D-Type Latches With 3-State Outputs (Rev. L) Datasheet

Texas Instruments SN74LV373A Octal Transparent D-Type Latches With 3-State Outputs (Rev. L) Datasheet
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SN74LV373A
SCLS407L – APRIL 1998 – REVISED AUGUST 2016
SN74LV373A Octal Transparent D-Type Latches With 3-State Outputs
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
1
•
•
•
•
•
2-V to 5.5-V VCC Operation
Maximum tpd of 8.5 ns at 5 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2.3 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on
All Ports
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 250 mA
Per JESD 17
ESD Protection Exceeds JESD 22
– 3000-V Human-Body Model
– 200-V Machine Model
– 2000-V Charged-Device Model
Printers
Network Switches
Tests and Measurements
Wireless Infratructure
Motor Controls
Server Motherboards
3 Description
The SN74LV373A device is an octal transparent Dtype latch designed for 2-V to 5.5-V VCC operation.
Device Information(1)
PART NUMBER
SN74LV373A
PACKAGE
BODY SIZE (NOM)
VQFN (20)
4.50 x 3.50 mm
SSOP (20)
7.50 x 5.30 mm
TSSOP (20)
6.50 x 4.40 mm
TVSOP (20)
5.00 x 4.40 mm
SOIC (20)
12.80 x 7.50 mm
SO (20)
12.60 mm × 5.30 mm
BGA (20)
4.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
OE
LE
C1
1Q
1D
1D
To Seven Other Channels
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LV373A
SCLS407L – APRIL 1998 – REVISED AUGUST 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
5
5
6
6
7
7
7
7
8
8
8
9
9
9
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements, VCC = 2.5 V ± 0.2 V ..............
Timing Requirements, VCC = 3.3 V ± 0.3 V ..............
Timing Requirements, VCC = 5 V ± 0.5 V .................
Switching Characteristics, VCC = 2.5 V ± 0.2 V ........
Switching Characteristics, VCC = 3.3 V ± 0.3 V ......
Switching Characteristics, VCC = 5 V ± 0.5 V .........
Noise Characteristics ..............................................
Operating Characteristics........................................
Typical Characteristics ............................................
7
8
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
11
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example .................................................... 14
12 Device and Documentation Support ................. 15
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
15
13 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (December 2014) to Revision L
Page
•
Updated Device Information table to include all available packages ..................................................................................... 1
•
Added Pin Functions — BGA table ........................................................................................................................................ 4
•
Changed IOL = 4 mA to IOL = 2 mA and 3 V to 2.3 V for VOL in Electrical Characteristics ..................................................... 7
•
Deleted Related Links section .............................................................................................................................................. 15
•
Added Receiving Notification of Documentation Updates section and Community Resources section .............................. 15
Changes from Revision J (April 2005) to Revision K
Page
•
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ......................................... 6
2
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SCLS407L – APRIL 1998 – REVISED AUGUST 2016
5 Pin Configuration and Functions
DB, DGV, DW, NS, or PW
20-Pin SSOP, TVSOP, SOIC, SO, or TSSOP
Top View
1Q
2
19
8Q
1D
3
18
8D
2D
4
17
7D
2Q
5
16
7Q
3Q
6
15
6Q
3D
7
14
6D
4D
8
13
5D
4Q
9
12
5Q
10
11
LE
1Q
2
19
8Q
1D
3
18
8D
2D
4
17
7D
2Q
5
16
7Q
Thermal
Pad
3Q
6
15
6Q
3D
7
14
6D
4D
8
13
5D
4Q
9
12
5Q
10
GND
VCC
VCC
20
20
11
1
OE
OE
1
RGY Package
20-Pin VQFN
Top View
GND
LE
Not to scale
Not to scale
Pin Functions — SSOP, TVSOP, SOIC, SO, TSSOP, or VQFN
PIN
TYPE
DESCRIPTION
SSOP, TVSOP, SOIC,
SO, or TSSOP
VQFN
1
OE
OE
I
Output Enable
2
1Q
1Q
O
1Q Output
3
1D
1D
I
1D Input
4
2D
2D
I
2D Input
5
2Q
2Q
O
2Q Output
6
3Q
3Q
O
3Q Output
7
3D
3D
I
3D Input
8
4D
4D
I
4D Input
NO.
9
4Q
4Q
O
4Q Output
10
GND
GND
—
Ground Pin
11
LE
LE
I
Latch Enable
12
5Q
5Q
O
5Q Output
13
5D
5D
I
5D Input
14
6D
6D
I
6D Input
15
6Q
6Q
O
6Q Output
16
7Q
7Q
O
7Q Output
17
7D
7D
I
7D Input
18
8D
8D
I
8D Input
19
8Q
8Q
O
8Q Output
20
VCC
VCC
—
Power Pin
—
—
Thermal Pad
—
Thermal Pad, normally tied to GND
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ZQN Package
20-Pin BGA
Bottom View
1
2
3
4
E
GND
4Q
LE
5Q
D
4D
5D
3D
6D
C
3Q
2Q
6Q
7Q
B
2D
7D
1D
8D
A
1Q
OE
VCC
8Q
Not to scale
Pin Functions — BGA
PIN
NO.
NAME
TYPE
DESCRIPTION
A1
1Q
O
1Q Output
A2
OE
I
Output Enable
A3
VCC
—
Power Pin
A4
8Q
O
8Q Output
B1
2D
I
2D Input
B2
7D
I
7D Input
B3
1D
I
1D Input
B4
8D
I
8D Input
C1
3Q
O
3Q Output
C2
2Q
O
2Q Output
C3
6Q
O
6Q Output
C4
7Q
O
7Q Output
D1
4D
I
4D Input
D2
5D
I
5D Input
D3
3D
I
3D Input
D4
6D
I
6D Input
E1
GND
—
Ground Pin
E2
4Q
O
4Q Output
E3
LE
I
Latch Enable
E4
5Q
O
5Q Output
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
7
V
(2)
VI
Input voltage
–0.5
7
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
7
V
VO
Output voltage (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
VO = 0 to VCC
±35
mA
±70
mA
150
°C
Continuous channel current through VCC or GND
Tstg
(1)
(2)
(3)
Storage temperature
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5-V maximum.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
3000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
2000
Machine Model (MM)
200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
MIN
MAX
UNIT
2
5.5
V
1.5
VCC = 2.3 V ± 2.7 V
VCC × 0.7
VCC = 3 V ± 3.6 V
VCC × 0.7
VCC = 4.5 V ± 5.5 V
VCC × 0.7
VCC = 2 V
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
0.5
VCC = 2.3 V ± 2.7 V
VCC × 0.3
VCC = 3 V ± 3.6 V
VCC × 0.3
VCC = 4.5 V ± 5.5 V
IOH
High-level output current
IOL
Low-level output current
Input transition rise or fall
Δt/Δv
TA
(1)
V
V
VCC × 0.3
0
5.5
High or low state
0
VCC
3-state
0
5.5
VCC = 2 V
–50
VCC = 2.3 V ± 2.7 V
–2
VCC = 3 V ± 3.6 V
–8
VCC = 4.5 V ± 5.5 V
–16
VCC = 2 V
50
VCC = 2.3 V ± 2.7 V
2
VCC = 3 V ± 3.6 V
8
VCC = 4.5 V ± 5.5 V
16
VCC = 2.3 V ± 2.7 V
200
VCC = 3 V ± 3.6 V
100
VCC = 4.5 V ± 5.5 V
20
Operating free-air temperature
–40
V
V
µA
mA
µA
mA
125
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
6.4 Thermal Information
SN74LV373A
THERMAL METRIC
(1)
DB
(SSOP)
DGV
(TVSOP)
DW
(SOIC)
NS (SO)
PW
(TSSOP)
RGY
(VQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
94.5
116.2
79.2
76.7
102.4
34.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
56.4
31.2
43.7
43.2
36.5
42.9
°C/W
RθJB
Junction-to-board thermal resistance
49.7
57.7
47.0
44.2
53.6
12.4
°C/W
ψJT
Junction-to-top characterization
parameter
18.5
0.9
18.6
16.8
2.4
0.8
°C/W
ψJB
Junction-to-board characterization
parameter
49.3
57.0
46.5
43.8
52.9
12.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
—
—
—
—
—
7.6
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
VOL
TEST CONDITIONS
TA = 25°C
VCC
MIN
–40°C to +85°C
TYP
MAX
MIN
–40°C to +125°C
MAX
MIN
MAX
IOH = –50 µA
2 V to
5.5 V
VCC – 0.1
VCC – 0.1
VCC – 0.1
IOH = −2 mA
2.3 V
2
2
2
IOH = −8 mA
3V
2.48
2.48
2.48
IOH = −16 mA
4.5 V
3.8
3.8
3.8
IOL = 50 µA
2 V to
5.5 V
IOL = 2 mA
2.3 V
0.4
0.4
0.4
IOL = 8 mA
4.5 V
0.44
0.44
0.44
0.55
0.55
0.55
0.1
IOL = 16 mA
UNIT
V
0.1
0.1
V
VI = 5.5 V or GND
0 V to
5.5 V
±1
±1
±1
µA
IOZ
VI = VCC or GND
5.5 V
±5
±5
±5
µA
ICC
VI = VCC or
GND,
5.5 V
20
20
20
µA
Ioff
VI or VO = 0 to VCC
5
5
5
µA
Ci
VI = VCC or GND
II
IO = 0
0
3.3 V
2.9
pF
6.6 Timing Requirements, VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
TA = 25°C
MIN
MAX
–40°C to +85°C
MIN
MAX
–40°C to +125°C
MIN
MAX
UNIT
tw
Pulse duration, LE high
6
6.5
6.5
ns
tsu
Setup time, data before LE↓
High or low
4.5
5
5.5
ns
th
Hold time, data after LE↓
High or low
1.5
1.5
2
ns
6.7 Timing Requirements, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
TA = 25°C
MIN
tw
Pulse duration, LE high
tsu
Setup time, data before LE↓
th
Hold time, data after LE↓
MAX
–40°C to +85°C
MIN
MAX
–40°C to +125°C
MIN
MAX
UNIT
5
5
5
ns
High or low
4
4
4.5
ns
High or low
1
1
1.5
ns
6.8 Timing Requirements, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
TA = 25°C
MIN
MAX
–40°C to +85°C
MIN
MAX
–40°C to +125°C
MIN
MAX
UNIT
tw
Pulse duration, LE high
5
5
5
ns
tsu
Setup time, data before LE↓
High or low
4
4
4.5
ns
th
Hold time, data after LE↓
High or low
1
1
1.5
ns
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6.9 Switching Characteristics, VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
D
LE
–40°C to
+85°C
TA = 25°C
MIN
MAX
MIN
MAX
Q
8.3 (1) 15.2 (1)
1
17
1
18.5
Q
9.1 (1) 15.7 (1)
1
19
1
20.5
(1)
1
19
1
20
6.2 (1) 12.6 (1)
OE
Q
tdis
OE
Q
D
Q
LE
Q
ten
OE
Q
tdis
OE
Q
MIN
CL = 15 pF
TYP
8.9
CL = 50 pF
(1)
15.8
1
15
1
16.5
10.4
18
1
21
1
22.5
11.1
18.6
1
22
1
23.5
10.9
18.8
1
22
1
23.5
8.3
17.4
1
19
1
20.5
tsk(o)
(1)
–40°C to +125°C
MAX
ten
tpd
LOAD
CAPACITANCE
2
2
UNIT
ns
ns
2
On products compliant to MIL-PRF-38535, this parameter is not production tested.
6.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
D
LOAD
CAPACITANCE
MIN
MAX
MIN
MAX
Q
5.8 (1) 11.4 (1)
1
13.5
1
14.5
LE
Q
6.4 (1)
11 (1)
1
13
1
14
ten
OE
Q
6.3 (1) 11.4 (1)
1
13.5
1
14.5
tdis
OE
Q
4.7 (1)
10 (1)
1
12
1
12.5
D
Q
7.3
14.9
1
17
1
18
LE
Q
7.8
14.5
1
16.5
1
17.5
ten
OE
Q
7.7
14.9
1
17
1
18
tdis
OE
Q
6
13.2
1
15
1
15.5
tpd
MIN
CL = 15 pF
CL = 50 pF
TYP
–40°C to +125°C
MAX
tpd
tsk(o)
(1)
–40°C to
+85°C
TA = 25°C
1.5
1.5
UNIT
ns
ns
1.5
On products compliant to MIL-PRF-38535, this parameter is not production tested.
6.11 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
D
LE
LOAD
CAPACITANCE
TYP
MAX
MIN
MAX
MIN
MAX
Q
4.1 (1)
7.2 (1)
1
8.5
1
9.5
Q
4.5 (1)
7.2 (1)
1
8.5
1
9.5
(1)
(1)
1
9.5
1
10.5
CL = 15 pF
MIN
OE
Q
tdis
OE
Q
3.3 (1)
7.2 (1)
1
8.5
1
9
D
Q
5.1
9.2
1
10.5
1
11.5
5.5
9.2
1
10.5
1
11.5
5.5
10.1
1
11.5
1
12.5
4
9.2
1
10.5
1
11
LE
Q
ten
OE
Q
tdis
OE
Q
CL = 50 pF
4.5
tsk(o)
8
–40°C to +125°C
ten
tpd
(1)
–40°C to
+85°C
TA = 25°C
8.1
1
1
UNIT
ns
ns
1
On products compliant to MIL-PRF-38535, this parameter is not production tested.
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6.12 Noise Characteristics
VCC = 5 V, CL = 50 pF, TA = 25°C (1)
SN74LV373A
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.6
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.6
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
2.9
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
V
2.31
V
0.99
V
VCC
TYP
UNIT
3.3 V
17.4
5V
19.5
Characteristics are for surface-mount packages only.
6.13 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
Outputs enabled
CL = 50 pF,
f = 10 MHz
pF
6.14 Typical Characteristics
6
8
7
5
6
TPD (ns)
TPD (ns)
4
3
5
4
3
2
2
1
1
TPD in ns
0
-100
TPD in ns
0
-50
0
50
Temperature (qC)
100
150
0
D001
Figure 1. TPD vs Temperature at 5 V
1
2
3
VCC
4
5
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D002
Figure 2. TPD vs VCC at 25°C
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7 Parameter Measurement Information
From Output
Under Test
Test
Point
From Output
Under Test
RL = 1 kΩ
S1
VCC
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
tw
0V
th
tsu
VCC
50% VCC
50% VCC
VCC
50% VCC
Timing Input
Input
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
0V
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
50% VCC
0V
≈VCC
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
tPLZ
tPZL
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
50% VCC
VCC
Output
Control
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
10
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SN74LV373A
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SCLS407L – APRIL 1998 – REVISED AUGUST 2016
8 Detailed Description
8.1 Overview
The SN74LV373A device is an octal transparent D-type latch designed for 2-V to 5.5-V VCC operation.
When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q
outputs are latched at the logic levels set up at the D inputs.
At power-up, the state of the Q outputs are not predictable until the first valid clock.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need
for interface or pull-up components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
8.2 Functional Block Diagram
OE
LE
C1
1Q
1D
1D
To Seven Other Channels
8.3 Feature Description
•
•
•
Wide operating voltage range
– Operates from 2 V to 5.5 V
Allows down-voltage translation
– Inputs accept voltages to 5.5 V
Slow edges reduce output ringing
8.4 Device Functional Modes
Table 1 shows the functional modes of SN74LV373A.
Table 1. Function Table
(Each Latch)
INPUTS
OUTPUT
OE
LE
D
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
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11
SN74LV373A
SCLS407L – APRIL 1998 – REVISED AUGUST 2016
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LV540A device is a low-drive CMOS device that can be used for a multitude of bus interface type
applications where putput ringing is a concern. The low drive and slow edge rates will minimize overshoot and
undershoot on the outputs. The inputs are tolerant to 5.5 V at any valid VCC. This feature makes it Ideal for
translating down to the VCC level. Figure 5 shows the reduction in ringing compared to higher drive parts such as
AC.
9.2 Typical Application
5-V regulated
OE
VCC
LE
1D
1Q
5-V µC
System Logic
LEDs
µC or
System Logic
8D
8Q
GND
Figure 4. Typical Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads, so routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions table.
– For specified High and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed 35 mA per output and 70 mA total for the part.
– Outputs should not be pulled above VCC.
12
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SN74LV373A
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SCLS407L – APRIL 1998 – REVISED AUGUST 2016
Typical Application (continued)
9.2.3 Application Curves
Figure 5. Switching Characteristics Comparison
10 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and
1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
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13
SN74LV373A
SCLS407L – APRIL 1998 – REVISED AUGUST 2016
www.ti.com
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 6 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a
transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when
asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.
11.2 Layout Example
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 6. Layout Diagram
14
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SN74LV373A
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SCLS407L – APRIL 1998 – REVISED AUGUST 2016
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: SN74LV373A
15
PACKAGE OPTION ADDENDUM
www.ti.com
14-Sep-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LV373ADBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV373A
SN74LV373ADGVR
ACTIVE
TVSOP
DGV
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV373A
SN74LV373ADW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV373A
SN74LV373ADWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV373A
SN74LV373ADWRG4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV373A
SN74LV373ANSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
74LV373A
SN74LV373APW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV373A
SN74LV373APWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV373A
SN74LV373APWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LV373A
SN74LV373APWRE4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV373A
SN74LV373APWRG4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV373A
SN74LV373APWT
ACTIVE
TSSOP
PW
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV373A
SN74LV373ARGYR
ACTIVE
VQFN
RGY
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LV373A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Sep-2018
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV373A :
• Automotive: SN74LV373A-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
8.2
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
7.5
2.5
12.0
16.0
Q1
SN74LV373ADBR
SSOP
DB
20
2000
330.0
16.4
SN74LV373ADGVR
TVSOP
DGV
20
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV373ADWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74LV373ANSR
SO
NS
20
2000
330.0
24.4
8.4
13.0
2.5
12.0
24.0
Q1
SN74LV373APWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74LV373APWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.0
1.4
8.0
16.0
Q1
SN74LV373APWRG4
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74LV373APWT
TSSOP
PW
20
250
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74LV373ARGYR
VQFN
RGY
20
3000
330.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Dec-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV373ADBR
SSOP
DB
20
2000
367.0
367.0
38.0
SN74LV373ADGVR
TVSOP
DGV
20
2000
367.0
367.0
35.0
SN74LV373ADWR
SOIC
DW
20
2000
367.0
367.0
45.0
SN74LV373ANSR
SO
NS
20
2000
367.0
367.0
45.0
SN74LV373APWR
TSSOP
PW
20
2000
364.0
364.0
27.0
SN74LV373APWR
TSSOP
PW
20
2000
367.0
367.0
38.0
SN74LV373APWRG4
TSSOP
PW
20
2000
367.0
367.0
38.0
SN74LV373APWT
TSSOP
PW
20
250
367.0
367.0
38.0
SN74LV373ARGYR
VQFN
RGY
20
3000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DB0020A
SSOP - 2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
C
8.2
TYP
7.4
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
18X 0.65
20
1
2X
7.5
6.9
NOTE 3
5.85
10
11
20X
B
5.6
5.0
NOTE 4
SEE DETAIL A
(0.15) TYP
0.38
0.22
0.1
C A B
2 MAX
0.25
GAGE PLANE
0 -8
0.95
0.55
0.05 MIN
DETAIL A
A 15
TYPICAL
4214851/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.85)
(R0.05) TYP
1
20
20X (0.45)
SYMM
18X (0.65)
11
10
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4214851/B 08/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
20X (1.85)
SYMM
(R0.05) TYP
1
20
20X (0.45)
SYMM
18X (0.65)
10
11
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214851/B 08/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
GENERIC PACKAGE VIEW
RGY 20
VQFN - 1 mm max height
PLASTIC QUAD FGLATPACK - NO LEAD
3.5 x 4.5, 0.5 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225264/A
www.ti.com
PACKAGE OUTLINE
RGY0020A
VQFN - 1 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
3.65
3.35
A
B
PIN 1 INDEX AREA
4.65
4.35
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
2.05 0.1
2X 1.5
(0.2) TYP
10
11
9
EXPOSED
THERMAL PAD
12
14X 0.5
2X
3.5
21
SYMM
3.05 0.1
2
PIN 1 ID
19
20X
20
1
SYMM
0.30
0.18
0.1
0.05
0.5
20X
0.3
C A B
4225320/A 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGY0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.05)
SYMM
1
20
20X (0.6)
2
19
20X (0.24)
(1.275)
(4.3)
21
SYMM
(3.05)
14X (0.5)
(0.775)
9
12
(R0.05) TYP
( 0.2) TYP
VIA
11
10
(0.75) TYP
(3.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4225320/A 09/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGY0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
4X (0.92)
(R0.05) TYP
20
1
20X (0.6)
2
19
20X (0.24)
4X
(1.33)
21
SYMM
(4.3)
(0.77)
14X (0.5)
(0.56)
9
12
METAL
TYP
11
10
(0.75)
TYP
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 21
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4225320/A 09/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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