Texas Instruments | SN74LVC2G74 Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset (Rev. P) | Datasheet | Texas Instruments SN74LVC2G74 Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset (Rev. P) Datasheet

Texas Instruments SN74LVC2G74 Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset (Rev. P) Datasheet
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SN74LVC2G74
SCES203P – APRIL 1999 – REVISED JULY 2016
SN74LVC2G74 Single Positive-Edge-Triggered D-Type Flip-Flop
With Clear and Preset
1 Features
3 Description
•
This single positive-edge-triggered D-type flip-flop is
designed for 1.65-V to 5.5-V VCC operation.
1
•
•
•
•
•
•
•
•
•
•
Available in the Texas Instruments
NanoFree™ Package
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 5.9 ns at 3.3 V
Low Power Consumption, 10-μA Max ICC
±24-mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 200-V Machine Model
– 1000-V Charged-Device Model
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
A low level at the preset (PRE) or clear (CLR) input
sets or resets the outputs, regardless of the levels of
the other inputs. When PRE and CLR are inactive
(high), data at the data (D) input meeting the setup
time requirements is transferred to the outputs on the
positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not related
directly to the rise time of the clock pulse. Following
the hold-time interval, data at the D input can be
changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
•
•
•
SN74LVC2G74
Servers
LED displays
Network switch
Telecom infrastructure
Motor drivers
I/O Expanders
PACKAGE
BODY SIZE
SM8 (8)
2.95 mm × 2.80 mm
VSSOP (8)
2.30 mm × 2.00 mm
DSBGA (8)
1.91 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
PRE
D
Q
CLK
Q
CLR
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC2G74
SCES203P – APRIL 1999 – REVISED JULY 2016
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
4
4
5
5
6
6
6
7
7
7
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements, –40°C to +85°C.....................
Timing Requirements, –40°C to +125°C...................
Switching Characteristics, –40°C to +85°C...............
Switching Characteristics, –40°C to +125°C.............
Operating Characteristics........................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
8.1
8.2
8.3
8.4
9
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
9
9
9
9
Application and Implementation ........................ 10
9.1 Application Information .......................................... 10
9.2 Typical Power Button Circuit .................................. 10
10 Power Supply Recommendations ..................... 11
11 Layout................................................................... 12
11.1 Layout Guidelines ................................................. 12
11.2 Layout Example .................................................... 12
12 Device and Documentation Support ................. 13
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13
13 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision O (January 2015) to Revision P
Page
•
Changed SSOP to SM8 in Device Information table.............................................................................................................. 1
•
Updated pinout images to new format.................................................................................................................................... 3
•
Added pin number for DSBGA package in Pin Functions table ............................................................................................. 3
•
Changed 6 PINS to 8 PINS in Thermal Information table ...................................................................................................... 5
•
Changed 23 to 2.3 for tsu data in Timing Requirements, –40°C to +125°C ........................................................................... 6
•
Added Receiving Notification of Documentation Updates section and Community Resources section .............................. 13
Changes from Revision N (July 2013) to Revision O
•
Page
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Revision M (February 2007) to Revision N
Page
•
Changed Ioff description in Features....................................................................................................................................... 1
•
Added parameter values for –40 to +125°C temperature ratings in Electrical Characteristics table. .................................... 6
•
Changed Timing Requirements, –40°C to +85°C table.......................................................................................................... 6
•
Added Timing Requirements, –40°C to +125°C table............................................................................................................ 6
•
Changed Switching Characteristics, –40°C to +85°C table.................................................................................................... 7
•
Added Switching Characteristics, –40°C to +125°C table...................................................................................................... 7
2
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5 Pin Configuration and Functions
DCT Package
8-Pin SM8
Top View
DCU Package
8-Pin VSSOP
Top View
CLK
1
8
VCC
D
2
7
PRE
Q
3
6
CLR
GND
4
5
Q
CLK
1
8
VCC
D
2
7
PRE
Q
3
6
CLR
GND
4
5
Q
Not to scale
Not to scale
YZP Package
8-Pin DSBGA
Bottom View
1
2
D
GND
Q
C
Q
CLR
B
D
PRE
A
CLK
VCC
Not to scale
See mecahnical drawings for dimensions.
Pin Functions
PIN
NAME
VSSOP, SM8
DSBGA
TYPE
DESCRIPTION
CLK
1
A1
I
Clock input
CLR
6
C2
I
Clear input - Pull low to set Q output low
D
2
B1
I
Input
GND
4
D1
—
Ground
Q
5
D2
O
Output
Q
3
C1
O
Inverted output
PRE
7
B2
I
Preset input - Pull low to set Q output high
VCC
8
A2
—
Supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage
–0.5
6.5
UNIT
V
(2)
VI
Input voltage
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
150
°C
Continuous current through VCC or GND
Tstg
(1)
(2)
(3)
Storage temperature
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
6.2 ESD Ratings
PARAMETER
V(ESD)
(1)
(2)
4
Electrostatic
discharge
DEFINITION
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Operating
Supply voltage
Data retention only
High-level input voltage
MAX
1.65
5.5
1.7
VCC = 3 V to 3.6 V
V
2
0.7 × VCC
VCC = 1.65 V to 1.95 V
Low-level input voltage
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 4.5 V to 5.5 V
VIL
UNIT
1.5
VCC = 1.65 V to 1.95 V
VIH
MIN
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VCC = 4.5 V to 5.5 V
V
0.3 × VCC
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
VCC = 1.65 V
–4
VCC = 2.3 V
–8
–16
VCC = 3 V
VCC = 4.5 V
–32
VCC = 1.65 V
4
VCC = 2.3 V
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
8
16
VCC = 3 V
mA
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
(1)
mA
–24
ns/V
5
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
6.4 Thermal Information
SN74LVC2G74
THERMAL METRIC (1)
DCT
DCU
YZP
UNIT
102
°C/W
8 PINS
RθJA
(1)
(2)
Junction-to-ambient thermal resistance (2)
220
227
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The package thermal impedance is calculated in accordance with JESD 51-7.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
1.65 V to 5.5 V
1.2
IOH = –8 mA
2.3 V
1.9
1.85
2.4
2.4
2.3
2.3
3V
UNIT
MAX
4.5 V
IOL = 100 μA
1.65 V to 5.5 V
0.1
0.1
IOL = 4 mA
1.65 V
0.45
0.45
IOL = 8 mA
2.3 V
0.3
0.3
0.4
0.4
0.55
0.55
0.55
0.55
0 to 5.5 V
±5
±5
μA
IOL = 16 mA
3.8
V
IOH = –32 mA
3.8
3V
IOL = 32 mA
4.5 V
VI = 5.5 V or GND
Ioff
VI or VO = 5.5 V
ICC
VI = 5.5 V or GND,
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
(1)
TYP
VCC – 0.1
1.2
IOL = 24 mA
II
VCC – 0.1
MIN
1.65 V
IOH = –24 mA
Data or
control inputs
MAX
IOH = –4 mA
IOH = –16 mA
VOL
Recommended
TYP (1)
MIN
IOH = –100 μA
–40°C to +125°C
–40°C to +85°C
VCC
IO = 0
V
0
±10
±10
μA
1.65 V to 5.5 V
10
10
μA
3 V to 5.5 V
500
500
μA
3.3 V
5
5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
6.6 Timing Requirements, –40°C to +85°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
–40°C to +85°C
PARAMETER
FROM
TO
VCC = 1.8 V
± 0.15 V
MIN
VCC = 2.5 V
± 0.2 V
MAX
fclock
MIN
MAX
80
tw
tsu
VCC = 3.3 V
± 0.3 V
MIN
VCC = 5 V
± 0.5 V
MAX
175
MIN
175
MAX
200
CLK
6.2
2.7
2.7
2
PRE or CLR low
6.2
2.7
2.7
2
Data
2.9
1.7
1.3
1.1
PRE or CLR inactive
1.9
1.4
1.2
1
0
0.3
1.2
0.5
th
UNIT
MHz
ns
ns
ns
6.7 Timing Requirements, –40°C to +125°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
–40°C to +125°C
PARAMETER
FROM
TO
VCC = 1.8 V
± 0.15 V
MIN
fclock
tw
tsu
MAX
MIN
80
VCC = 3.3 V
± 0.3 V
MAX
MIN
120
VCC = 5 V
± 0.5 V
MAX
MIN
120
6.2
3.5
3.5
3.3
PRE or CLR low
6.2
3.5
3.5
3.3
Data
2.9
2.3
1.9
1.7
PRE or CLR inactive
1.9
2
1.8
1.6
0
0.3
0.5
0.5
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UNIT
MAX
140
CLK
th
6
VCC = 2.5 V
± 0.2 V
MHz
ns
ns
ns
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6.8 Switching Characteristics, –40°C to +85°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
–40°C to +85°C
PARAMETER
FROM
VCC = 1.8 V
± 0.15 V
TO
MIN
fmax
VCC = 2.5 V
± 0.2 V
MAX
MIN
80
Q
CLK
tpd
Q
PRE or CLR low
Q or Q
VCC = 3.3 V
± 0.3 V
MAX
175
4.8
13.4
6
4.4
MIN
VCC = 5 V
± 0.5 V
MAX
175
MIN
UNIT
MAX
200
MHz
2.2
7.1
2.2
5.9
1.4
4.1
14.4
3
7.7
2.6
6.2
1.6
4.4
12.9
2.3
7
1.7
5.9
1.6
4.1
ns
6.9 Switching Characteristics, –40°C to +125°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
–40°C to +125°C
PARAMETER
FROM
VCC = 1.8 V
± 0.15 V
TO
MIN
fmax
VCC = 2.5 V
± 0.2 V
MAX
MIN
80
Q
CLK
tpd
4.8
Q
PRE or CLR low
Q or Q
VCC = 3.3 V
± 0.3 V
MAX
120
14.4
MIN
VCC = 5 V
± 0.5 V
MAX
120
MIN
UNIT
MAX
140
MHz
2.2
8.1
2.2
6.9
1.4
5.1
6
16
3
9.7
2.6
7.2
1.6
5.4
4.4
14.9
2.3
9.5
1.7
7.9
1.6
6.1
ns
6.10 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
35
35
37
40
UNIT
pF
6.11 Typical Characteristics
10
14
12
VCC = 3 V,
TA = 25°C
tpd – Propagation Delay Time – ns
tpd – Propagation Delay Time – ns
VCC = 3 V,
TA = 25°C
One Output Switching
10
8
6
4
One Output Switching
8
6
4
2
2
0
50
100
150
200
250
300
CL – Load Capacitance – pF
Figure 1. Propagation Delay (Low to High Transition)
vs Load Capacitance
0
50
100
150
200
250
300
CL – Load Capacitance – pF
Figure 2. Propagation Delay (High to Low Transition)
vs Load Capacitance
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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8 Detailed Description
8.1 Overview
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
8.2 Functional Block Diagram
PRE
CLK
7
1
C
C
C
5
Q
TG
C
C
C
C
D
2
TG
TG
TG
3
C
CLR
Q
C
C
6
8.3 Feature Description
•
•
•
Allows down voltage translation
– 5 V to 3.3 V
– 5 V or 3.3 V to 1.8V
Inputs accept voltage levels up to 5.5 V
Ioff Feature
– Can prevent backflow current that can damage device when powered down.
8.4 Device Functional Modes
Table 1 shows the functional modes of SN74LVC2G74.
Table 1. Function Table
INPUTS
(1)
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H (1)
H (1)
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0
Q0
This configuration is non-stable; that is, it does not persist when PRE or CLR returns to its inactive (high) level.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
The resistor and capacitor at the CLR pin are optional. If they are not used, the CLR pin should be connected
directly to VCC to be inactive.
9.2 Typical Power Button Circuit
3V
3V
3V
NC
A
GND
VCC
Y
SN74LVC1G17
CLK
D
Q
GND
VCC
PRE
CLR
Q
MCU
SN74LVC2G74
Figure 4. Device Power Button Circuit
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. Outputs can be combined to
produce higher drive but the high drive will also create faster edges into light loads so routing and load conditions
should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For rise time and fall time specifications, see (Δt/ΔV) in Recommended Operating Conditions table.
– For specified high and low levels, see (VIH and VIL) in Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC
2. Recommend Output Conditions:
– Load currents should not exceed 50 mA per output and 100 mA total for the part.
– Series resistors on the output may be used if the user desires to slow the output edge signal or limit the
output current.
10
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Copyright © 1999–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVC2G74
SN74LVC2G74
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SCES203P – APRIL 1999 – REVISED JULY 2016
Typical Power Button Circuit (continued)
9.2.3 Application Curves
60
40
100
TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
80
TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
20
I OL – mA
I OH – mA
60
0
–20
–40
40
20
–60
0
–80
–100
–1
–0.5 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
–20
–0.2
0.0
VOH – V
Figure 5. Output Current Drive
vs HIGH-Level Output Voltage
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VOL – V
Figure 6. Output Current Drive
vs LOW-Level Output Voltage
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table. Each VCC terminal should have a good bypass capacitor to prevent
power disturbance. For devices with a single supply, a 0.1-μF capacitor is recommended and if there are multiple
VCC terminals then .01-μF or .022-μF capacitors are recommended for each power terminal. It is acceptable to
parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are
commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible
for best results.
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Product Folder Links: SN74LVC2G74
11
SN74LVC2G74
SCES203P – APRIL 1999 – REVISED JULY 2016
www.ti.com
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a
transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when
asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.
11.2 Layout Example
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 7. Layout Diagram
12
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Product Folder Links: SN74LVC2G74
SN74LVC2G74
www.ti.com
SCES203P – APRIL 1999 – REVISED JULY 2016
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
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Copyright © 1999–2016, Texas Instruments Incorporated
Product Folder Links: SN74LVC2G74
13
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LVC2G74DCT3
ACTIVE
SM8
DCT
8
3000
Pb-Free
(RoHS)
CU SNBI
Level-1-260C-UNLIM
-40 to 125
C74
Z
SN74LVC2G74DCTR
ACTIVE
SM8
DCT
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C74
Z
SN74LVC2G74DCTRE4
ACTIVE
SM8
DCT
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C74
Z
SN74LVC2G74DCTRE6
ACTIVE
SM8
DCT
8
3000
Pb-Free
(RoHS)
CU SNBI
Level-1-260C-UNLIM
-40 to 125
C74
Z
SN74LVC2G74DCTRG4
ACTIVE
SM8
DCT
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C74
Z
SN74LVC2G74DCUR
ACTIVE
VSSOP
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(74, C74Q, C74R)
CZ
SN74LVC2G74DCURE4
ACTIVE
VSSOP
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C74R
SN74LVC2G74DCURG4
ACTIVE
VSSOP
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C74R
SN74LVC2G74DCUT
ACTIVE
VSSOP
DCU
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(C74Q, C74R)
SN74LVC2G74DCUTE4
ACTIVE
VSSOP
DCU
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C74R
SN74LVC2G74DCUTG4
ACTIVE
VSSOP
DCU
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C74R
SN74LVC2G74YZPR
ACTIVE
DSBGA
YZP
8
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
CPN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2018
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC2G74 :
• Automotive: SN74LVC2G74-Q1
• Enhanced Product: SN74LVC2G74-EP
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jan-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LVC2G74DCT3
SM8
DCT
8
3000
180.0
13.0
3.35
4.5
1.55
4.0
12.0
Q3
SN74LVC2G74DCTR
SM8
DCT
8
3000
180.0
13.0
3.35
4.5
1.55
4.0
12.0
Q3
SN74LVC2G74DCTRE6
SM8
DCT
8
3000
180.0
13.0
3.35
4.5
1.55
4.0
12.0
Q3
SN74LVC2G74DCUR
VSSOP
DCU
8
3000
180.0
8.4
2.25
3.35
1.05
4.0
8.0
Q3
SN74LVC2G74DCUR
VSSOP
DCU
8
3000
180.0
9.0
2.05
3.3
1.0
4.0
8.0
Q3
SN74LVC2G74DCURG4
VSSOP
DCU
8
3000
180.0
8.4
2.25
3.35
1.05
4.0
8.0
Q3
SN74LVC2G74DCUTG4
VSSOP
DCU
8
250
180.0
8.4
2.25
3.35
1.05
4.0
8.0
Q3
SN74LVC2G74YZPR
DSBGA
YZP
8
3000
178.0
9.2
1.02
2.02
0.63
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jan-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC2G74DCT3
SM8
DCT
8
3000
182.0
182.0
20.0
SN74LVC2G74DCTR
SM8
DCT
8
3000
182.0
182.0
20.0
SN74LVC2G74DCTRE6
SM8
DCT
8
3000
182.0
182.0
20.0
SN74LVC2G74DCUR
VSSOP
DCU
8
3000
202.0
201.0
28.0
SN74LVC2G74DCUR
VSSOP
DCU
8
3000
182.0
182.0
20.0
SN74LVC2G74DCURG4
VSSOP
DCU
8
3000
202.0
201.0
28.0
SN74LVC2G74DCUTG4
VSSOP
DCU
8
250
202.0
201.0
28.0
SN74LVC2G74YZPR
DSBGA
YZP
8
3000
220.0
220.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
YZP0008
DSBGA - 0.5 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.19
0.15
0.05 C
BALL TYP
0.5 TYP
D
C
SYMM
1.5
TYP
0.5
TYP
8X
0.015
D: Max = 1.919 mm, Min =1.858 mm
B
0.25
0.21
C A B
E: Max = 0.918 mm, Min =0.857 mm
A
1
2
SYMM
4223082/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YZP0008
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
8X ( 0.23)
2
1
A
(0.5) TYP
B
SYMM
C
D
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
SOLDER MASK
OPENING
0.05 MAX
( 0.23)
SOLDER MASK
OPENING
0.05 MIN
( 0.23)
METAL
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4223082/A 07/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YZP0008
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
8X ( 0.25)
(R0.05) TYP
1
2
A
(0.5)
TYP
B
SYMM
C
METAL
TYP
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4223082/A 07/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
8
0,13 M
5
0,15 NOM
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
1
0,25
4
0° – 8°
3,15
2,75
0,60
0,20
1,30 MAX
Seating Plane
0,10
0,10
0,00
NOTES: A.
B.
C.
D.
4188781/C 09/02
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion
Falls within JEDEC MO-187 variation DA.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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