Texas Instruments | SN74LV595A 8-Bit Shift Registers With 3-State Output Registers (Rev. Q) | Datasheet | Texas Instruments SN74LV595A 8-Bit Shift Registers With 3-State Output Registers (Rev. Q) Datasheet

Texas Instruments SN74LV595A 8-Bit Shift Registers With 3-State Output Registers (Rev. Q) Datasheet
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SN74LV595A
SCLS414Q – APRIL 1998 – REVISED APRIL 2016
SN74LV595A 8-Bit Shift Registers With 3-State Output Registers
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
1
•
•
•
•
•
•
•
2-V to 5.5-V VCC Operation
Max tpd of 7.1 ns at 5 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2.3 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on All
Ports
8-Bit Serial-In, Parallel-Out Shift
Ioff Supports Live Insertion, Partial Power-Down
Mode, and Back-Drive Protection
Shift Register Has Direct Clear
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 200-V Machine Model
– 1000-V Charged-Device Model
Network Switches
Power Infrastructures
PCs and Notebooks
LED Displays
Servers
I/O Expanders
3 Description
The SN74LV595A device contains an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. Both the shift register clock (SRCLK)
and storage register clock (RCLK) are positive-edge
triggered.
Device Information
PART NUMBER
SNx4LV595A
PACKAGE
BODY SIZE (NOM)
VQFN (16)
4.00 mm × 3.50 mm
TSSOP (16)
5.00 mm × 4.40 mm
SOP (16)
10.20 mm × 5.30 mm
SOIC (16)
9.00 mm × 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
OE
RCLK
SRCLR
SRCLK
SER
1D Q
C1
R
3D
C3 Q
QA
2D Q
C2
R
3D
C3 Q
QB
2D Q
C2
R
3D
C3 Q
QC
2D Q
C2
R
3D
C3 Q
QD
2D Q
C2
R
3D
C3 Q
QE
2D Q
C2
R
3D
C3 Q
QF
2D Q
C2
R
3D
C3 Q
QG
2D Q
C2
R
3D
C3 Q
QH
QH′
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LV595A
SCLS414Q – APRIL 1998 – REVISED APRIL 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Timing Requirements, VCC = 2.5 V ± 0.2 V .............. 6
Timing Requirements, VCC = 3.3 V ± 0.3 V .............. 7
Timing Requirements, VCC = 5 V ± 0.5 V ................. 7
Switching Characteristics, VCC = 2.5 V ± 0.2 V ........ 9
Switching Characteristics, VCC = 3.3 V ± 0.3 V ...... 9
Switching Characteristics, VCC = 5 V ± 0.5 V ....... 10
Noise Characteristics ............................................ 10
Operating Characteristics...................................... 10
Typical Characteristics .......................................... 11
7
8
Parameter Measurement Information ................ 12
Detailed Description ............................................ 13
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
13
13
14
14
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 16
12 Device and Documentation Support ................. 17
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
13 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
Changes from Revision P (October 2014) to Revision Q
Page
•
Changed "Handling Ratings" to "ESD Ratings" ..................................................................................................................... 2
•
Changed "I" to "O" on QA row in Pin Functions table ............................................................................................................. 3
•
Changed "QA Inout" to "QA Output" in Pin Functions table .................................................................................................... 3
•
Changed "Handling Ratings" to "ESD Ratings" ..................................................................................................................... 4
Changes from Revision O (January 2011) to Revision P
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Deleted SN54LV595A from data sheet. ................................................................................................................................. 1
•
Changed Ioff bullet in Features................................................................................................................................................ 1
•
Added Applications. ................................................................................................................................................................ 1
•
Added Pin Functions table...................................................................................................................................................... 3
•
Added Handling Ratings table. ............................................................................................................................................... 4
•
Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ......................................... 5
•
Added Thermal Information table. .......................................................................................................................................... 5
•
Added –40°C to 125°C for SN74LV595A in Electrical Characteristics table.......................................................................... 6
•
Added –40°C to 125°C for SN74LV595A in all three Timing Requirements tables. .............................................................. 6
•
Added –40°C to 125°C for SN74LV595A in all three Switching Requirements tables. ........................................................ 9
•
Added Detailed Description section...................................................................................................................................... 13
•
Added Application and Implementation section.................................................................................................................... 15
•
Added Power Supply Recommendations and Layout sections............................................................................................ 16
2
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SCLS414Q – APRIL 1998 – REVISED APRIL 2016
5 Pin Configuration and Functions
V
Q
B
16
1
Q
C
2
Q
D
3
Q
E
4
Q
F
15
Q
A
14
SER
13
OE_n
5
12
RCLK
Q
G
6
11
SRCLK
Q
H
7
10
SRCLR_n
Thermal
8
9
Q
H'
Pad
GND
R
TSSOP Package
16-Pin D, DW, or PW
Top View
CC
RGY Package
16-Pin VQFN
Top View
Q
B
1
16
V
Q
C
2
15
Q
A
Q
D
3
14
SER
Q
E
4
13
OE_n
Q
F
5
12
RCLK
Q
G
6
11
SRCLK
Q
H
7
10
SRCLR_n
GND
8
9
CC
Q
H'
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
Ground Pin
GND
8
—
OE_n
13
I
Output Enable Pin
QA
15
O
QA Output
QB
1
O
QB Output
QC
2
O
QC Output
QD
3
O
QD Output
QE
4
O
QE Output
QF
5
O
QF Output
QG
6
O
QG Output
QH
7
O
QH Output
QH'
9
O
QH' Output
RCLK
12
I
RCLK Input
SER
14
I
SER Input
SRCLK
11
I
SRCLK Input
SRCLR_n
10
I
SRCLR Input
VCC
16
—
Power Pin
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SCLS414Q – APRIL 1998 – REVISED APRIL 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
Supply voltage range
–0.5
7
V
VI
Input voltage range
(2)
–0.5
7
V
VO
Voltage range applied to any output in the
high-impedance or power-off state (2)
–0.5
7
V
VO
Output voltage range applied in the high or low state (2) (3)
–0.5
VCC + 0.5
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
VO = 0 to VCC
±35
mA
±70
mA
VCC
Continuous current through VCC or GND
(1)
(2)
(3)
UNIT
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5-V maximum.
6.2 ESD Ratings
Tstg
V(ESD)
(1)
(2)
4
MIN
MAX
UNIT
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
Storage temperature range
Electrostatic discharge
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN74LV595A
VCC
MIN
MAX
2
5.5
Supply voltage
VCC = 2 V
VIH
High-level input voltage
Low-level input voltage
VI
VCC = 2.3 V to 2.7 V
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
V
0.5
VCC = 2.3 V to 2.7 V
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC = 4.5 V to 5.5 V
VCC × 0.3
Input voltage
VO
Output voltage
0
5.5
High or low state
0
VCC
3-state
0
5.5
VCC = 2 V
IOH
Δt/Δv
Input transition rise or fall rate
(1)
µA
–8
mA
50
VCC = 2.3 V to 2.7 V
2
VCC = 3 V to 3.6 V
8
VCC = 4.5 V to 5.5 V
16
VCC = 2.3 V to 2.7 V
200
VCC = 3 V to 3.6 V
100
VCC = 4.5 V to 5.5 V
TA
V
–16
VCC = 2 V
Low-level output current
V
–2
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
IOL
V
–50
VCC = 2.3 V to 2.7 V
High-level output current
V
1.5
VCC = 2 V
VIL
UNIT
µA
mA
ns/V
20
Operating free-air temperature
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
6.4 Thermal Information
SN74LV595A
THERMAL METRIC (1)
D
DB
NS
PW
RGY
16 PINS
16 PINS
16 PINS
16 PINS
16 PINS
RθJA
Junction-to-ambient thermal
resistance
80.2
97.8
79.4
106.1
39.5
RθJC(top)
Junction-to-case (top) thermal
resistance
40.3
48.1
35.8
40.8
50.5
RθJB
Junction-to-board thermal
resistance
38.0
48.5
40.2
51.1
17.1
ψJT
Junction-to-top characterization
parameter
9.0
10.0
5.5
3.8
0.9
ψJB
Junction-to-board characterization
parameter
37.7
47.9
39.9
50.6
17.2
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
—
—
—
—
5.9
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
–40°C to 85°C
SN74LV595A
VCC
MIN
VOH
VOL
IOH = –50 µA
2 V to
5.5 V
IOH = –2 mA
2.3 V
QH’
IOH = –6 mA
QA –QH
IOH = –8 mA
QH’
IOH = –12 mA
QA–QH
IOH = –16 mA
4.5 V
IOL = 50 µA
IOL = 2 mA
2.3 V
QH’
IOL = 6 mA
QA−QH
IOL = 8 mA
QH’
IOL = 12 mA
QA−QH
IOL = 16 mA
TYP
MAX
MIN
VCC – 0.1
3V
2 V to
5.5 V
–40°C to 125°C
SN74LV595A
TYP
UNIT
MAX
VCC – 0.1
2
2
2.48
2.45
2.48
2.45
3.8
3.7
3.8
3.7
3V
4.5 V
V
0.1
0.1
0.4
0.4
0.44
0.5
0.44
0.5
0.55
0.6
0.55
0.6
±1
±1
µA
0 to
5.5 V
V
II
VI = 5.5 V or GND
IOZ
VO = VCC or GND,
QA – QH
5.5 V
±5
±5
µA
ICC
VI = VCC or GND,
IO = 0
5.5 V
20
20
µA
Ioff
VI or VO = 0 to 5.5 V
0
5
5
µA
Ci
VI = VCC or GND
3.3 V
3.5
3.5
pF
6.6 Timing Requirements, VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
TA = 25°C
MIN
tw
Pulse duration
(1)
6
Hold time
MAX
MIN
7.5
8.5
RCLK high or low
7
7.5
8.5
SRCLR low
6
6.5
7.5
5.5
5.5
6.5
8
9
10
8.5
9.5
10.5
4
4
5
1.5
1.5
2.5
SRCLR low before RCLK↑
SRCLR high (inactive)
before SRCLK↑
th
MIN
7
SRCLK↑ before RCLK↑ (1)
Setup time
MAX
–40°C to 125°C
SN74LV595A
SRCLK high or low
SER before SRCLK↑
tsu
–40°C to 85°C
SN74LV595A
SER after SRCLK↑
UNIT
MAX
ns
ns
ns
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case
the shift register is one clock pulse ahead of the storage register.
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6.7 Timing Requirements, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
TA = 25°C
MIN
tw
Pulse duration
th
(1)
Hold time
MIN
MAX
MIN
5.5
5.5
6.5
RCLK high or low
5.5
5.5
6.5
5
5
6
3.5
3.5
4.5
SRCLK↑ before RCLK↑ (1)
8
8.5
9.5
SRCLR low before RCLK↑
8
9
10
SRCLR high (inactive)
before SRCLK↑
3
3
4
1.5
1.5
2.5
SER before SRCLK↑
Setup time
MAX
–40°C to 125°C
SN74LV595A
SRCLK high or low
SRCLR low
tsu
–40°C to 85°C
SN74LV595A
SER after SRCLK↑
UNIT
MAX
ns
ns
ns
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case
the shift register is one clock pulse ahead of the storage register.
6.8 Timing Requirements, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
TA = 25°C
MIN
SRCLK high or low
tw
Pulse duration
RCLK high or low
SER before SRCLK↑
SRCLK↑ before RCLK↑
Setup time
th
(1)
Hold time
(1)
SRCLR low before RCLK↑
SRCLR high (inactive)
before SRCLK↑
SER after SRCLK↑
MAX
5
SRCLR low
tsu
–40°C to 85°C
SN74LV595A
MIN
5
MAX
–40°C to 125°C
SN74LV595A
MIN
UNIT
MAX
6
5
5
6
5.2
5.2
6.2
3
3
4
5
5
6
5
5
6
2.5
2.5
3.5
2
2
3
ns
ns
ns
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case
the shift register is one clock pulse ahead of the storage register.
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SRCLK
SER
RCLK
SRCLR
OE
QA
QB
QC
QD
QE
QF
QG
QH
QH′
NOTE:
implies that the output is in 3-State mode.
Copyright © 2016, Texas Instruments Incorporated
Figure 1. Timing Diagram
8
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6.9 Switching Characteristics, VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
fmax
tPLH
tPHL
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
(1)
RCLK
QH’
SRCLR
QH’
OE
OE
RCLK
65 (1)
80 (1)
45
45
CL = 50 pF
60
70
40
40
CL = 15 pF
SRCLR
QH’
CL = 50 pF
QA– QH
QA– QH
MAX
MIN
UNIT
MAX
MHz
1
15.8
1
16.8
8.4 (1)
14.2 (1)
1
15.8
1
16.8
9.4 (1)
19.6 (1)
1
22.2
1
23.2
9.4 (1)
19.6 (1)
1
22.2
1
23.2
8.7 (1)
14.6 (1)
1
16.3
1
17.3
8.2 (1)
13.9 (1)
1
15
1
16
10.9 (1)
18.1 (1)
1
20.3
1
21.3
(1)
(1)
1
15.6
1
16.6
9.2 (1)
15.2 (1)
1
16.7
1
17.7
11.2
17.2
1
19.3
1
21.3
11.2
17.2
1
19.3
1
21.3
13.1
22.5
1
25.5
1
27.5
13.1
22.5
1
25.5
1
27.5
12.4
18.8
1
21.1
1
23.1
10.8
17
1
18.3
1
20.3
13.4
21
1
23
1
25
12.2
18.3
1
19.5
1
21.5
14
20.9
1
22.6
1
24.6
8.3
QA– QH
MIN
(1)
8.4
QA– QH
QH’
OE
CL = 15 pF
QA– QH
SRCLK
OE
TYP
(1)
MAX
–40°C to 125°C
SN74LV595A
MIN
QA– QH
SRCLK
–40°C to 85°C
SN74LV595A
TA = 25°C
14.2
13.7
ns
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
6.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
fmax
tPLH
tPHL
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
(1)
RCLK
QH’
SRCLR
QH’
OE
OE
RCLK
80 (1)
120 (1)
70
70
CL = 50 pF
55
105
50
50
QA– QH
SRCLR
QH’
QA– QH
QA– QH
CL = 50 pF
MIN
MAX
MIN
UNIT
MAX
MHz
6 (1)
11.9 (1)
1
13.5
1
14.5
6 (1)
11.9 (1)
1
13.5
1
14.5
6.6 (1)
13 (1)
1
15
1
16
6.6 (1)
13 (1)
1
15
1
16
6.2 (1)
12.8 (1)
1
13.7
1
14.7
(1)
(1)
1
13.5
1
14.5
7.8 (1)
11.5 (1)
1
13.5
1
14.5
6.1 (1)
14.7 (1)
1
15.2
1
16.2
6.3 (1)
14.7 (1)
1
15.2
1
16.2
7.9
15.4
1
17
1
19
7.9
15.4
1
17
1
19
9.2
16.5
1
18.5
1
20.5
9.2
16.5
1
18.5
1
20.5
9
16.3
1
17.2
1
19.2
7.8
15
1
17
1
19
9.6
15
1
17
1
19
8.1
15.7
1
16.2
1
18.2
9.3
15.7
1
16.2
1
18.2
6
QA– QH
QH’
OE
CL = 15 pF
QA– QH
SRCLK
OE
TYP
CL = 15 pF
MAX
–40°C to 125°C
SN74LV595A
MIN
QA– QH
SRCLK
–40°C to 85°C
SN74LV595A
TA = 25°C
11.5
ns
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
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6.11 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPLH
tPHL
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
(1)
RCLK
QH’
SRCLR
QH’
OE
RCLK
135 (1)
170 (1)
115
115
CL = 50 pF
120
140
95
95
CL = 15 pF
QH’
QA–QH
QA–QH
MAX
MIN
UNIT
MAX
MHz
1
8.5
1
4.3 (1)
7.4 (1)
1
8.5
1
9.5
4.5 (1)
8.2 (1)
1
9.4
1
10.4
4.5 (1)
8.2 (1)
1
9.4
1
10.4
4.5 (1)
8 (1)
1
9.1
1
10.1
4.3 (1)
8.6 (1)
1
10
1
11
5.4 (1)
8.6 (1)
1
10
1
11
(1)
(1)
1
7.1
1
7.1
2.7 (1)
5.1 (1)
1
7.2
1
7.2
5.6
9.4
1
10.5
1
12.5
5.6
9.4
1
10.5
1
12.5
6.4
10.2
1
11.4
1
13.4
6.4
10.2
1
11.4
1
13.4
6.4
10
1
11.1
1
13.1
5.7
10.6
1
12
1
14
6.8
10.6
1
12
1
14
3.5
10.3
1
11
1
13
3.4
10.3
1
11
1
13
2.4
CL = 50 pF
MIN
(1)
4.3
QA–QH
SRCLR
OE
CL = 15 pF
QA–QH
QH’
OE
TYP
(1)
MAX
–40°C to 125°C
SN74LV595A
MIN
QA–QH
SRCLK
–40°C to 85°C
SN74LV595A
TA = 25°C
QA–QH
SRCLK
OE
LOAD
CAPACITANCE
7.4
6
9.5
ns
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
6.12 Noise Characteristics
VCC = 3.3 V, CL = 50 pF, TA = 25°C (1)
SN74LV595A
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.3
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.2
V
VOH(V)
Quiet output, minimum dynamic VOH
2.8
V
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
2.31
V
0.99
V
Characteristics are for surface-mount packages only.
6.13 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
10
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF,
f = 10 MHz
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VCC
TYP
3.3 V
111
5V
114
UNIT
pF
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6.14 Typical Characteristics
13
CL=50pF
12
tPD (ns)
11
10
9
8
7
6
2.5
3
3.5
4
VCC (V)
4.5
5
C001
Figure 2. TPD vs VCC
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7 Parameter Measurement Information
VCC
From Output
Under Test
Test
Point
RL = 1 kΩ
From Output
Under Test
CL
(see Note A)
S1
Open
TEST
GND
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
CL
(see Note A)
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
50% VCC
Input
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
0V
VOH
50% VCC
VOL
VOH
50% VCC
VOL
50% VCC
tPLZ
tPZL
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
0V
Output
Waveform 1
S1 at VCC
(see Note B)
tPLH
50% VCC
VCC
Output
Control
≈VCC
50% VCC
VOL + 0.3 V
tPHZ
tPZH
50% VCC
VOH − 0.3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output
control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns,
tf ≤ 3 ns.
D.
The outputs are measured one at a time, with one input transition per measurement.
E.
tPLZ and tPHZ are the same as tdis.
tPZL and tPZH are the same as ten.
G.
tPHL and tPLH are the same as tpd.
H.
All parameters and waveforms are not applicable to all devices.
VOH
≈0 V
A.
F.
VOL
Figure 3. Load Circuit and Voltage Waveforms
12
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8 Detailed Description
8.1 Overview
The SN74LV595A device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage
register. The storage register has parallel 3-state outputs. Separate clocks are provided for the shift and storage
registers. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for
cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state. Both the shift
register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are
connected together, the shift register always is one clock pulse ahead of the storage register.
8.2 Functional Block Diagram
OE
RCLK
SRCLR
SRCLK
SER
1D Q
C1
R
3D
C3 Q
QA
2D Q
C2
R
3D
C3 Q
QB
2D Q
C2
R
3D
C3 Q
QC
2D Q
C2
R
3D
C3 Q
QD
2D Q
C2
R
3D
C3 Q
QE
2D Q
C2
R
3D
C3 Q
QF
2D Q
C2
R
3D
C3 Q
QG
2D Q
C2
R
3D
C3 Q
QH
QH′
Copyright © 2016, Texas Instruments Incorporated
Figure 4. Logic Diagram (Positive Logic)
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8.3 Feature Description
•
•
•
•
Inputs are 5-V tolerant allowing for voltage translation down to VCC
Slow edges for reduced noise
Low power
Ioff circuitry allows voltages on the inputs and outputs when VCC = 0 V
8.4 Device Functional Modes
Table 1. Function Table
INPUTS
14
FUNCTION
SER
SRCLK
SRCLR
RCLK
OE
X
X
X
X
H
Outputs QA−QH are disabled.
X
X
X
X
L
Outputs QA−QH are enabled.
X
X
L
X
X
Shift register is cleared.
L
↑
H
X
X
First stage of the shift register goes low.
Other stages store the data of previous stage,
respectively.
H
↑
H
X
X
First stage of the shift register goes high.
Other stages store the data of previous stage,
respectively.
X
X
X
↑
X
Shift-register data is stored in the storage
register.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LV595A is a low-drive CMOS device that can be used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. The inputs are 5-V tolerant allowing for down translation to VCC.
12
13
SRCLR
OC
RCLK
OE
OF
OE
OG
R9
OH
1K
8
R3
270
LED3
R4
270
LED4
GND
R5
270
LED5
R6
270
LED6
R7
270
LED7
R8
270
LED8
1
2
3
4
5
6
7
9
OH*
SN74LV595A
VCC
GND
GND
LED2
OB
OD
µC
270
GND
SRCLK
15
GND
VCC
GND
VCC
11
R2
16
SER
OA
10
LED1
GND
14
270
GND
IC1
R1
GND
VCC
GND
9.2 Typical Application
Copyright © 2016, Texas Instruments Incorporated
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For rise time and fall time specifcations, see Δt/ΔV in the Recommended Operating Conditions table.
– For specified high and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions:
– Load currents should not exceed 35 mA per output and 70 mA total for the part.
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Typical Application (continued)
– Outputs should not be pulled above VCC.
9.2.3 Application Curves
1600
ICC 1.8 V
ICC 2.5 V
ICC 5 V
1400
ICC (mA)
1200
1000
800
600
400
200
0
0
20
40
Frequency (MHz)
60
80
D003
Figure 5. ICC vs Frequency in MHz
10 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1 μF capacitor is recommended. If there are multiple VCC terminals then 0.01 μF or 0.022 μF
capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject
different frequencies of noise. 0.1 μF and 1.0 μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power terminal as possible for the best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 6 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a
transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when
asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.
11.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
Figure 6. Layout Diagram
16
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12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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17
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LV595AD
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV595A
SN74LV595ADR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LV595A
SN74LV595ADRG3
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LV595A
SN74LV595ADRG4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV595A
SN74LV595ANSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
74LV595A
SN74LV595APWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LV595A
SN74LV595APWRG3
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LV595A
SN74LV595APWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV595A
SN74LV595APWT
ACTIVE
TSSOP
PW
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV595A
SN74LV595ARGYR
ACTIVE
VQFN
RGY
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LV595A
SN74LV595ARGYRG4
ACTIVE
VQFN
RGY
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LV595A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV595A :
• Automotive: SN74LV595A-Q1
• Enhanced Product: SN74LV595A-EP
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jun-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LV595ADR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
SN74LV595ADR
SOIC
D
16
2500
330.0
16.8
6.5
10.3
2.1
8.0
16.0
Q1
SN74LV595ADRG3
SOIC
D
16
2500
330.0
16.8
6.5
10.3
2.1
8.0
16.0
Q1
SN74LV595ADRG4
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
SN74LV595ANSR
SO
NS
16
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74LV595APWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV595APWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV595APWRG3
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV595APWRG4
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV595APWT
TSSOP
PW
16
250
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV595ARGYR
VQFN
RGY
16
3000
330.0
12.4
3.8
4.3
1.5
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jun-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV595ADR
SOIC
D
16
2500
333.2
345.9
28.6
SN74LV595ADR
SOIC
D
16
2500
364.0
364.0
27.0
SN74LV595ADRG3
SOIC
D
16
2500
364.0
364.0
27.0
SN74LV595ADRG4
SOIC
D
16
2500
333.2
345.9
28.6
SN74LV595ANSR
SO
NS
16
2000
367.0
367.0
38.0
SN74LV595APWR
TSSOP
PW
16
2000
364.0
364.0
27.0
SN74LV595APWR
TSSOP
PW
16
2000
367.0
367.0
35.0
SN74LV595APWRG3
TSSOP
PW
16
2000
364.0
364.0
27.0
SN74LV595APWRG4
TSSOP
PW
16
2000
367.0
367.0
35.0
SN74LV595APWT
TSSOP
PW
16
250
367.0
367.0
35.0
SN74LV595ARGYR
VQFN
RGY
16
3000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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