Texas Instruments | SN74AVCH1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Level-Shifting, Voltage Translation, and 3-State Outputs (Rev. E) | Datasheet | Texas Instruments SN74AVCH1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Level-Shifting, Voltage Translation, and 3-State Outputs (Rev. E) Datasheet

Texas Instruments SN74AVCH1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Level-Shifting, Voltage Translation, and 3-State Outputs (Rev. E) Datasheet
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SN74AVCH1T45
SCES598E – JULY 2004 – REVISED MARCH 2016
SN74AVCH1T45 Single-Bit Dual-Supply Bus Transceiver
With Configurable Level-Shifting, Voltage Translation, and 3-State Outputs
1 Features
2 Applications
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1
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Available in the Texas Instruments NanoStar™
and NanoFree™ Packages
Control Inputs (DIR) VIH and VIL Levels Are
Referenced to VCCA Voltage
Bus Hold on Data Inputs Eliminates the Need for
External Pullup and Pulldown Resistors
VCC Isolation
Fully Configurable Dual-Rail Design
I/Os Are 4.6-V Tolerant
Ioff Supports Partial-Power-Down Mode Operation
Typical Max Data Rates
– 500 Mbps (1.8-V to 3.3-V Translation)
– 320 Mbps (<1.8-V to 3.3-V Translation)
– 320 Mbps (Translate to 2.5 V or 1.8 V)
– 280 Mbps (Translate to 1.5 V)
– 240 Mbps (Translate to 1.2 V)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– Human-Body Model (A114-A): 2000 V
– Machine Model (A115-A): 200 V
– Charged-Device Model (C101): 1000 V
Personal Electronics
Industrial
Enterprise
Telecommunications
3 Description
The SN74AVCH1T45 is a single-bit noninverting bus
transceiver that uses two separate configurable
power-supply rails. The A port is designed to track
VCCA, which accepts any supply voltage from 1.2 V to
3.6 V. The B port is designed to track VCCB, which
also accepts any supply voltage from 1.2 V to 3.6 V.
This allows for universal low-voltage bidirectional
translation between any of the 1.2-V, 1.5-V, 1.8-V,
2.5-V, and 3.3-V voltage nodes.
The SN74AVCH1T45 is designed for asynchronous
communication between two data buses. The device
transmits data from either the A bus to the B bus, or
from the B bus to the A bus, depending upon the
logic level at the direction-control (DIR) input.
The SN74AVCH1T45 is designed so that the DIR
input is referenced to VCCA.
Device Information(1)
PART NUMBER
SN74AVCH1T45
PACKAGE
BODY SIZE (NOM)
SC70 (6)
2.00 mm × 1.25 mm
SOT-23 (6)
2.90 mm × 1.60 mm
DSBGA (6)
1.50 mm × 0.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
DIR
A
5
3
4
VCCA
B
VCCB
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AVCH1T45
SCES598E – JULY 2004 – REVISED MARCH 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
8
1
1
1
2
3
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Switching Characteristics, VCCA= 1.2 V .................... 8
Switching Characteristics, VCCA= 1.5 V ± 0.1 V........ 9
Switching Characteristics, VCCA= 1.8 V ± 0.15 V.... 10
Switching Characteristics, VCCA= 2.5 V ± 0.2 V...... 11
Switching Characteristics, VCCA= 3.3 V ± 0.3 V.... 12
Operating Characteristics...................................... 13
Typical Characteristics .......................................... 14
Parameter Measurement Information ................ 16
9
Detailed Description ............................................ 17
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
17
17
17
18
10 Application and Implementation........................ 18
10.1 Application Information.......................................... 18
10.2 Typical Applications .............................................. 18
11 Power Supply Recommendations ..................... 21
12 Layout................................................................... 22
12.1 Layout Guidelines ................................................. 22
12.2 Layout Example .................................................... 22
13 Device and Documentation Support ................. 23
13.1
13.2
13.3
13.4
13.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
14 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (January 2008) to Revision E
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
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5 Description (continued)
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device.
The VCC isolation feature ensures that if either VCCA or VCCB is at GND, then the outputs are in the highimpedance state. The bus-hold circuitry on the powered-up side always stays active.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
6 Pin Configuration and Functions
DBV or DCK Package
6-Pin SOT-23 or SC70
Top View
VCCA
GND
A
1
6
2
5
3
4
YZP Package
6-Pin DSBGA
Bottom View
VCCB
DIR
B
A
GND
VCCA
3 4
2 5
1 6
B
DIR
VCCB
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
A
3
I/O
Input/output A. Referenced to VCCA.
B
4
I/O
Input/output B. Referenced to VCCB.
DIR
5
I
VCCA
1
—
A-port supply voltage. 1.2 V ≤ VCCA ≤ 3.6 V
VCCB
6
—
B-port supply voltage. 1.2 V ≤ VCCB ≤ 3.6 V.
GND
2
—
Ground
Direction control signal. Referenced to VCCA.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage
Input voltage (2)
Voltage applied to any output in the high-impedance or power-off
state (2)
Voltage applied to any output in the high or low state (2) (3)
MIN
MAX
UNIT
VCCA and VCCB
–0.5
4.6
V
I/O ports (A port)
–0.5
4.6
I/O ports (B port)
–0.5
4.6
Control inputs
–0.5
4.6
A port
–0.5
4.6
B port
–0.5
4.6
A port
–0.5
VCCA + 0.5
B port
–0.5
VCCB + 0.5
V
V
V
Input clamp current
VI < 0
–50
mA
Output clamp current
VO < 0
–50
mA
±50
mA
Continuous output current
Continuous through current
±100
mA
Junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
(3)
VCCA, VCCB, or GND
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Machine model, per A115-A
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
see
(1) (2) (3) (4) (5)
MIN
MAX
VCCA
Supply voltage
1.2
3.6
V
VCCB
Supply voltage
1.2
3.6
V
VIH
High-level input voltage (1)
Data inputs (4)
VCCI = 1.2 V to 1.95 V
VCCI × 0.65
VCCI = 1.95 V to 2.7 V
1.6
VCCI = 2.7 V to 3.6 V
VIL
VIH
Low-level input voltage
(1)
High-level input voltage
Data inputs
(4)
DIR
(referenced to VCCA) (5)
4
V
2
VCCI = 1.2 V to 1.95 V
VCCI × 0.35
VCCI = 1.95 V to 2.7 V
0.7
VCCI = 2.7 V to 3.6 V
0.8
VCCI = 1.2 V to 1.95 V
VCCA × 0.65
VCCI = 1.95 V to 2.7 V
1.6
VCCI = 2.7 V to 3.6 V
(1)
(2)
(3)
(4)
(5)
UNIT
V
V
2
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
All unused control inputs of the device must be held at VCCI or GND to ensure proper device operation.
For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V.
For VCCI values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V.
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Recommended Operating Conditions (continued)
see (1)(2)(3)(4)(5)
MIN
VIL
Low-level input voltage
VI
Input voltage
Output voltage (2)
VO
IOH
DIR
(referenced to VCCA) (5)
MAX
VCCI = 1.2 V to 1.95 V
VCCA × 0.35
VCCI = 1.95 V to 2.7 V
0.7
VCCI = 2.7 V to 3.6 V
0.8
Control Inputs (3)
0
3.6
Active state
0
VCCO
3-state
0
3.6
High-level output current
VCCO = 1.2 V
–3
VCCO = 1.4 V to 1.6 V
–6
VCCO = 1.65 V to 1.95 V
–8
VCCO = 2.3 V to 2.7 V
–9
VCCO = 3 V to 3.6 V
IOL
Low-level output current
Input transition rise or fall rate
TA
Operating free-air temperature
V
V
V
mA
–12
VCCO = 1.2 V
3
VCCO = 1.4 V to 1.6 V
6
VCCO = 1.65 V to 1.95 V
8
VCCO = 2.3 V to 2.7 V
9
VCCO = 3 V to 3.6 V
Δt/Δv
UNIT
mA
12
–40
5
ns/V
85
°C
7.4 Thermal Information
SN74AVCH1T45
THERMAL METRIC (1)
DBV (SOT-23)
DCK (SC70)
YZP (DSBGA)
6 PINS
6 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance (2)
24.3
290.7
130
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
174.7
97
54
°C/W
RθJB
Junction-to-board thermal resistance
92.4
99.2
51
°C/W
ψJT
Junction-to-top characterization parameter
61.1
2.1
1
°C/W
ψJB
Junction-to-board characterization parameter
92
98.4
50
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
The package thermal impedance is calculated in accordance with JESD 51-7.
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7.5 Electrical Characteristics
All typical limits apply over TA = 25°C, and all maximum and minimum limits apply over TA = –40°C to 85°C (unless otherwise
noted). (1) (2) (3) (4)
PARAMETER
High-level output
voltage (1)
VOH
Low-level output
voltage
VOL
II
TEST CONDITIONS
IBHL
Bus-hold high
sustaining
current (6)
IBHH
Bus-hold low
overdrive
current (3)
IOH = –3 mA, VI= VIH
VCCA = VCCB = 1.2 V
IOH = –6 mA, VI= VIH
VCCA = VCCB = 1.4 V
1.05
IOH = –8 mA, VI= VIH
VCCA = VCCB = 1.65 V
1.2
IOH = –9 mA, VI= VIH
VCCA = VCCB = 2.3 V
1.75
IOH = –12 mA, VI= VIH
VCCA = VCCB = 3 V
IOL = 100 µA, VI= VIL
VCCA = VCCB = 1.2 V to 3.6 V
IOL = 3 mA, VI= VIL
VCCA = VCCB = 1.2 V
IOL = 6 mA, VI= VIL
VCCA = VCCB = 1.4 V
0.35
IOL = 8 mA, VI= VIL
VCCA = VCCB = 1.65 V
0.45
IOL = 9 mA, VI= VIL
VCCA = VCCB = 2.3 V
0.55
IOL = 12 mA, VI= VIL
VCCA = VCCB = 3 V
Ioff
(1)
(2)
(3)
(4)
(5)
(6)
6
Bus-hold high
overdrive
current (4)
0.2
0.15
±0.025
VI = 0.49 V
VCCA = VCCB = 1.4 V
15
VI = 0.58 V
VCCA = VCCB = 1.65 V
25
VI = 0.7 V
VCCA = VCCB = 2.3 V
45
VI = 0.8 V
VCCA = VCCB = 3.3 V
100
VI = 0.78 V
VCCA = VCCB = 1.2 V
VI = 0.91 V
VCCA = VCCB = 1.4 V
–15
VI = 1.07 V
VCCA = VCCB = 1.65 V
–25
VI = 1.6 V
VCCA = VCCB = 2.3 V
–45
VI = 2 V
VCCA = VCCB = 3.3 V
–100
Input and output
Power-off
leakge current
VI = 0 V to 3.6 V,
VO= 0 V to 3.6 V
±1
μA
25
μA
–25
μA
50
VCCA = VCCB = 1.6 V
125
VCCA = VCCB = 1.95 V
200
VCCA = VCCB = 2.7 V
300
VCCA = VCCB = 3.6 V
500
μA
–50
VCCA = VCCB = 1.6 V
–125
VCCA = VCCB = 1.95 V
–200
VCCA = VCCB = 2.7 V
–300
VCCA = VCCB = 3.6 V
–500
VCCA = 0 V,
VCCB = 0 V to 3.6 V
V
0.7
VCCA = VCCB = 1.2 V to 3.6 V
VCCA = VCCB = 1.2 V
VI = 0 to VCC
V
2.3
VI = 0.42 V
VI = 0 to VCC
UNIT
0.95
VCCA = VCCB = 1.2 V
IBHHO
MAX
VCCO - 0.2 V
VCCA = VCCB = 1.2 V
IBHLO
TYP
VCCA = VCCB = 1.2 V to 3.6 V
Control Input (DIR) VI = VCCA or GND
Bus-hold low
sustaining
current (5)
MIN
IOH = –100 μA, VI= VIH
μA
A Port
±0.1
±5
VCCA = 0 V to 3.6 V,
B Port
VCCB = 0 V
±0.1
±5
μA
VCCO is the VCC associated with the output port.
VCCI is the VCC associated with the input port.
An external driver must source at least IBHLO to switch this node from low to high.
An external driver must sink at least IBHHO to switch this node from high to low.
The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND
and then raising it to VIL max.
The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to
VCC and then lowering it to VIH min.
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Electrical Characteristics (continued)
All typical limits apply over TA = 25°C, and all maximum and minimum limits apply over TA = –40°C to 85°C (unless otherwise
noted).(1)(2)(3)(4)
PARAMETER
Off-state output
current (7)
IOZ
Supply current A
port
ICCA
Supply current B
port
ICCB
TEST CONDITIONS
VI = VCCI or GND,
VO = VCCO or GND
VI = VCCI or GND, IO = 0
VI = VCCI or GND, IO = 0
VCCA = 0 V,
VCCB = 3.6 V
VCCA = 3.6 V,
VCCB = 0 V
MIN
TYP
MAX
A Port
±0.5
±5
B port
±0.5
±5
UNIT
μA
VCCA = VCCB = 1.2 V to 3.6 V
10
VCCA = 0 V, VCCB = 3.6 V
–2
VCCA = 3.6 V, VCCB = 0 V
10
VCCA = VCCB = 1.2 V to 3.6 V
10
VCCA = 0 V, VCCB = 3.6 V
10
VCCA = 3.6 V, VCCB = 0 V
–2
20
μA
μA
ICCA +
ICCB
Combined supply
current
VI = VCCI or GND, IO = 0
VCCA = VCCB = 1.2 V to 3.6 V
Ci
Input capacitance
control pin (DIR)
VI = 3.3 V or GND
VCCA = VCCB = 3.3 V
2.5
pF
Cio
Input and output
capacitance A or B VO = 3.3 V or GND
port
VCCA = VCCB = 3.3 V
6
pF
(7)
μA
For I/O ports, the parameter IOZ includes the input leakage current.
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7.6 Switching Characteristics, VCCA= 1.2 V
TA= 25°C (see Figure 11).
PARAMETER
tPLH,
tPHL
tPLH,
tPHL
tPZH,
tPZL
tPZH,
tPZL
tPHZ,
tPLZ
tPHZ,
tPLZ
(1)
8
Propagation delay time:
low-to-high-level output and
high-to-low level output
Propagation delay time:
low-to-high-level output and
high-to-low level output
Enable time:
to high level (1) and
to low level (1)
Enable time:
to high level (1) and
to low level (1)
Disable time:
from high level and
from low level
Disable time:
from high level and
from low level
FROM
(INPUT)
A
B
DIR
DIR
DIR
DIR
TO
(OUTPUT)
B
A
A
B
A
B
TEST CONDITIONS
MIN
TYP
VCCB = 1.2 V
3.3
VCCB = 1.5 V
2.7
VCCB = 1.8 V
2.4
VCCB = 2.5 V
2.3
VCCB = 3.3 V
2.4
VCCB = 1.2 V
3.3
VCCB = 1.5 V
3.1
VCCB = 1.8 V
2.9
VCCB = 2.5 V
2.8
VCCB = 3.3 V
2.7
VCCB = 1.2 V
5.1
VCCB = 1.5 V
5.2
VCCB = 1.8 V
5.3
VCCB = 2.5 V
5.2
VCCB = 3.3 V
3.7
VCCB = 1.2 V
5.3
VCCB = 1.5 V
4.3
VCCB = 1.8 V
4
VCCB = 2.5 V
3.3
VCCB = 3.3 V
3.7
VCCB = 1.2 V
8.5
VCCB = 1.5 V
6.9
VCCB = 1.8 V
6.4
VCCB = 2.5 V
5.5
VCCB = 3.3 V
6.1
VCCB = 1.2 V
8.3
VCCB = 1.5 V
7.8
VCCB = 1.8 V
7.7
VCCB = 2.5 V
7.5
VCCB = 3.3 V
5.9
MAX
UNIT
ns
ns
ns
ns
ns
ns
The enable time is a calculated value, derived using the formula shown in Enable Times.
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7.7 Switching Characteristics, VCCA= 1.5 V ± 0.1 V
All typical limits apply over TA = 25°C, and all maximum and minimum limits apply over TA = –40°C to 85°C (unless otherwise
noted) (see Figure 11).
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
MIN
VCCB = 1.2 V
tPLH,
tPHL
Propagation delay time:
low-to-high-level output and
high-to-low level output
A
B
Propagation delay time:
low-to-high-level output and
high-to-low level output
B
A
Enable time:
to high level (1) and
to low level (1)
DIR
A
5.6
VCCB = 1.8 V ± 0.15 V
0.6
4.2
VCCB = 2.5 V ± 0.2 V
0.5
4.2
VCCB = 3.3 V ± 0.3 V
0.5
Enable time:
to high level (1) and
to low level (1)
DIR
B
tPHZ,
tPLZ
Disable time:
from high level and
from low level
DIR
A
3.8
VCCB = 1.5 V ± 0.1 V
0.6
5.5
VCCB = 1.8 V ± 0.15 V
0.4
5.3
VCCB = 2.5 V ± 0.2 V
0.3
4.9
VCCB = 3.3 V ± 0.3 V
0.3
4.8
1.6
6.7
VCCB = 1.8 V ± 0.15 V
1.5
6.8
VCCB = 2.5 V ± 0.2 V
0.3
6.9
VCCB = 3.3 V ± 0.3 V
0.9
6.9
1.8
8.1
VCCB = 1.8 V ± 0.15 V
1.6
7.1
VCCB = 2.5 V ± 0.2 V
1.1
4.7
VCCB = 3.3 V ± 0.3 V
1.4
4.5
(1)
Disable time:
from high level and
from low level
13.6
VCCB = 1.8 V ± 0.15 V
12.4
VCCB = 2.5 V ± 0.2 V
9.6
VCCB = 1.5 V ± 0.1 V
DIR
B
VCCB = 1.8 V ± 0.15 V
ns
7.7
VCCB = 1.5 V ± 0.1 V
VCCB = 3.3 V ± 0.3 V
tPHZ,
tPLZ
ns
5.1
VCCB = 1.5 V ± 0.1 V
VCCB = 1.2 V
ns
3.8
VCCB = 1.5 V ± 0.1 V
VCCB = 1.2 V
ns
2.6
VCCB = 1.2 V
tPZH,
tPZL
UNIT
2.9
0.7
VCCB = 1.2 V
tPZH,
tPZL
MAX
VCCB = 1.5 V ± 0.1 V
VCCB = 1.2 V
tPLH,
tPHL
TYP
ns
9.3
6.7
12.3
12
VCCB = 2.5 V ± 0.2 V
11.1
VCCB = 3.3 V ± 0.3 V
10.7
ns
The enable time is a calculated value, derived using the formula shown in Enable Times.
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7.8 Switching Characteristics, VCCA= 1.8 V ± 0.15 V
All typical limits apply over TA = 25°C, and all maximum and minimum limits apply over TA = –40°C to 85°C (unless otherwise
noted) (see Figure 11).
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
MIN
VCCB = 1.2 V
tPLH,
tPHL
Propagation delay time:
low-to-high-level output and
high-to-low level output
A
B
Propagation delay time:
low-to-high-level output and
high-to-low level output
B
A
Enable time:
to high level (1) and
to low level (1)
DIR
A
2.8
VCCB = 1.8 V ± 0.15 V
0.5
5
VCCB = 2.5 V ± 0.2 V
0.4
3.9
VCCB = 3.3 V ± 0.3 V
0.4
Enable time:
to high level (1) and
to low level (1)
DIR
B
Disable time:
from high level and
from low level
DIR
A
0.5
5.2
VCCB = 1.8 V ± 0.15 V
0.4
5
VCCB = 2.5 V ± 0.2 V
0.3
4.6
VCCB = 3.3 V ± 0.3 V
0.2
4.4
1.6
5.9
VCCB = 1.8 V ± 0.15 V
1.6
5.9
VCCB = 2.5 V ± 0.2 V
1.6
5.9
VCCB = 3.3 V ± 0.3 V
0.5
6
VCCB = 1.5 V ± 0.1 V
1.8
7.7
VCCB = 1.8 V ± 0.15 V
1.4
6.8
VCCB = 2.5 V ± 0.2 V
1
4.4
VCCB = 3.3 V ± 0.3 V
1.4
4.3
(1)
10
B
ns
7.3
VCCB = 1.5 V ± 0.1 V
12.9
VCCB = 1.8 V ± 0.15 V
11.8
VCCB = 2.5 V ± 0.2 V
DIR
ns
5
VCCB = 1.2 V
Disable time:
from high level and
from low level
ns
3.8
VCCB = 1.5 V ± 0.1 V
ns
9
VCCB = 3.3 V ± 0.3 V
tPHZ,
tPLZ
ns
3.4
VCCB = 1.5 V ± 0.1 V
VCCB = 1.2 V
tPHZ,
tPLZ
5.3
2.3
VCCB = 1.2 V
tPZH,
tPZL
UNIT
0.6
VCCB = 1.2 V
tPZH,
tPZL
MAX
VCCB = 1.5 V ± 0.1 V
VCCB = 1.2 V
tPLH,
tPHL
TYP
8.7
6.5
VCCB = 1.5 V ± 0.1 V
11.2
VCCB = 1.8 V ± 0.15 V
10.9
VCCB = 2.5 V ± 0.2 V
9.8
VCCB = 3.3 V ± 0.3 V
9.4
ns
The enable time is a calculated value, derived using the formula shown in Enable Times.
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7.9 Switching Characteristics, VCCA= 2.5 V ± 0.2 V
All typical limits apply over TA = 25°C, and all maximum and minimum limits apply over TA = –40°C to 85°C (unless otherwise
noted) (see Figure 11).
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
MIN
VCCB = 1.2 V
tPLH,
tPHL
Propagation delay time:
low-to-high-level output and
high-to-low level output
A
B
Propagation delay time:
low-to-high-level output and
high-to-low level output
B
A
Enable time:
to high level (1) and
to low level (1)
DIR
A
4.9
VCCB = 1.8 V ± 0.15 V
0.4
4.6
VCCB = 2.5 V ± 0.2 V
0.3
3.4
VCCB = 3.3 V ± 0.3 V
0.3
Enable time:
to high level (1) and
to low level (1)
DIR
B
0.4
4.2
VCCB = 1.8 V ± 0.15 V
0.3
3.8
VCCB = 2.5 V ± 0.2 V
0.2
3.4
VCCB = 3.3 V ± 0.3 V
0.2
3.3
Disable time:
from high level and
from low level
DIR
A
0.3
3.8
VCCB = 1.8 V ± 0.15 V
0.8
3.8
VCCB = 2.5 V ± 0.2 V
0.4
3.8
VCCB = 3.3 V ± 0.3 V
0.5
3.8
7.6
VCCB = 1.8 V ± 0.15 V
1.5
6.5
VCCB = 2.5 V ± 0.2 V
0.6
4.1
VCCB = 3.3 V ± 0.3 V
1
4
(1)
Disable time:
from high level and
from low level
DIR
B
ns
7.1
VCCB = 1.5 V ± 0.1 V
11.8
VCCB = 1.8 V ± 0.15 V
10.3
VCCB = 2.5 V ± 0.2 V
7.5
VCCB = 3.3 V ± 0.3 V
tPHZ,
tPLZ
ns
4.9
2
VCCB = 1.2 V
ns
2.8
VCCB = 1.5 V ± 0.1 V
VCCB = 1.2 V
tPHZ,
tPLZ
3
VCCB = 1.5 V ± 0.1 V
VCCB = 1.5 V ± 0.1 V
ns
2.2
VCCB = 1.2 V
tPZH,
tPZL
UNIT
2.6
0.5
VCCB = 1.2 V
tPZH,
tPZL
MAX
VCCB = 1.5 V ± 0.1 V
VCCB = 1.2 V
tPLH,
tPHL
TYP
ns
7.3
5.4
VCCB = 1.5 V ± 0.1 V
8.6
VCCB = 1.8 V ± 0.15 V
8.1
VCCB = 2.5 V ± 0.2 V
7
VCCB = 3.3 V ± 0.3 V
6.6
ns
The enable time is a calculated value, derived using the formula shown in Enable Times.
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7.10 Switching Characteristics, VCCA= 3.3 V ± 0.3 V
All typical limits apply over TA = 25°C, and all maximum and minimum limits apply over TA = –40°C to 85°C (unless otherwise
noted) (see Figure 11).
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
MIN
VCCB = 1.2 V
tPLH,
tPHL
Propagation delay time:
low-to-high-level output and
high-to-low level output
A
B
Propagation delay time:
low-to-high-level output and
high-to-low level output
B
A
Enable time:
to high level (1) and
to low level (1)
DIR
A
4.7
VCCB = 1.8 V ± 0.15 V
0.3
4.4
VCCB = 2.5 V ± 0.2 V
0.2
3.3
VCCB = 3.3 V ± 0.3 V
0.2
Enable time:
to high level (1) and
to low level (1)
DIR
B
Disable time:
from high level and
from low level
DIR
A
2.8
VCCB = 1.5 V ± 0.1 V
0.4
3.8
VCCB = 1.8 V ± 0.15 V
0.3
3.4
VCCB = 2.5 V ± 0.2 V
0.2
3
VCCB = 3.3 V ± 0.3 V
0.1
2.8
1.3
4.3
VCCB = 1.8 V ± 0.15 V
1.3
4.3
VCCB = 2.5 V ± 0.2 V
1.3
4.3
VCCB = 3.3 V ± 0.3 V
1.3
4.3
VCCB = 1.5 V ± 0.1 V
0.7
7.4
VCCB = 1.8 V ± 0.15 V
0.6
6.5
VCCB = 2.5 V ± 0.2 V
0.7
4
VCCB = 3.3 V ± 0.3 V
1.5
3.9
11.2
VCCB = 1.8 V ± 0.15 V
9.9
VCCB = 2.5 V ± 0.2 V
(1)
12
DIR
B
ns
6.2
VCCB = 1.5 V ± 0.1 V
VCCB = 1.2 V
Disable time:
from high level and
from low level
ns
4
ns
7
VCCB = 3.3 V ± 0.3 V
tPHZ,
tPLZ
ns
3.1
VCCB = 1.5 V ± 0.1 V
VCCB = 1.2 V
tPHZ,
tPLZ
ns
2.2
VCCB = 1.2 V
tPZH,
tPZL
UNIT
2.6
0.4
VCCB = 1.2 V
tPZH,
tPZL
MAX
VCCB = 1.5 V ± 0.1 V
VCCB = 1.2 V
tPLH,
tPHL
TYP
6.7
5.7
VCCB = 1.5 V ± 0.1 V
8.9
VCCB = 1.8 V ± 0.15 V
8.5
VCCB = 2.5 V ± 0.2 V
7.2
VCCB = 3.3 V ± 0.3 V
6.8
ns
The enable time is a calculated value, derived using the formula shown in Enable Times.
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7.11 Operating Characteristics
TA= 25°C
PARAMETER
FROM
(INPUT)
A
CpdA
A
CL = 0 pF,
f = 10 MHz,
tr = tf = 1 ns
A
B
CL = 0 pF,
f = 10 MHz,
tr = tf = 1 ns
CL = 0 pF,
f = 10 MHz,
tr = tf = 1 ns
Power dissipation capacitance
per transceiver (1)
port B
B
(1)
B
TEST CONDITIONS
Power dissipation capacitance
per transceiver (1)
port A
B
CpdB
TO
(OUTPUT)
A
CL = 0 pF,
f = 10 MHz,
tr = tf = 1 ns
TYP
VCCA = VCCB = 1.2 V
3
VCCA = VCCB = 1.5 V
3
VCCA = VCCB = 1.8 V
3
VCCA = VCCB = 2.5 V
3
VCCA = VCCB = 3.3 V
4
VCCA = VCCB = 1.2 V
14
VCCA = VCCB = 1.5 V
14
VCCA = VCCB = 1.8 V
14
VCCA = VCCB = 2.5 V
15
VCCA = VCCB = 3.3 V
16
VCCA = VCCB = 1.2 V
14
VCCA = VCCB = 1.5 V
14
VCCA = VCCB = 1.8 V
14
VCCA = VCCB = 2.5 V
15
VCCA = VCCB = 3.3 V
16
VCCA = VCCB = 1.2 V
3
VCCA = VCCB = 1.5 V
3
VCCA = VCCB = 1.8 V
3
VCCA = VCCB = 2.5 V
3
VCCA = VCCB = 3.3 V
4
UNIT
pF
pF
pF
pF
See CMOS Power Consumption and Cpd Calculation, SCAA035.
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7.12 Typical Characteristics
6
6
5
5
4
4
tPLH - ns
tPHL - ns
TA= 25°C
3
2
3
2
VCCB = 1.2 V
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.5 V
VCCB = 1.8 V
1
VCCB = 1.8 V
1
VCCB = 2.5 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 3.3 V
0
0
0
10
20
30
CL - pF
40
50
60
0
10
20
VCCA= 1.2 V
40
5
5
4
4
tPHL - ns
6
3
2
3
2
VCCB = 1.2 V
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.5 V
VCCB = 1.8 V
1
VCCB = 1.8 V
1
VCCB = 2.5 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 3.3 V
0
10
20
30
40
50
0
60
0
10
20
CL - pF
40
6
6
5
5
4
4
3
2
VCCB = 1.2 V
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.8 V
VCCB = 1.8 V
1
VCCB = 2.5 V
VCCB = 2.5 V
VCCB = 3.3 V
0
10
20
30
40
50
VCCB = 3.3 V
60
0
0
CL - pF
10
20
30
CL - pF
40
50
60
VCCA= 1.8 V
VCCA= 1.8 V
Figure 5. Typical Propagation Delay (A to B) vs
Load Capacitance
14
60
3
VCCB = 1.5 V
1
50
Figure 4. Typical Propagation Delay (A to B) vs
Load Capacitance
tPHL - ns
tPLH - ns
Figure 3. Typical Propagation Delay (A to B) vs
Load Capacitance
2
30
CL - pF
VCCA= 1.5 V
VCCA= 1.5 V
0
60
Figure 2. Typical Propagation Delay (A to B) vs
Load Capacitance
6
0
50
VCCA= 1.2 V
Figure 1. Typical Propagation Delay (A to B) vs
Load Capacitance
tPLH - ns
30
CL - pF
Figure 6. Typical Propagation Delay (A to B) vs
Load Capacitance
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Typical Characteristics (continued)
TA= 25°C
6
6
VCCB = 1.2 V
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.5 V
VCCB = 1.8 V
5
VCCB = 1.8 V
5
VCCB = 2.5 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 3.3 V
4
tPHL - ns
tPLH - ns
4
3
3
2
2
1
1
0
0
10
20
30
40
50
0
60
0
10
20
CL - pF
Figure 7. Typical Propagation Delay (A to B) vs
Load Capacitance
6
VCCB = 1.2 V
VCCB = 1.8 V
VCCB = 1.2 V
VCCB = 1.8 V
5
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 3.3 V
4
4
tPHL - ns
tPLH - ns
60
VCCB = 1.5 V
VCCB = 2.5 V
3
3
2
2
1
1
0
50
Figure 8. Typical Propagation Delay (A to B) vs
Load Capacitance
VCCB = 1.5 V
5
40
VCCA= 2.5 V
VCCA= 2.5 V
6
30
CL - pF
0
10
20
30
40
50
60
0
0
CL - pF
10
20
30
CL - pF
40
50
60
VCCA= 3.3 V
VCCA= 3.3 V
Figure 9. Typical Propagation Delay (A to B) vs
Load Capacitance
Figure 10. Typical Propagation Delay (A to B) vs
Load Capacitance
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8 Parameter Measurement Information
2 × VCCO
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
t pd
t PLZ/t PZL
t PHZ/t PZH
Open
2 × VCCO
GND
RL
tw
LOAD CIRCUIT
VCCI
VCCI/2
Input
VCCO
CL
RL
VTP
1.2 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
15 pF
15 pF
15 pF
15 pF
15 pF
2 kW
2 kW
2 kW
2 kW
2 kW
0.1 V
0.1 V
0.15 V
0.15 V
0.3 V
VCCI/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VCCA
Output
Control
(low-level
enabling)
VCCA/2
VCCA/2
0V
t PLZ
t PZL
VCCI
Input
VCCI/2
VCCI/2
0V
t PLH
Output
t PHL
VOH
VCCO/2
VOL
VCCO/2
VCCO
Output
Waveform 1
S1 at 2 × VCCO
(see Note B)
VCCO/2
VOL + VTP
VOL
t PHZ
t PZH
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCCO/2
VOH – VTP
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 W, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
Figure 11. Load Circuit and Voltage Waveforms
16
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9 Detailed Description
9.1 Overview
The SN74AVCH1T45 is a single-bit, dual-supply, noninverting voltage level translator. Pins A and DIR are
referenced to VCCA, while pin B is referenced to VCCB. Both the A port and B port can accept I/O voltages ranging
from 1.2 V to 3.6 V. The high on DIR allows data transmission from Port A to Port B and a low on DIR allows
data transmission from Port B to Port A. See applications report, AVC Logic Family Technology and Applications
(SCLA015), for more information.
9.2 Functional Block Diagram
DIR
A
5
3
4
VCCA
B
VCCB
9.3 Feature Description
9.3.1 Fully Configurable Dual-Rail Design
Both VCCA and VCCB can be supplied at any voltage from 1.2 V to 3.6 V, making the device suitable for translating
between any of the voltage nodes (1.2 V, 1.8 V, 2.5 V and 3.3 V).
9.3.2 Supports High-Speed Translation
SN74AVCH1T45 can support high data rate applications, which can be calculated from the maximum
propagation delay. This is also dependent on output load. For example, a 1.8-V to 3.3-V conversion yields a
maximum data rate of 500 Mbps.
9.3.3 Partial-Power-Down Mode Operation
Ioff circuitry disables the outputs, preventing damaging current backflow through the SN74AVCH1T45 when it is
powered down. This can occur in applications where subsections of a system are powered down (partial-powerdown) to reduce power consumption.
9.3.4 Active Bus-Hold Circuitry
Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state, which helps with board space
savings and reduced component costs. Use of pullup or pulldown resistors with the bus-hold circuitry is not
recommended. See applications report, Bus-Hold Circuit (SCLA015), for more information.
9.3.5 VCC Isolation
The VCC isolation feature ensures that if either VCCA or VCCB are at GND (or < 0.4 V), both ports will be in a highimpedance state (IOZ as shown in Electrical Characteristics). This prevents false logic levels from being
presented to either bus.
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9.4 Device Functional Modes
Table 1 lists the functional modes of the SN74AVCH1T45.
Table 1. Function Table
DIR
OPERATION
L
B data to A bus
H
A data to B bus
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN74AVCH1T45 device can be used in level-translation applications for interfacing devices or systems
operating at different interface voltages with one another. The maximum data rate can be up to 500 Mbps when
device translate signal from 1.8 V to 3.3 V.
10.2 Typical Applications
10.2.1 Unidirectional Logic Level-Shifting Application
Figure 12 shows an example of the SN74AVCH1T45 being used in a unidirectional logic level-shifting
application.
VCC1
VCC1
VCC2
1
6
2
5
3
4
SYSTEM-1
VCC2
SYSTEM-2
Figure 12. Unidirectional Logic Level-Shifting Application Diagram
Table 2. Data Transmission: SYSTEM-1 and SYSTEM-2
18
PIN
NAME
FUNCTION
1
VCCA
VCC1
SYSTEM-1 supply voltage (1.2 V to 3.6 V)
DESCRIPTION
2
GND
GND
Device GND
3
A
OUT
Output level depends on VCC1 voltage.
4
B
IN
5
DIR
DIR
GND (low level) determines B-port to A-port direction.
6
VCCB
VCC2
SYSTEM-2 supply voltage (1.2 V to 3.6 V)
Input threshold value depends on VCC2 voltage.
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10.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 3.
Table 3. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUES
Input voltage
1.2 V to 3.6 V
Output voltage
1.2 V to 3.6 V
10.2.1.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the SN74AVCH1T45 device to determine the input
voltage range. For a valid logic-high, the value must exceed the VIH of the input port. For a valid logic low
the value must be less than the VIL of the input port.
• Output voltage range
– Use the supply voltage of the device that the SN74AVCH1T45 device is driving to determine the output
voltage range.
10.2.1.3 Application Curve
Figure 13. Translation Up (1.2 V to 3.3 V) at 2.5 MHz
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10.2.2 Bidirectional Logic Level-Shifting Application
Figure 14 shows the SN74AVCH1T45 being used in a bidirectional logic level-shifting application. Because the
SN74AVCH1T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid
bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
VCC1
VCC1
VCC2
I/O-1
VCC2
I/O-2
1
6
2
5
3
4
DIR CTRL
SYSTEM-1
SYSTEM-2
Figure 14. Bidirectional Logic Level-Shifting Application Diagram
The following table shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to
SYSTEM-1.
Table 4. Data Transmission: SYSTEM-1 and SYSTEM-2
STATE
DIR CTRL
I/O-1
I/O-2
1
H
Out
In
DESCRIPTION
2
H
Hi-Z
Hi-Z
SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled.
3
L
Hi-Z
Hi-Z
DIR bit is flipped. I/O-1 and I/O-2 still are disabled.
4
L
In
Out
SYSTEM-2 data to SYSTEM-1
SYSTEM-1 data to SYSTEM-2
10.2.2.1 Design Requirements
Refer to Design Requirements found in Unidirectional Logic Level-Shifting Application.
10.2.2.2 Detailed Design Procedure
10.2.2.2.1 Enable Times
Calculate the enable times for the SN74AVCH1T45 using the following formulas:
• tPZH (DIR to A) = tPLZ(DIR to B) + tPLH (B to A)
• tPZL (DIR to A) = tPHZ(DIR to B) + tPHL (B to A)
• tPZH (DIR to B) = tPLZ(DIR to A) + tPLH (A to B)
• tPZL (DIR to B) = tPHZ(DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74AVCH1T45 initially is transmitting from A to B, then
the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B
port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
20
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Product Folder Links: SN74AVCH1T45
SN74AVCH1T45
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SCES598E – JULY 2004 – REVISED MARCH 2016
10.2.2.3 Application Curve
Figure 15. Translation Up (1.2 V to 3.3 V) at 2.5 MHz
11 Power Supply Recommendations
A proper power-up sequence must be followed to avoid excessive supply current, bus contention, oscillations, or
other anomalies. To guard against such power-up problems, take the following precautions:
1. Connect ground before any supply voltage is applied.
2. Power up VCCA.
3. VCCB can be ramped up along with or after VCCA.
Table 5. Typical Total Static Power Consumption (ICCA + ICCB)
VCCB
VCCA
0V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0V
0
<0.5
<0.5
<0.5
<0.5
<0.5
1.2 V
<0.5
<1
<1
<1
<1
1
1.5 V
<0.5
<1
<1
<1
<1
1
1.8 V
<0.5
<1
<1
<1
<1
<1
2.5 V
<0.5
1
<1
<1
<1
<1
3.3 V
<0.5
1
<1
<1
<1
<1
UNIT
μA
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Product Folder Links: SN74AVCH1T45
21
SN74AVCH1T45
SCES598E – JULY 2004 – REVISED MARCH 2016
www.ti.com
12 Layout
12.1 Layout Guidelines
To
•
•
•
ensure reliability of the device, TI recommends following common printed-circuit board layout guidelines.
Bypass capacitors should be used on power supplies.
Short trace lengths should be used to avoid excessive loading.
Placing pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of
signals depending on the system requirements.
12.2 Layout Example
Figure 16. PCB Layout Example
22
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SN74AVCH1T45
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SCES598E – JULY 2004 – REVISED MARCH 2016
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• Designing with SN74LVCXT245 and SN74LVCHXT245
Translators/Level-Shifters, SLVA746
• Bus-Hold Circuit, SCLA015
• AVC Logic Family Technology and Applications, SCEA006
Family
of
Direction
Controlled
Voltage
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
NanoStar, NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2004–2016, Texas Instruments Incorporated
Product Folder Links: SN74AVCH1T45
23
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
74AVCH1T45DBVRE4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(ET1F ~ ET1R)
74AVCH1T45DBVRG4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(ET1F ~ ET1R)
74AVCH1T45DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(ET1F ~ ET1R)
74AVCH1T45DCKRE4
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(TFF ~ TFR)
74AVCH1T45DCKRG4
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(TFF ~ TFR)
74AVCH1T45DCKTG4
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(TFF ~ TFR)
SN74AVCH1T45DBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(ET1F ~ ET1R)
SN74AVCH1T45DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(ET1F ~ ET1R)
SN74AVCH1T45DCKR
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(TFF ~ TFR)
SN74AVCH1T45DCKT
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(TFF ~ TFR)
SN74AVCH1T45YZPR
ACTIVE
DSBGA
YZP
6
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(TE2 ~ TE7 ~ TEN)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
SN74AVCH1T45DBVR
SOT-23
3000
180.0
8.4
DBV
6
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.23
3.17
1.37
4.0
8.0
Q3
SN74AVCH1T45DBVT
SOT-23
DBV
6
250
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
SN74AVCH1T45DCKR
SC70
DCK
6
3000
180.0
8.4
2.41
2.41
1.2
4.0
8.0
Q3
SN74AVCH1T45DCKT
SC70
DCK
6
250
180.0
8.4
2.41
2.41
1.2
4.0
8.0
Q3
SN74AVCH1T45YZPR
DSBGA
YZP
6
3000
178.0
9.2
1.02
1.52
0.63
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AVCH1T45DBVR
SOT-23
DBV
6
3000
202.0
201.0
28.0
SN74AVCH1T45DBVT
SOT-23
DBV
6
250
202.0
201.0
28.0
SN74AVCH1T45DCKR
SC70
DCK
6
3000
202.0
201.0
28.0
SN74AVCH1T45DCKT
SC70
DCK
6
250
202.0
201.0
28.0
SN74AVCH1T45YZPR
DSBGA
YZP
6
3000
220.0
220.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
6
2X 0.95
1.9
1.45 MAX
3.05
2.75
5
2
4
0.50
6X
0.25
0.2
C A B
3
(1.1)
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X (0.95)
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214840/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X(0.95)
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
YZP0006
DSBGA - 0.5 mm max height
SCALE 9.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.19
0.15
BALL TYP
0.05 C
0.5 TYP
C
SYMM
1
TYP
B
0.5
TYP
D: Max = 1.418 mm, Min =1.358 mm
E: Max = 0.918 mm, Min =0.858 mm
A
6X
0.015
0.25
0.21
C A
B
1
2
SYMM
4219524/A 06/2014
NanoFree Is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
TM
3. NanoFree package configuration.
www.ti.com
EXAMPLE BOARD LAYOUT
YZP0006
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
6X ( 0.225)
1
2
A
(0.5) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
( 0.225)
METAL
0.05 MAX
METAL
UNDER
MASK
0.05 MIN
( 0.225)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4219524/A 06/2014
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017).
www.ti.com
EXAMPLE STENCIL DESIGN
YZP0006
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
6X ( 0.25)
(R0.05) TYP
2
1
A
(0.5)
TYP
SYMM
B
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4219524/A 06/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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