Texas Instruments | SN74LVCH8T245 8-BIT Dual-Supply Bus Transceiver With Configurable Level-Shifting, Voltage Translation, and 3-State Outputs (Rev. B) | Datasheet | Texas Instruments SN74LVCH8T245 8-BIT Dual-Supply Bus Transceiver With Configurable Level-Shifting, Voltage Translation, and 3-State Outputs (Rev. B) Datasheet

Texas Instruments SN74LVCH8T245 8-BIT Dual-Supply Bus Transceiver With Configurable Level-Shifting, Voltage Translation, and 3-State Outputs (Rev. B) Datasheet
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SN74LVCH8T245
SCES637B – AUGUST 2005 – REVISED FEBRUARY 2016
SN74LVCH8T245 8-BIT Dual-Supply Bus Transceiver
With Configurable Level-Shifting, Voltage Translation, and 3-State Outputs
1 Features
•
1
•
•
•
•
•
•
Control Inputs (DIR and OE) VIH and VIL Levels
are Referenced to VCCA
Bus Hold on Data Inputs Eliminates the Need for
External Pullup and Pulldown Resistors
VCC Isolation
Fully Configurable Dual-Rail Design
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
2 Applications
•
•
•
•
Personal Electronics
Industrial
Enterprise
Telecommunications
3 Description
The SN74LVCH8T245 is an 8-bit noninverting bus
transceiver that uses two separate configurable
power-supply rails. The A port is designed to track
VCCA, which accepts any supply voltage from 1.65 V
to 5.5 V. The B port is designed to track VCCB, which
also accepts any supply voltage from 1.65 V to 5.5 V.
This allows for universal low-voltage bidirectional
translation between any of the 1.8-V, 2.5-V, 3.3-V,
and 5.5-V voltage nodes.
The SN74LVCH8T245 is designed for asynchronous
communication between two data buses. The logic
levels of the direction-control (DIR) input and the
output-enable (OE) input activate either the B-port
outputs, the A-port outputs, or place both output ports
into a high-impedance state. The device transmits
data from the A bus to the B bus when the B-port
outputs are activated, and from the B bus to the A
bus when the A-port outputs are activated. The input
circuitry on both A and B ports are always active.
Active bus-hold circuitry holds unused or undriven
inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not
recommended.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device.
The VCC isolation feature ensures that if either VCCA
or VCCB is at GND, then the outputs are in the highimpedance state.
To ensure the high-impedance state during power up
or power down, OE should be tied to VCCA through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
Device Information(1)
PART NUMBER
SN74LVCH8T245
PACKAGE
BODY SIZE (NOM)
SSOP (24)
8.65 mm × 3.90 mm
TVSOP (24)
5.00 mm × 4.40 mm
TSSOP (24)
7.80 mm × 4.40 mm
VQFN (24)
5.50 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
2
DIR
22
OE
3
A1
21
B1
To Seven Other Channels
The SN74LVCH8T245 is designed so that the control
pins (DIR and OE) are referenced to VCCA.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVCH8T245
SCES637B – AUGUST 2005 – REVISED FEBRUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
7
8
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Switching Characteristics: VCCA = 1.8 V ± 0.15 V .... 7
Switching Characteristics: VCCA = 2.5 V ± 0.2 V ...... 8
Switching Characteristics: VCCA = 3.3 V ± 0.3 V ...... 9
Switching Characteristics: VCCA = 5 V ± 0.5 V ....... 10
Operating Characteristics...................................... 11
Typical Characteristics .......................................... 11
Parameter Measurement Information ................ 12
Detailed Description ............................................ 13
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
13
13
13
14
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application .................................................. 15
10 Power Supply Recommendations ..................... 17
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 18
12 Device and Documentation Support ................. 19
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
13 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (February 2007) to Revision B
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
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SCES637B – AUGUST 2005 – REVISED FEBRUARY 2016
5 Pin Configuration and Functions
DB, DGV, or PW Packages
24-Pin SSOP, TVSOP, or TSSOP
Top View
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCCB
VCCB
OE
B1
B2
B3
B4
B5
B6
B7
B8
GND
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
VCCB
23
1
24
23 VCCB
22 OE
2
3
21 B1
20 B2
4
5
19 B3
18 B4
6
7
17 B5
16 B6
8
9
15 B7
14 B8
10
11
12
13
GND
24
2
VCCA
1
GND
VCCA
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
GND
RHL Package
24-Pin VQFN
Top View
Pin Functions
PIN
SSOP,
TVSOP,
TSSOP
VQFN
A1
3
3
I/O
Input/output A1. Referenced to VCCA.
A2
4
4
I/O
Input/output A2. Referenced to VCCA.
A3
5
5
I/O
Input/output A3. Referenced to VCCA.
A4
6
6
I/O
Input/output A4. Referenced to VCCA.
A5
7
7
I/O
Input/output A5. Referenced to VCCA.
A6
8
8
I/O
Input/output A6. Referenced to VCCA.
A7
9
9
I/O
Input/output A7. Referenced to VCCA.
A8
10
10
I/O
Input/output A8. Referenced to VCCA.
B1
21
21
I/O
Input/output B1. Referenced to VCCB.
B2
20
20
I/O
Input/output B2. Referenced to VCCB.
B3
19
19
I/O
Input/output B3. Referenced to VCCB.
B4
18
18
I/O
Input/output B4. Referenced to VCCB.
B5
17
17
I/O
Input/output B5. Referenced to VCCB.
B6
16
16
I/O
Input/output B6. Referenced to VCCB.
B7
15
15
I/O
Input/output B7. Referenced to VCCB.
B8
14
14
I/O
Input/output B8. Referenced to VCCB.
DIR
2
2
I
Direction-control signal. Referenced to VCCA.
OE
22
22
I
3-state output-mode enables. Pull OE high to place all outputs in 3-state mode. Referenced to VCCA.
NAME
I/O
DESCRIPTION
VCCA
1
1
—
A-port supply voltage. 1.65 V ≤ VCCA ≤ 5.5 V
VCCB
23, 24
23, 24
—
B-port supply voltage. 1.65 V ≤ VCCA ≤ 5.5 V
GND
11, 12,
13
11, 12,
13
—
Ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage
Input voltage (2)
Voltage range applied to any output
in the high-impedance or power-off state (2)
Voltage range applied to any output in the high or low state (2) (3)
MIN
MAX
UNIT
VCCA and VCCB
–0.5
6.5
V
I/O ports (A port)
–0.5
6.5
I/O ports (B port)
–0.5
6.5
Control inputs
–0.5
6.5
A port
–0.5
6.5
B port
–0.5
6.5
A port
–0.5
VCCA + 0.5
B port
–0.5
VCCB + 0.5
V
V
V
Input clamp current
VI < 0
–50
mA
Output clamp current
VO < 0
–50
mA
±50
mA
Continuous output current, IO
Continuous through current
±100
mA
Junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
(3)
VCCA, VCCB, and GND
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The output positive-voltage rating may be exceeded up to 6.5 V maximum if the output current rating is observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Machine model (MM)
±200
UNIT
V
JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
VCCA
VCCB
Supply voltage
VCCI = 1.65 V to 4.5 V
VIH
High-level input voltage (1)
Data inputs (4)
VCCI = 2.3 V to 2.7 V
VCCI = 3 V to 3.6 V
VCCI = 4.5 V to 5.5 V
VCCI = 1.65 V to 4.5 V
VIL
Low-level input voltage (1)
Data inputs (4)
(4)
4
MAX
5.5
1.65
5.5
UNIT
V
VCCI × 0.65
1.7
V
2
VCCI × 0.7
VCCI × 0.35
VCCI = 2.3 V to 2.7 V
0.7
VCCI = 3 V to 3.6 V
0.8
VCCI = 4.5 V to 5.5 V
(1)
(2)
(3)
MIN
1.65
V
VCCI × 0.3
VCCI is the VCC associated with the data input port.
VCCO is the VCC associated with the output port.
All unused control inputs of the device must be held at VCCA or GND to ensure proper device operation and minimize power
consumption. See Implications of Slow or Floating CMOS Inputs, SCBA004.
For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL (max) = VCCI × 0.3 V.
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN
VCCI = 1.65 V to 4.5 V
VIH
High-level input voltage
Control inputs
(referenced to VCCA) (5)
MAX
VCCA × 0.65
VCCI = 2.3 V to 2.7 V
1.7
VCCI = 3 V to 3.6 V
V
2
VCCI = 4.5 V to 5.5 V
VCCA × 0.7
VCCI = 1.65 V to 4.5 V
VCCA × 0.35
VCCI = 2.3 V to 2.7 V
0.7
VCCI = 3 V to 3.6 V
0.8
VIL
Low-level input voltage
Control inputs
(referenced to VCCA) (5)
VI
Input voltage
Control inputs (3)
0
5.5
Active state
0
VCCO
3-State
0
5.5
VCCI = 4.5 V to 5.5 V
Input/output voltage (2)
VI/O
IOH
High-level output current
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
Data inputs
(5)
V
VCCA × 0.3
VCCO = 1.65 V to 4.5 V
–4
VCCO = 2.3 V to 2.7 V
–8
VCCO = 3 V to 3.6 V
–24
VCCO = 4.5 V to 5.5 V
–32
VCCO = 1.65 V to 4.5 V
4
VCCO = 2.3 V to 2.7 V
8
VCCO = 3 V to 3.6 V
24
VCCO = 4.5 V to 5.5 V
32
VCCI = 1.65 V to 4.5 V
20
VCCI = 2.3 V to 2.7 V
20
VCCI = 3 V to 3.6 V
10
VCCI = 4.5 V to 5.5 V
TA
UNIT
V
V
mA
mA
ns/V
5
Operating free-air temperature
–40
85
°C
For VCCA values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL (max) = VCCA × 0.3 V.
6.4 Thermal Information
SN74LVCH8T245
THERMAL METRIC (1)
DB (SSOP)
DGV (TVSOP)
PW (TSSOP)
RHL (VQFN)
24 PINS
24 PINS
24 PINS
24 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
88.5
91.1
90.6
37.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
48.7
23.7
27.6
38.1
°C/W
RθJB
Junction-to-board thermal resistance
44.1
44.5
45.3
15.2
°C/W
ψJT
Junction-to-top characterization parameter
12.8
0.6
1.3
0.7
°C/W
ψJB
Junction-to-board characterization
parameter
43.6
44.1
44.8
15.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
—
—
—
4.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
All typical limits apply over TA = 25°C, and all maximum and minimum limits apply over TA = –40°C to 85°C (unless otherwise
noted). (1) (2)
PARAMETER
High-level output
voltage (1)
VOH
Low-level output
voltage
VOL
TEST CONDITIONS
VCCA = VCCB = 1.65 V
1.2
IOH = –8 mA, VI = VIH
VCCA = VCCB = 2.3 V
1.9
IOH = –24 mA, VI = VIH
VCCA = VCCB = 3 V
2.4
IOH = –32 mA, VI = VIH
VCCA = VCCB = 4.5 V
3.8
IOL = 100 μA, VI = VIL
VCCA = VCCB = 1.65 V to 4.5 V
IOL = 4 mA, VI = VIL
VCCA = VCCB = 1.65 V
0.45
IOL = 8 mA, VI = VIL
VCCA = VCCB = 2.3 V
0.3
IOL = 24 mA, VI = VIL
VCCA = VCCB = 3 V
IOL = 32 mA, VI = VIL
VCCA = VCCB = 4.5 V
VI = VCCA or GND
VCCA = VCCB = 1.65 V to 4.5 V
VI = 0.58 V
VCCA = VCCB = 1.65 V
15
VCCA = VCCB = 2.3 V
45
VCCA = VCCB = 3 V
75
IBHL (3)
VI = 0.7 V
Bus-hold low
sustaining current VI = 0.8 V
IBHHO (6)
Ioff
Bus-hold high
overdrive current
VCCA = VCCB = 1.65 V
–15
VI = 1.7 V
VCCA = VCCB = 2.3 V
–45
VCCA = VCCB = 3 V
–75
Input and output
power-off leakage VI or VO = 0 to 5.5 V
current
OE = VIH
IOZ
ICCA
(1)
(2)
(3)
(4)
(5)
(6)
6
Off-state output
current
Supply current
A port
0.55
±0.5
VI = 1.07 V
VI = 0 to VCC
VO = VCCO or GND,
VI = VCCI or GND
OE = X
VI = VCCI or GND, IO = 0
V
0.55
100
VI = 0 to VCC
V
0.1
VCCA = VCCB = 4.5 V
VI = 3.15 V
UNIT
VCCO = 0.1
VI = 1.35 V
Bus-hold high
sustaining current VI = 2 V
Bus-hold low
overdrive current
MAX
IOH = –4 mA, VI = VIH
Control inputs
IBHLO (5)
TYP
VCCA = VCCB = 1.65 V to 4.5 V
II
IBHH (4)
MIN
IOH = –100 μA, VI = VIH
VCCA = VCCB = 4.5 V
–100
VCCA = VCCB = 1.95 V
200
VCCA = VCCB = 2.7 V
300
VCCA = VCCB = 3.6 V
500
VCCA = VCCB = 5.5 V
900
VCCA = VCCB = 1.95 V
–200
VCCA = VCCB = 2.7 V
–300
VCCA = VCCB = 3.6 V
–500
VCCA = VCCB = 5.5 V
–900
±2
μA
μA
μA
μA
μA
VCCA = 0 V,
VCCB = 0 to 5.5 V
A Port
±0.5
±2
VCCA = 0 to 5.5 V,
VCCB = 0 V
B Port
±0.5
±2
VCCA = VCCB =
1.65 V to 4.5 V
A Port,
B Port
±2
VCCA = 0 V,
VCCB = 5.5 V
B Port
±2
VCCA = 5.5 V,
VCCB = 0 V
A Port
±2
μA
VCCA = VCCB = 1.65 V to 4.5 V
20
VCCA = 5 V, VCCB = 0 V
20
VCCA = 0 V, VCCB = 5 V
–2
μA
μA
VCCO is the VCC associated with the output port.
VCCI is the VCC associated with the input port.
The bus-hold circuit can sink at least the minimum low sustaining current at the VIL maximum. IBHL should be measured after lowering
VIN to GND and then raising it to VIL maximum.
The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to
VCC and then lowering it to VIH min.
An external driver must source at least IBHLO to switch this node from low to high.
An external driver must sink at least IBHHO to switch this node from high to low.
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Electrical Characteristics (continued)
All typical limits apply over TA = 25°C, and all maximum and minimum limits apply over TA = –40°C to 85°C (unless otherwise
noted).(1)(2)
PARAMETER
ICCB
Supply current
B port
TEST CONDITIONS
VI = VCCI or GND, IO = 0
MIN
TYP
MAX
VCCA = VCCB = 1.65 V to 4.5 V
20
VCCA = 5 V, VCCB = 0 V
–2
VCCA = 0 V, VCCB = 5 V
20
UNIT
μA
Combined supply
current
VI = VCCI or GND, IO = 0
VCCA = VCCB = 1.65 V to 4.5 V
30
μA
ΔICCA
Supply-current
change DIR
DIR at VCCA - 0.6 V,
B port = open,
A port at VCCA or GND
VCCA = VCCB = 3 to 5.5 V
50
μA
Ci
Input capacitance
VI = VCCA or GND
control inputs
VCCA = VCCB = 3.3 V
4
5
pF
Cio
Input and output
capacitance
A or B port
VCCA = VCCB = 3.3 V
8.5
10
pF
VO = VCCA/B or GND
6.6 Switching Characteristics: VCCA = 1.8 V ± 0.15 V
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) (see Figure 3)
PARAMETER
tPLH, tPHL
tPLH, tPHL
tPHZ, tPLZ
tPHZ, tPLZ
tPZH, tPZL
tPZH, tPZL
FROM
(INPUT)
TO
(OUTPUT)
A
B
OE
OE
OE
OE
B
A
A
B
A
B
TEST CONDITIONS
MIN
MAX
VCCB = 1.8 V ± 0.15 V
1.7
21.9
VCCB = 2.5 V ± 0.2 V
1.3
9.2
VCCB = 3.3 V ± 0.3 V
1
7.4
VCCB = 5 V ± 0.5 V
0.4
7.1
VCCB = 1.8 V ± 0.15 V
0.9
23.8
VCCB = 2.5 V ± 0.2 V
0.8
23.6
VCCB = 3.3 V ± 0.3 V
0.7
23.4
VCCB = 5 V ± 0.5 V
0.7
23.4
VCCB = 1.8 V ± 0.15 V
1.5
29.6
VCCB = 2.5 V ± 0.2 V
1.5
29.4
VCCB = 3.3 V ± 0.3 V
1.5
29.3
VCCB = 5 V ± 0.5 V
1.4
29.2
VCCB = 1.8 V ± 0.15 V
2.4
32.2
VCCB = 2.5 V ± 0.2 V
1.9
13.1
VCCB = 3.3 V ± 0.3 V
1.7
12
VCCB = 5 V ± 0.5 V
1.3
10.3
VCCB = 1.8 V ± 0.15 V
0.4
24
VCCB = 2.5 V ± 0.2 V
0.4
23.8
VCCB = 3.3 V ± 0.3 V
0.4
23.7
VCCB = 5 V ± 0.5 V
0.4
23.7
VCCB = 1.8 V ± 0.15 V
1.8
32
VCCB = 2.5 V ± 0.2 V
1.5
16
VCCB = 3.3 V ± 0.3 V
1.2
12.6
VCCB = 5 V ± 0.5 V
0.9
10.8
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UNIT
ns
ns
ns
ns
ns
ns
7
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SCES637B – AUGUST 2005 – REVISED FEBRUARY 2016
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6.7 Switching Characteristics: VCCA = 2.5 V ± 0.2 V
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 3)
PARAMETER
tPLH, tPHL
tPLH, tPHL
tPHZ, tPLZ
tPHZ, tPLZ
tPZH, tPZL
tPZH, tPZL
FROM
(INPUT)
A
B
OE
OE
OE
OE
TO
(OUTPUT)
B
A
A
B
A
B
TEST CONDITIONS
MIN
MAX
VCCB = 1.8 V ± 0.15 V
1.5
21.4
VCCB = 2.5 V ± 0.2 V
1.2
9
VCCB = 3.3 V ± 0.3 V
0.8
6.2
VCCB = 5 V ± 0.5 V
0.6
4.8
VCCB = 1.8 V ± 0.15 V
1.2
9.3
VCCB = 2.5 V ± 0.2 V
1
9.1
VCCB = 3.3 V ± 0.3 V
1
8.9
VCCB = 5 V ± 0.5 V
0.9
8.8
VCCB = 1.8 V ± 0.15 V
1.4
9
VCCB = 2.5 V ± 0.2 V
1.4
9
VCCB = 3.3 V ± 0.3 V
1.4
9
VCCB = 5 V ± 0.5 V
1.4
9
VCCB = 1.8 V ± 0.15 V
2.3
29.6
VCCB = 2.5 V ± 0.2 V
1.8
11
VCCB = 3.3 V ± 0.3 V
1.7
9.3
VCCB = 5 V ± 0.5 V
0.9
6.9
VCCB = 1.8 V ± 0.15 V
1
10.9
VCCB = 2.5 V ± 0.2 V
1
10.9
VCCB = 3.3 V ± 0.3 V
1
10.9
VCCB = 5 V ± 0.5 V
1
10.9
VCCB = 1.8 V ± 0.15 V
1.7
28.2
VCCB = 2.5 V ± 0.2 V
1.5
12.9
VCCB = 3.3 V ± 0.3 V
1.2
9.4
1
6.9
VCCB = 5 V ± 0.5 V
8
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UNIT
ns
ns
ns
ns
ns
ns
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6.8 Switching Characteristics: VCCA = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 3)
PARAMETER
tPLH, tPHL
tPLH, tPHL
tPHZ, tPLZ
tPHZ, tPLZ
tPZH, tPZL
tPZH, tPZL
FROM
(INPUT)
TO
(OUTPUT)
A
B
OE
OE
OE
OE
B
A
A
B
A
B
TEST CONDITIONS
MIN
MAX
VCCB = 1.8 V ± 0.15 V
1.5
21.2
VCCB = 2.5 V ± 0.2 V
1.1
8.8
VCCB = 3.3 V ± 0.3 V
0.8
6.2
VCCB = 5 V ± 0.5 V
0.5
4.4
VCCB = 1.8 V ± 0.15 V
0.8
7.2
VCCB = 2.5 V ± 0.2 V
0.8
6.2
VCCB = 3.3 V ± 0.3 V
0.7
6.1
VCCB = 5 V ± 0.5 V
0.6
6
VCCB = 1.8 V ± 0.15 V
1.6
8.2
VCCB = 2.5 V ± 0.2 V
1.6
8.2
VCCB = 3.3 V ± 0.3 V
1.6
8.2
VCCB = 5 V ± 0.5 V
1.6
8.2
VCCB = 1.8 V ± 0.15 V
2.1
29
VCCB = 2.5 V ± 0.2 V
1.7
10.3
VCCB = 3.3 V ± 0.3 V
1.5
8.6
VCCB = 5 V ± 0.5 V
0.8
6.3
VCCB = 1.8 V ± 0.15 V
0.8
8.1
VCCB = 2.5 V ± 0.2 V
0.8
8.1
VCCB = 3.3 V ± 0.3 V
0.8
8.1
VCCB = 5 V ± 0.5 V
0.8
8.1
VCCB = 1.8 V ± 0.15 V
1.8
27.7
VCCB = 2.5 V ± 0.2 V
1.4
12.4
VCCB = 3.3 V ± 0.3 V
1.1
8.5
VCCB = 5 V ± 0.5 V
0.9
6.4
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UNIT
ns
ns
ns
ns
ns
ns
9
SN74LVCH8T245
SCES637B – AUGUST 2005 – REVISED FEBRUARY 2016
www.ti.com
6.9 Switching Characteristics: VCCA = 5 V ± 0.5 V
over recommended operating free-air temperature range, VCCA = 5 V ± 0.5 V (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
VCCB = 1.8 V ± 0.15 V
tPLH, tPHL
tPLH, tPHL
tPHZ, tPLZ
A
B
OE
B
A
A
tPZH, tPZL
tPZH, tPZL
OE
OE
OE
B
A
B
1.5
21.4
1
8.8
VCCB = 3.3 V ± 0.3 V
0.7
6
VCCB = 5 V ± 0.5 V
0.4
4.2
VCCB = 1.8 V ± 0.15 V
0.7
7
VCCB = 2.5 V ± 0.2 V
0.4
4.8
VCCB = 3.3 V ± 0.3 V
0.3
4.5
VCCB = 5 V ± 0.5 V
0.3
4.3
VCCB = 1.8 V ± 0.15 V
0.3
5.4
VCCB = 2.5 V ± 0.2 V
0.3
5.4
VCCB = 3.3 V ± 0.3 V
0.3
5.4
VCCB = 5 V ± 0.5 V
0.3
5.4
2
28.7
VCCB = 2.5 V ± 0.2 V
1.6
9.7
VCCB = 3.3 V ± 0.3 V
1.4
8
VCCB = 5 V ± 0.5 V
0.7
5.7
VCCB = 1.8 V ± 0.15 V
0.7
6.4
VCCB = 2.5 V ± 0.2 V
0.7
6.4
VCCB = 3.3 V ± 0.3 V
0.7
6.4
VCCB = 5 V ± 0.5 V
0.7
6.4
VCCB = 1.8 V ± 0.15 V
1.5
27.6
VCCB = 2.5 V ± 0.2 V
1.3
11.4
VCCB = 3.3 V ± 0.3 V
1
8.1
0.9
6
VCCB = 5 V ± 0.5 V
10
MAX
VCCB = 2.5 V ± 0.2 V
VCCB = 1.8 V ± 0.15 V
tPHZ, tPLZ
MIN
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UNIT
ns
ns
ns
ns
ns
ns
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6.10 Operating Characteristics
TA = 25°C
PARAMETER (1)
TEST CONDITIONS
A-port input, B-port output
CL = 0, f = 10 MHz, tr = tf = 1 ns
CpdA (2)
B-port input, A-port output
CL = 0, f = 10 MHz, tr = tf = 1 ns
A-port input, B-port output
CL = 0, f = 10 MHz, tr = tf = 1 ns
CpdB (2)
B-port input, A-port output
(1)
(2)
CL = 0, f = 10 MHz, tr = tf = 1 ns
TYP
VCCA = VCCB = 1.8 V
2
VCCA = VCCB = 2.5 V
2
VCCA = VCCB = 3.3 V
2
VCCA = VCCB = 5 V
3
VCCA = VCCB = 1.8 V
12
VCCA = VCCB = 2.5 V
13
VCCA = VCCB = 3.3 V
13
VCCA = VCCB = 5 V
16
VCCA = VCCB = 1.8 V
13
VCCA = VCCB = 2.5 V
13
VCCA = VCCB = 3.3 V
14
VCCA = VCCB = 5 V
16
VCCA = VCCB = 1.8 V
2
VCCA = VCCB = 2.5 V
2
VCCA = VCCB = 3.3 V
2
VCCA = VCCB = 5 V
3
UNIT
pF
pF
See CMOS Power Consumption and Cpd Calculation, SCAA035.
Power dissipation capacitance per transceiver.
1.4
5.6
1.2
5.4
1.0
5.2
VOH Voltage (V)
VOL Voltage (V)
6.11 Typical Characteristics
0.8
0.6
0.4
4.8
4.6
o
-40 C
o
25 C
0.2
5.0
o
-40 C
o
25 C
4.4
o
o
85 C
85 C
4.2
0
0
20
40
60
80
100
0
-20
-40
-60
-80
IOL Current (mA)
IOH Current (mA)
Figure 1. Voltage vs Current
Figure 2. Voltage vs Current
-100
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7 Parameter Measurement Information
2 × VCCO
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
t pd
t PLZ/t PZL
t PHZ/t PZH
Open
2 × VCCO
GND
RL
tw
LOAD CIRCUIT
VCCI
VCCI/2
Input
VCCO
CL
RL
VTP
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
15 pF
15 pF
15 pF
15 pF
2 kW
2 kW
2 kW
2 kW
0.15 V
0.15 V
0.3 V
0.3 V
VCCI/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VCCA
Output
Control
(low-level
enabling)
VCCA/2
VCCA/2
0V
t PLZ
t PZL
VCCI
Input
VCCI/2
VCCI/2
0V
t PLH
Output
t PHL
VOH
VCCO/2
VOL
VCCO/2
VCCO
Output
Waveform 1
S1 at 2 × VCCO
(see Note B)
VCCO/2
VOL + VTP
VOL
t PHZ
t PZH
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCCO/2
VOH − VTP
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 W, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
J. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
12
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8 Detailed Description
8.1 Overview
The SN74LVCH8T245 is an 8-bit, dual supply noninverting voltage level translator. Pins A1 through A4, and the
control pins (DIR and OE) are referenced to VCCA, while pins B1 through B4 are referenced to VCCB. Both the A
port and B port can accept I/O voltages ranging from 1.65 V to 5.5 V. The high on DIR allows data transmission
from Port A to Port B, and a low on DIR allows data transmission from Port B to Port A. See AVC Logic Family
Technology and Applications (SCEA006).
8.2 Functional Block Diagram
2
DIR
22
OE
3
A1
21
B1
To Seven Other Channels
8.3 Feature Description
8.3.1 Fully Configurable Dual-Rail Design
Both VCCA and VCCB can be supplied at any voltage from 1.65 V to 5.5 V, making the device suitable for
translating between any of the voltage nodes: 1.8 V, 2.5 V, 3.3 V and 5 V.
8.3.2 Partial-Power-Down Mode Operation
Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. This can occur in applications where subsections of a system are powered down (partial power down) to
reduce power consumption.
8.3.3 Active Bus Hold Circuitry
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state, which helps with board space
savings and reduced component costs. Use of pullup or pulldown resistors with the bus-hold circuitry is not
recommended.
8.3.4 Supports High-Speed Translation
The device can support high data rate applications, which can be calculated from the maximum propagation
delay. This is also dependant on the output load. For example, for a 3.3-V to 5-V conversion, the maximum
frequency is 200 MHz.
8.3.5 VCC Isolation
The VCC isolation feature ensures that if either VCCA or VCCB are at GND (or < 0.4 V), both ports will be in a highimpedance state (IOZ shown in Electrical Characteristics). This prevents false logic levels from being presented to
either bus.
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8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74LVCH8T245.
Table 1. Function Table (Each 8-Bit Section)
CONTROL INPUTS (1)
(1)
14
OUTPUT CIRCUITS
OPERATION
OE
DIR
A PORT
B PORT
L
L
Enabled
Hi-Z
B data to A bus
L
H
Hi-Z
Enabled
A data to B bus
H
X
Hi-Z
Hi-Z
Isolation
Input circuits of the data I/Os are always active.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVCH8T245 device can be used in level-translation applications for interfacing devices or systems
operating at different interface voltages with one another. The maximum output current can be up to 32 mA when
device is powered by 5 V.
9.2 Typical Application
1.8V
5V
0.1 μF
0.1 μF
VCCA
1 µF
VCCB
DIR
OE
1.8V
Controller
5V
System
SN74LVCH8T245
Data
GND
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
GND
Data
GND
Figure 4. Typical Application Circuit
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Typical Application (continued)
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 2.
Table 2. Design Parameters
PARAMETERS
VALUES
Input voltage
1.65 V to 5.5 V
Output voltage
1.65 V to 5.5 V
9.2.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the SN74LVCH8T245 to determine the input voltage
range. For a valid logic high, the value must exceed the VIH of the input port. For a valid logic low, the
value must be less than the VIL of the input port.
• Output voltage range
– Use the supply voltage of the device that the SN74LVCH8T245 is driving to determine the output voltage
range.
9.2.2.1 Enable Times
Calculate the enable times for the SN74LVCH8T245 using Equation 1, Equation 2, Equation 3, and Equation 4:
tPZH (DIR to A) = tPLZ
tPZL (DIR to A) = tPHZ
tPZH (DIR to B) = tPLZ
tPZL (DIR to B) = tPHZ
(DIR
(DIR
(DIR
(DIR
to
to
to
to
B) +
B) +
A) +
A) +
tPLH (B to
tPHL (B to
tPLH (A to
tPHL (A to
A)
A)
B)
B)
(1)
(2)
(3)
(4)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the device initially is transmitting from A to B, then the DIR
bit is switched; the B port of the device must be disabled before presenting it with an input. After the B port has
been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation
delay.
9.2.3 Application Curve
Voltage (V)
Output (5 V)
Input (1.8 V)
Time (200 ns/div)
Figure 5. Translation Up (1.8 V to 5 V) at 2.5 MHz
16
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10 Power Supply Recommendations
The output-enable (OE) input circuit is designed so that it is supplied by VCCA and when the OE input is high, all
outputs are placed in the high-impedance state. To ensure the high-impedance state of the outputs during power
up or power down, the OE input pin must be tied to VCCA through a pullup resistor and must not be enabled until
VCCA and VCCB are fully ramped and stable. The minimum value of the pullup resistor to VCCA is determined by
the current-sinking capability of the driver.
VCCA or VCCB can be powered up first. If the SN74LVCH8T245 is powered up in a permanently enabled state
(for example OE is always kept low), pullup resistors are recommended at the input. This ensures proper, glitchfree, power-up. See Designing with SN4LVCXT245 and SN74LVCHXT245 Family of Direction Controlled Voltage
Translators/Level-Shifters (SLVA746). In addition, the OE pin may be shorted to GND if the application does not
require use of the high-impedance state at any time.
11 Layout
11.1 Layout Guidelines
To
•
•
•
ensure reliability of the device, TI recommends the following common printed-circuit board layout guidelines.
Bypass capacitors should be used on power supplies.
Short trace lengths should be used to avoid excessive loading.
Placing pads on the signal paths for loading capacitors or pullup resistors helps adjust rise and fall times of
signals depending on the system requirements.
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11.2 Layout Example
LEGEND
VIA to Power Plane
Polygonal Copper Pour
VIA to GND Plane (Inner Layer)
VCCB
VCCA
Bypass Capacitor
Bypass Capacitor
VCCA
1
VCCA
VCCB
16
2
DIR
VCCB
15
From
Controller
3
A1
OE
14
From
Controller
4
A2
B1
13
To
System
From
Controller
5
A3
B2
12
To
System
From
Controller
6
A4
B3
11
To
System
From
Controller
7
A5
B4
10
To
System
From
Controller
8
A6
B5
12
To
System
From
Controller
9
A7
B6
11
To
System
From
Controller
10
A8
B7
10
To
System
11
GND
B8
10
To
System
12
GND
GND
13
Keep OE high until VCCA and
VCCB are powered up
SN74LVCH8T245
Figure 6. SN74LVCH8T245 Layout
18
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Designing with SN74LVCXT245 and SN74LVCHXT245
Translators/Level-Shifters, SLVA746
• Bus-Hold Circuit, SCLA015
• AVC Logic Family Technology and Applications, SCEA006
• CMOS Power Consumption and Cpd Calculation, SCAA035
Family
of
Direction
Controlled
Voltage
12.2 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LVCH8T245DBR
ACTIVE
SSOP
DB
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
NJ245
SN74LVCH8T245DGVR
ACTIVE
TVSOP
DGV
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
NJ245
SN74LVCH8T245PW
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
NJ245
SN74LVCH8T245PWE4
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
NJ245
SN74LVCH8T245PWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
NJ245
SN74LVCH8T245RHLR
ACTIVE
VQFN
RHL
24
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
NJ245
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jan-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8.2
8.8
2.5
12.0
16.0
Q1
SN74LVCH8T245DBR
SSOP
DB
24
2000
330.0
16.4
SN74LVCH8T245DGVR
TVSOP
DGV
24
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LVCH8T245PWR
TSSOP
PW
24
2000
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
SN74LVCH8T245RHLR
VQFN
RHL
24
1000
180.0
12.4
3.8
5.8
1.2
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jan-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVCH8T245DBR
SSOP
DB
24
2000
367.0
367.0
38.0
SN74LVCH8T245DGVR
TVSOP
DGV
24
2000
367.0
367.0
35.0
SN74LVCH8T245PWR
TSSOP
PW
24
2000
367.0
367.0
38.0
SN74LVCH8T245RHLR
VQFN
RHL
24
1000
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0024A
TSSOP - 1.2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1
2X
7.15
7.9
7.7
NOTE 3
12
13
B
0.30
0.19
0.1
C A B
24X
4.5
4.3
NOTE 4
1.2 MAX
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220208/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
24X (1.5)
(R0.05) TYP
1
24
24X (0.45)
22X (0.65)
SYMM
13
12
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
24X (1.5)
SYMM
(R0.05) TYP
1
24
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OUTLINE
VQFN - 1 mm max height
RHL0024A
PLASTIC QUAD FLATPACK- NO LEAD
A
3.6
3.4
B
PIN 1 INDEX AREA
5.6
5.4
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
2.05±0.1
2X 1.5
24X 0.5
0.3
SYMM
13
12
18X 0.5
11
(0.1) TYP
14
21
2X
4.5
SYMM
4.05±0.1
23
2
PIN 1 ID
(OPTIONAL)
1
24
4X (0.2)
2X (0.55)
24X 0.30
0.18
0.1
0.05
C A B
C
4225250/A 09/2019
NOTES:
1.
2.
3.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RHL0024A
PLASTIC QUAD FLATPACK- NO LEAD
(3.3)
(2.05)
2X (1.5)
SYMM
1
24
24X (0.6)
24X (0.24)
2X (0.4)
23
2
18X (0.5)
2X (1.105)
6X (0.67)
25
SYMM
(4.05)
4.6
4.4
(5.3)
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
(Ø 0.2) VIA
TYP
(R0.05) TYP
11
14
13
12
4X
(0.775)
4X (0.2)
2X (0.55)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED METAL
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4225250/A 09/2019
NOTES: (continued)
4.
5.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RHL0024A
PLASTIC QUAD FLATPACK- NO LEAD
(3.3)
(2.05)
2X (1.5)
SYMM
1
SOLDER MASK EDGE
TYP
24
24X (0.6)
24X (0.24)
23
2
18X (0.5)
25
SYMM
4.6
4.4
(5.3)
4X
(1.34)
METAL TYP
(R0.05) TYP
11
14
13
12
2X (0.84)
6X (0.56)
4X (0.2)
2X (0.55)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
80% PRINTED COVERAGE BY AREA
SCALE: 18X
4225250/A 09/2019
NOTES: (continued)
6.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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