Texas Instruments | SN74HC595B 8-Bit Shift Registers With 3-State Output Registers | Datasheet | Texas Instruments SN74HC595B 8-Bit Shift Registers With 3-State Output Registers Datasheet

Texas Instruments SN74HC595B 8-Bit Shift Registers With 3-State Output Registers Datasheet
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SN74HC595B
SCLS751 – MARCH 2016
SN74HC595B 8-Bit Shift Registers With 3-State Output Registers
1 Features
2 Applications
•
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1
•
•
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8-Bit Serial-In, Parallel-Out Shift Registers
Available in Ultra Small Logic QFN package(0.5
mm max height)
Over-Voltage Tolerant on Inputs Independent of
Vcc
Wide Operating Voltage Range of 2 V to 6 V
High-Current 3-State Outputs Can Drive Up to 15
LSTTL Loads
Low Power Consumption: 80-μA (Maximum) ICC
tpd = 13 ns (Typical)
±6-mA Output Drive at 5 V
Low Input Current: 1 μA (Maximum)
Shift Register Has Direct Clear
-55oC to 125oC Operating Temperature
Network Switches
Factory Automation
Mobile Wearables
Industrial Building Automation
Power Infrastructure
LED Displays
Servers
3 Description
The SN74HC595B devices contain an 8-bit, serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. The storage register has parallel 3state outputs. Separate clocks are provided for both
the shift register and storage register. The shift
register has a direct overriding clear (SRCLR) input,
serial (SER) input, and serial outputs for cascading.
When the output-enable (OE) input is high, the all
outputs are in the high-impedance state except QH'.
Table 1. Device Information
PART NUMBER
PACKAGE (PINS)
SN74HC595BRWN
X1QFN (16)
BODY SIZE (NOM)
2.50 mm x 2.50 mm
(1) For available package, see the orderable addendum at the
end of the data sheet.
Logic Diagram (Positive Logic)
13
OE
12
RCLK
10
SRCLR
11
SRCLK
14
1D
SER
>
C1
R
3R
>
15
C3
QA
3S
2S
2R
>
C2
R
3R
>
1
C3
QB
3S
2S
2R
>
C2
R
3R
>
2
C3
QC
3S
2S
2R
>
C2
R
3R
>
3
C3
QD
3S
2S
2R
>
C2
R
3R
>
4
C3
QE
3S
2S
2R
>
C2
R
3R
>
5
C3
QF
3S
2S
2R
>
C2
R
3R
>
6
C3
QG
3S
2S
2R
>
C2
R
3R
>
7
C3
QH
3S
9
Q+¶
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74HC595B
SCLS751 – MARCH 2016
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
3
4
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
4
4
4
5
5
6
7
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
2
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 13
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 14
9 Power Supply Recommendations...................... 16
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 16
11 Device and Documentation Support ................. 17
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
12 Mechanical, Packaging, and Orderable
Information ........................................................... 17
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4 Pin Configuration and Functions
QG
QH
5
6
7
GND
QF
RWN Package
16-Pin XQFN
Bottom View
8
QD
3
10
SRCLR
QC
2
11
SRCLK
QB
1
12
RCLK
16
15
14
13
OE
QH[
SER
9
QA
4
VCC
QE
Table 2. Pin Functions
PIN
NAME
RWN
I/O
—
DESCRIPTION
GND
8
Ground Pin
OE
13
I
Output Enable; does not control QH'
QA
15
O
QA Output
QB
1
O
QB Output
QC
2
O
QC Output
QD
3
O
QD Output
QE
4
O
QE Output
QF
5
O
QF Output
QG
6
O
QG Output
QH
7
O
QH Output
QH'
9
O
QH' Output
RCLK
12
I
RCLK Input
SER
14
I
SER Input
SRCLK
11
I
SRCLK Input
SRCLR
10
I
SRCLR Input
VCC
16
—
Power Pin
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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
VI
Input voltage
IIK
Input clamp current (1)
IOK
Output clamp current
IO
Continuous output current
MIN
MAX
UNIT
–0.5
7
V
-0.5
(2)
7
V
VI < 0
-20
mA
VO < 0 or VO > VCC
±20
mA
VO = 0 to VCC
±35
mA
Continuous current through VCC or GND
±70
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
5.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN74HC595B
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
VCC = 4.5 V
VCC = 6 V
MIN
NOM
MAX
2
5
6
Low-level input voltage
V
1.5
3.15
V
4.2
VCC = 2 V
VIL
UNIT
0.5
VCC = 4.5 V
1.35
VCC = 6 V
V
1.8
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
Δt/Δv
Input transition rise or fall time (2)
VCC = 2 V
TA
(1)
(2)
4
1000
VCC = 4.5 V
500
VCC = 6 V
400
Operating free-air temperature
–55
125
ns
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
If this device is used in the threshold region (from VILmax = 0.5 V to VIH min = 1.5 V), there is a potential to go into the wrong state from
induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device;
however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
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5.4 Thermal Information
SN74HC595B
THERMAL METRIC (1)
RWN (X1QFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
112
RθJCtop
Junction-to-case (top) thermal resistance
47.9
RθJB
Junction-to-board thermal resistance
72.4
ψJT
Junction-to-top characterization parameter
0.6
ψJB
Junction-to-board characterization parameter
72.4
RθJCbot
Junction-to-case (bottom) thermal resistance
32.2
(1)
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
5.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –20 μA
VOH
VI = VIH or VIL
QH′, IOH = –4 mA
QA – QH, IOH = –6 mA
QH′, IOH = −5.2 mA
QA – QH, IOH = –7.8 mA
IOL = 20 μA
VOL
VI = VIH or VIL
QH′, IOL = 4 mA
QA – QH, IOL = 6 mA
QH′, IOL = 5.2 mA
QA – QH, IOL = 7.8 mA
VCC
TA = 25°C
MIN
TYP
TA = -55°C to 125°C
MAX
MIN
MAX
TA = -40°C to 85°C
MIN
2V
1.9
1.998
1.9
1.9
4.5 V
4.4
4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
3.98
4.3
3.7
3.84
3.98
4.3
3.7
3.84
5.48
5.8
5.2
5.34
5.48
5.8
5.2
4.5 V
6V
MAX
V
5.34
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
0.17
0.26
0.4
0.33
0.17
0.26
0.4
0.33
0.15
0.26
0.4
0.33
4.5 V
6V
UNIT
V
0.15
0.26
0.4
0.33
II
VI = VCC or 0
6V
±0.1
±100
±1000
±1000
nA
IOZ
VO = VCC or 0, QA – QH
6V
±0.01
±0.5
±10
±5
µA
ICC
VI = VCC or 0, IO = 0
6V
8
160
80
µA
10
10
10
pF
Ci
2 V to
6V
3
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5.6 Timing Requirements
over operating free-air temperature range (unless otherwise noted)
VCC
fclock
Clock frequency
SRCLK or RCLK high or low
tw
Pulse
duration
SRCLR low
SER before SRCLK↑
SRCLK↑ before RCLK↑
tsu
(1)
Set-up time
SRCLR low before RCLK↑
SRCLR high (inactive)
before SRCLK↑
th
(1)
6
Hold time, SER after SRCLK↑
TA = 25°C
MIN
TA = -55°C to 125°C
MAX
MIN
MAX
TA = -40°C to 85°C
MIN
MAX
2V
6
4.2
5
4.5 V
31
21
25
6V
36
25
29
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
2V
75
113
94
4.5 V
15
23
19
6V
13
19
16
2V
50
75
65
4.5 V
10
15
13
6V
9
13
11
2V
50
75
60
4.5 V
10
15
12
6V
9
13
11
2V
0
0
0
4.5 V
0
0
0
6V
0
0
0
UNIT
MHz
ns
ns
ns
This set-up time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case
the shift register is one clock pulse ahead of the storage register.
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5.7 Switching Characteristics
Over recommended operating free-air temperature range.
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
SRCLK
QH′
tPHL
ten
tdis
SRCLR
OE
OE
QA – QH
QH′
QA – QH
QA – QH
QA – QH
2V
6
26
4.2
5
50 pF
4.5 V
31
38
21
25
6V
36
42
50 pF
50 pF
50 pF
50 pF
50 pF
50 pF
tt
QH′
tpd
ten
tt
RCLK
OE
QA – QH
QA – QH
QA – QH
TA = -40°C to
85°C
VCC
tpd
RCLK
TA = -55°C to
125°C
TA = 25°C
LOAD
CAPACITANCE
50 pF
150 pf
150 pf
150 pf
MIN
TYP MAX
MIN
MAX
25
MIN
MHz
29
2V
50
160
240
200
4.5 V
17
32
48
40
6V
14
27
41
34
2V
50
150
225
187
4.5 V
17
30
45
37
6V
14
26
38
32
2V
51
175
261
219
4.5 V
18
35
52
44
6V
15
30
44
37
2V
40
150
255
187
4.5 V
15
30
45
37
6V
13
26
38
32
2V
42
200
300
250
4.5 V
23
40
60
50
6V
20
34
51
43
2V
28
60
90
75
4.5 V
8
12
18
15
6V
6
10
15
13
2V
28
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
2V
60
200
300
250
4.5 V
22
40
60
50
6V
19
34
51
43
2V
70
200
298
250
4.5 V
23
40
60
50
6V
19
34
51
43
2V
45
210
315
265
4.5 V
17
42
63
53
6V
13
36
53
45
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UNIT
MAX
ns
ns
ns
ns
ns
ns
ns
ns
7
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SRCLK
SER
RCLK
SRCLR
OE
QA
QB
QC
QD
QE
QF
QG
QH
QH’
NOTE:
implies that the output is in 3-State mode.
Figure 1. Timing Diagram
5.8 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
8
TEST CONDITIONS
TYP
UNIT
No load
400
pF
Power dissipation capacitance
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5.9 Typical Characteristics
40
OUTPUTS = µ+,¶
OE = µ/2:¶
35
30
25
20
ICC(nA) 15
10
5
0
-5
0
1
2
3
VCC(V)
4
5
6
Figure 2. SN74HC595B ICC vs. VCC
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6 Parameter Measurement Information
VCC
S1
Test
Point
From Output
Under Test
PARAMETER
RL
CL
(see Note A)
tPZH
ten
1 kΩ
tPZL
tPHZ
tdis
S2
RL
tPLZ
1 kΩ
Reference
Input
VCC
Data
Input
VCC
50%
10%
50%
VCC
0V
In-Phase
Output
50%
10%
tPHL
90%
tr
Out-ofPhase
Output
90%
Closed
Closed
Open
Open
Open
VCC
th
90%
90%
VCC
50%
10% 0 V
tf
VCC
50%
50%
0V
Output
Waveform 1
(See Note B)
VOH
Output
Waveform 2
(See Note B)
tPLZ
90%
tr
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
≈VCC
≈VCC
50%
10%
tPZH
50%
10%
tf
Output
Control
(Low-Level
Enabling)
VOH
50%
10% V
OL
tf
tPLH
50%
10%
Open
tPZL
90%
tPHL
Open
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
50%
tPLH
Closed
tr
VOLTAGE WAVEFORMS
PULSE DURATIONS
50%
Closed
0V
0V
Input
Open
tsu
0V
50%
50 pF
or
150 pF
50%
50%
tw
Low-Level
Pulse
S2
50 pF
or
150 pF
LOAD CIRCUIT
50%
S1
50 pF
tpd or tt
High-Level
Pulse
CL
VOL
tPHZ
50%
90%
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, fmax is measured when the input duty cycle is 50%.
E. The outputs are measured one at a time, with one input transition per measurement.
F. t PLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
10
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7 Detailed Description
7.1 Overview
The SN74HC595B is part of the HC family of logic devices intended for CMOS applications. The SN74HC595B
device is an 8-bit shift register that feeds an 8-bit D-type storage register.
Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both
clocks are connected together, the shift register is always one clock pulse ahead of the storage register. The QH'
may be used for daisy chaining the device and will not go into high impedance when OE is asserted.
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7.2 Functional Block Diagram
13
OE
12
RCLK
10
SRCLR
11
SRCLK
14
1D
SER
>
C1
3R
>
R
15
C3
QA
3S
2S
2R
>
C2
3R
>
R
1
C3
QB
3S
2S
2R
>
C2
3R
>
R
2
C3
QC
3S
2S
2R
>
C2
3R
>
R
3
C3
QD
3S
2S
2R
>
C2
3R
>
R
4
C3
QE
3S
2S
2R
>
C2
3R
>
R
5
C3
QF
3S
2S
2R
>
C2
3R
>
R
6
C3
QG
3S
2S
2R
>
C2
3R
>
R
7
C3
QH
3S
9
Q+¶
Figure 4. Logic Diagram (Positive Logic)
12
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7.3 Feature Description
The SN74HC595B device is an 8-bit Serial-In, Parallel-Out shift register. It has a wide operating voltage of 2 V to
6 V, and the high-current 3-state outputs can drive up to 15 LSTTL Loads. The device has a low power
consumption of 80-μA (Maximum) ICC. Additionally, this device has a low input current of 1 μA (Maximum) and a
±6-mA output drive at 5 V. The device is available currently in the smallest logic QFN package at 0.5 mm max
height with 0.4 mm pitch. The inputs are over voltage tolerant independent of Vcc.
7.4 Device Functional Modes
Table 3 lists the functional modes of the SN74HC595B devices.
Table 3. Function Table
INPUTS
FUNCTION
SER
SRCLK
SRCLR
RCLK
OE
–
–
–
–
H
Outputs QA – QH are disabled. QH' is active .
–
–
–
–
L
Outputs QA – QH are enabled.
–
–
L
–
–
Shift register is cleared.
L
↑
H
–
–
First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
H
↑
H
–
–
First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
–
–
–
↑
–
Shift-register data is stored in the storage register.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The SN74HC595B is a low-drive CMOS device that is used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. QH' pin of the first register should be connected to the serial (SER) pin of the second register for
daisy chaining.
8.2 Typical Application
SRCLR
SRCLK
5
RCLK
Controller
OE
SER
10
15
11
1
12
2
13
3
14
4
5
6
7
+5V
9
VCC
16
8
QA
560
QB
560
560
QC
560
QD
560
QE
560
QF
560
QG
560
QH
Q+¶
GND
0.1 F
Figure 5. Typical Application Schematic
8.2.1 Design Requirements
This device uses CMOS technology and has a balanced output drive. Take care to avoid bus contention because
it can drive currents in excess of the maximum limits. The high drive will also create fast edges into light loads,
so routing and load conditions should be considered to prevent ringing.
8.2.2 Detailed Design Procedure
• Recommended input conditions
– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are over-voltage tolerant allowing them to go as high as 5.5 V at any valid VCC
14
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SCLS751 – MARCH 2016
Typical Application (continued)
•
Recommended output conditions
– Load currents should not exceed 35 mA per output as per the Absolute Maximum Ratings table.
– Outputs should not be pulled below Ground or above VCC
8.2.3 Application Curves
60
50
40
30
tpd(ns)
20
10
0
0
2
4
VCC(V)
6
8
Figure 6. SN75HC595B tpd vs. VCC
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SN74HC595B
SCLS751 – MARCH 2016
www.ti.com
9 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table. The total current through Ground or Vcc should not exceed 70 mA as
per Absolute Maximum Ratings table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μf is recommended; if there are multiple VCC pins, then 0.01 μf or 0.022 μf is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and a
1 μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
10 Layout
10.1 Layout Guidelines
When using multiple-bit logic devices, inputs should never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input and the gate are used, or only 3 of the 4 buffer gates are used. Such input pins should not
be left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Figure 7 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally, they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs, unless the
part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the part when
asserted. This will not disable the input section of the I/Os, so they cannot float when disabled.
10.2 Layout Example
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 7. Layout Diagram
16
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SCLS751 – MARCH 2016
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
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17
PACKAGE OPTION ADDENDUM
www.ti.com
11-Mar-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
SN74HC595BRWNR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
X1QFN
RWN
16
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-55 to 125
13YI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Mar-2016
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Jun-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74HC595BRWNR
Package Package Pins
Type Drawing
X1QFN
RWN
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
178.0
13.5
Pack Materials-Page 1
2.8
B0
(mm)
K0
(mm)
P1
(mm)
2.8
0.75
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Jun-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74HC595BRWNR
X1QFN
RWN
16
2000
189.0
185.0
36.0
Pack Materials-Page 2
PACKAGE OUTLINE
RWN0016A
X1QFN - 0.5 mm max height
SCALE 5.000
PLASTIC QUAD FLATPACK - NO LEAD
2.55
2.45
A
B
PIN 1 INDEX AREA
2.55
2.45
C
0.5 MAX
SEATING PLANE
0.05
0.00
0.08
2X 1.2
8X
(45 X 0.12)
5
8
4
9
2X
1.2
12X 0.4
1.2 0.05
1
12
16X
PIN 1 ID
(OPTIONAL)
(0.15) TYP
EXPOSED
THERMAL PAD
16
13
0.45
16X
0.35
0.25
0.15
0.1
0.05
C A
B
4221911/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RWN0016A
X1QFN - 0.5 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.2)
SYMM
16
13
16X (0.6)
16X (0.2)
1
12
(2.3)
SYMM
(1.2)
12X (0.4)
4
9
( 0.2) VIA
8
5
(R0.05)
TYP
(2.3)
LAND PATTERN EXAMPLE
SCALE:20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221911/A 05/2015
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RWN0016A
X1QFN - 0.5 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(R0.05) TYP
( 1.13)
13
16
16X (0.6)
16X (0.2)
1
12
SYMM
(2.3)
12X (0.4)
9
4
METAL
TYP
5
SYMM
8
(2.3)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
88% PRINTED SOLDER COVERAGE BY AREA
SCALE:30X
4221911/A 05/2015
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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