Texas Instruments | SN74AHC1G00 Single 2-Input Positive-NAND Gate (Rev. O) | Datasheet | Texas Instruments SN74AHC1G00 Single 2-Input Positive-NAND Gate (Rev. O) Datasheet

Texas Instruments SN74AHC1G00 Single 2-Input Positive-NAND Gate (Rev. O) Datasheet
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SN74AHC1G00
SCLS313O – MARCH 1996 – REVISED APRIL 2016
SN74AHC1G00 Single 2-Input Positive-NAND Gate
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
1
•
•
Operating Range: 2 V to 5.5 V
Maximum tpd of 6.5 ns at 5 V
Low Power Consumption: Maximum ICC of 10 μA
±8-mA Output Drive at 5 V
Schmitt Trigger Action at All Inputs Makes the
Circuit Tolerant for Slower Input Rise and Fall
Time
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
IP Phones
Notebook PCs
Printers
Access Control and Security
Solar Inverters
Personal Electronics
3 Description
The SN74AHC1G00 performs the Boolean function
Y = A • B or Y = A + B in positive logic.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74AHC1G00DBV SOT-23 (5)
2.90 mm × 1.60 mm
SN74AHC1G00DCK SC70 (5)
2.00 mm × 1.25 mm
SN74AHC1G00DRL SOT (5)
1.60 mm × 1.20 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
A
B
1
2
4
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AHC1G00
SCLS313O – MARCH 1996 – REVISED APRIL 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
5
5
6
6
7
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Switching Characteristics: VCC = 3.3 V ± 0.3 V ........
Switching Characteristics: VCC = 5 V ± 0.5 V ...........
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement information .................. 8
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes.......................................... 9
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 12
11.1 Layout Guidelines ................................................. 12
11.2 Layout Example .................................................... 12
12 Device and Documentation Support ................. 13
12.1
12.2
12.3
12.4
12.5
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13
13 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision N (May 2013) to Revision O
•
Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................... 1
Changes from Original (March 1996) to Revision N
•
2
Page
Page
Changed document format from Quicksilver to DocZone. ..................................................................................................... 1
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5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
A
1
B
2
GND
DCK Package
5-Pin SC70
Top View
5
3
V
4
A
1
B
2
GND
3
5
V
4
Y
CC
CC
Y
DRL Package
5-Pin SOT
Top View
A
1
B
2
GND
3
5
V
4
Y
CC
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
A
I
A input
2
B
I
B input
3
GND
—
Ground
4
Y
O
Output
5
VCC
—
Power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VCC
(1)
MIN
MAX
UNIT
Supply voltage
–0.5
7
V
(2)
–0.5
7
V
–0.5
VCC + 0.5
V
VI
Input voltage
VO
Output voltage (2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
150
°C
150
°C
Continuous current through VCC or GND
TJ
Maximum junction temperature
Tstg
Storage temperature
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
See
(1)
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
VCC = 3 V
VCC = 5.5 V
MIN
MAX
2
5.5
Low-level input voltage
V
1.5
2.1
V
3.85
VCC = 2 V
VIL
UNIT
0.5
VCC = 3 V
0.9
VCC = 5.5 V
V
1.65
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
–50
µA
IOH
High-level output current
VCC = 2 V
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
4
VCC = 3.3 V ± 0.3 V
–4
VCC = 5 V ± 0.5 V
–8
VCC = 2 V
50
VCC = 3.3 V ± 0.3 V
4
VCC = 5 V ± 0.5 V
8
VCC = 3.3 V ± 0.3 V
100
VCC = 5 V ± 0.5 V
20
–40
125
mA
µA
mA
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
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6.4 Thermal Information
SN74AHC1G00
THERMAL METRIC (1)
DBV (SOT-23)
DCK (SC70)
DRL (SOT)
5 PINS
5 PINS
5 PINS
UNIT
240
276.53
256
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
174.5
118.5
130
°C/W
RθJB
Junction-to-board thermal resistance
73.7
62.8
152
°C/W
ψJT
Junction-to-top characterization parameter
54.9
6.7
9.9
°C/W
ψJB
Junction-to-board characterization parameter
72.9
62.1
152
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER (1)
TEST CONDITIONS
VCC
TA = 25°C
TA = –40°C to +85°C
2V
TA = –40°C to +125°C
TA = –40°C to +85°C
VOL
0.1
2V
0.1
TA = 25°C
0.1
TA = –40°C to +85°C
3V
0.1
TA = 25°C
0.1
4.5 V
TA = –40°C to +85°C
3V
0.36
4.5 V
TA = –40°C to +125°C
±0.1
0 V to 5.5 V
TA = –40°C to +125°C
(1)
0.44
0.44
TA = 25°C
TA = –40°C to +85°C
0.44
0.44
TA = 25°C
VI = 5.5 V or GND
V
0.36
TA = –40°C to +125°C
TA = –40°C to +85°C
0.1
0.1
TA = 25°C
II
0.1
TA = –40°C to +125°C
TA = –40°C to +125°C
IOL = 8 mA
0.1
TA = –40°C to +125°C
TA = –40°C to +85°C
IOL = 4 mA
3.8
3.8
TA = 25°C
IOL = 50 µA
2.48
3.94
4.5 V
TA = –40°C to +125°C
TA = –40°C to +85°C
V
2.48
TA = 25°C
TA = –40°C to +85°C
4.5
4.4
2.58
3V
TA = –40°C to +125°C
IOH = –8 mA
3
2.9
4.4
TA = 25°C
TA = –40°C to +85°C
UNIT
1.9
4.4
4.5 V
TA = –40°C to +125°C
IOH = –4 mA
MAX
2.9
TA = 25°C
TA = –40°C to +85°C
2
2.9
3V
TA = –40°C to +125°C
VOH
TYP
1.9
1.9
TA = 25°C
IOH = –50 µA
MIN
±1
µA
±1
Recommended TA = –40°C to +125°C
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER (1)
TEST CONDITIONS
VCC
MIN
TYP
MAX
TA = 25°C
ICC
VI = VCC or GND,
IO = 0
1
TA = –40°C to +85°C
5.5 V
10
TA = –40°C to +125°C
VI = VCC or GND
2
TA = –40°C to +85°C
µA
10
TA = 25°C
Ci
UNIT
10
5V
10
TA = –40°C to +125°C
pF
10
6.6 Switching Characteristics: VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
OUTPUT
CAPACITANCE
TA (1)
MIN
25°C
tPLH
A or B
Y
CL = 15 pF
tPHL
5.5
–40°C to +85°C
1
9.5
1
10.5
25°C
5.5
–40°C to +85°C
1
9.5
1
10.5
A or B
Y
CL = 50 pF
tPHL
(1)
8
1
–40°C to +125°C
1
25°C
ns
7.9
–40°C to +125°C
–40°C to +85°C
UNIT
7.9
–40°C to +125°C
25°C
tPLH
TYP MAX
11.4
13
14
8
ns
11.4
–40°C to +85°C
1
13
–40°C to +125°C
1
14
Recommended TA = –40°C to +125°C
6.7 Switching Characteristics: VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
OUTPUT
CAPACITANCE
TA (1)
MIN
25°C
tPLH
A or B
Y
CL = 15 pF
tPHL
3.7
–40°C to +85°C
1
–40°C to +125°C
1
25°C
–40°C to +85°C
1
–40°C to +125°C
1
A or B
Y
CL = 50 pF
tPHL
(1)
6
5.5
6.5
7
3.7
25°C
tPLH
TYP MAX UNIT
5.5
6.5
7
5.2
7.5
–40°C to +85°C
1
6.5
–40°C to +125°C
1
9
25°C
ns
5.2
7.5
–40°C to +85°C
1
6.5
–40°C to +125°C
1
9
ns
Recommended TA = –40°C to +125°C
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6.8 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
MIN
TYP
No load, f = 1 MHz
MAX
UNIT
9.5
pF
6.9 Typical Characteristics
14
tPLH/HL(max) (ns)
12
Vcc=3.3 +/-0.3 V
A/B to Y
CL = 50 pF
10
Vcc=5 +/-0.5 V
A/B to Y
CL = 50 pF
8
6
4
0
25
50
85
125
Temperature (°C)
CL = 50 pF
Figure 1. Propagation Delay vs Temperature
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7 Parameter Measurement information
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
Test
Point
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
Open
VCC
GND
VCC
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
Input
VCC
50% VCC
50% VCC
0V
th
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
0V
tPHL
tPLH
In-Phase
Output
50% VCC
Output
Waveform 1
S1 at VCC
(see Note B)
50% VCC
50% VCC
VOH
50% VCC
VOL
50% VCC
0V
tPLZ
tPZL
≈VCC
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
VCC
Output
Control
50% VCC
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output
control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output
control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf
≤ 3 ns.
D.
The outputs are measured one at a time with one input transition per measurement.
E.
All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
8
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8 Detailed Description
8.1 Overview
The SN74AHC1G00 device performs the NAND Boolean function Y = A × B or Y = A + B in positive logic. The
device has a wide operating range of VCC from 2 V to 5 V.
8.2 Functional Block Diagram
A
B
1
4
2
Y
Figure 3. Logic Diagram (Positive Logic)
8.3 Feature Description
The SN74AHC1G00 device has wide operating voltage range for logic system from 2 V to 5 V. The low
propagation delay allows fast switching and higher speeds of operation. In addition, the low power consumption
of 10-uA (maximum) makes this device a good choice for portable and battery power-sensitive applications. The
Schmitt trigger action on all inputs have noise rejection capabilities.
8.4 Device Functional Modes
Table 1 lists the functions of the SN74AHC1G00 device.
Table 1. Function Table
INPUTS
OUTPUT
A
B
H
H
Y
L
L
X
H
X
L
H
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74AHC1G00 device is a low-drive CMOS device with 8-mA output drive at 5 V. It can be used for a
multitude of bus interface type applications where output ringing is a concern. The low drive and slow edge rates
minimizes overshoot and undershoot on the outputs. The NAND gates are used to build simple SR flip flop. They
could be used in removing noise from a switch debounce circuit
9.2 Typical Application
S
Q
Q
R
Figure 4. Typical Application
9.2.1 Design Requirements
This SN74AHC1G00 device uses CMOS technology and has balanced output drive. Take care to avoid bus
contention becuase it can drive currents that would exceed maximum limits. The high drive also creates fast
edges into light loads. Routing and load conditions must be considered to prevent ringing.
9.2.2 Detailed Design Procedure
• Recommended input conditions:
– Specified high and low levels. See VIH and VIL in Recommended Operating Conditions.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
• Recommended output conditions:
– Load currents must not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC.
10
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Typical Application (continued)
9.2.3 Application Curve
12
tPLH/HL(max) (ns)
10
Vcc=3.3 +/-0.3 V
A/B to Y
CL = 15 pF
8
Vcc=5 +/-0.5 V
A/B to Y
CL = 15 pF
6
4
2
0
25
50
85
125
Temperature (°C)
CL = 15 pF
Figure 5. Propagation Delay vs Temperature
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, TI recommends a 0.1-μF capacitor; if there are multiple VCC terminals, then TI recommends a 0.01-μF or
0.022-μF capacitor for each power terminal. Multiple bypass capacitors can be paralleled to reject different
frequencies of noise. Frequencies of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor must
be installed as close as possible to the power terminal for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs must not ever float.
In many cases, functions or parts of functions of digital logic devices are unused. For example, when only two
inputs of a triple-input AND gate are used or only three of the four buffer gates are used. Such input pins must
not be left unconnected because the undefined voltages at the outside connections result in undefined
operational states. The following are the rules must be observed under all circumstances.
All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating.
The logic level that should be applied to any particular unused input depends on the function of the device.
Generally they will be tied to GND or VCC whichever make more sense or is more convenient. Floating outputs is
generally acceptable, unless the part is a transceiver. If the transceiver has an output enable pin, it disables the
outputs section of the part when asserted. This does not disable the input section of the input and output, so they
also cannot float when disabled.
11.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
Figure 6. Layout Recommendation
12
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Introduction to Logic, SLVA700
• Implications of Slow or Floating CMOS Inputs, SCBA004
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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4-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74AHC1G00DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(A003, A00G, A00J,
A00L, A00S)
SN74AHC1G00DBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
A00G
SN74AHC1G00DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(A003, A00G, A00L,
A00S, A04J)
SN74AHC1G00DCK3
ACTIVE
SC70
DCK
5
3000
Pb-Free
(RoHS)
CU SNBI
Level-1-260C-UNLIM
-40 to 125
AAY
SN74AHC1G00DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(AA3, AAG, AAJ, AA
L, AAS)
SN74AHC1G00DCKRE4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AA3
SN74AHC1G00DCKRG4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AA3
SN74AHC1G00DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(AA3, AAG, AAJ, AA
L, AAS)
SN74AHC1G00DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AA3
SN74AHC1G00DRLR
ACTIVE
SOT-5X3
DRL
5
4000
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
(AAB, AAS)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
4-Apr-2019
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74AHC1G00 :
• Automotive: SN74AHC1G00-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
SN74AHC1G00DBVR
SOT-23
DBV
5
3000
178.0
9.0
SN74AHC1G00DBVR
SOT-23
DBV
5
3000
178.0
SN74AHC1G00DBVR
SOT-23
DBV
5
3000
180.0
SN74AHC1G00DBVR
SOT-23
DBV
5
3000
SN74AHC1G00DBVRG4 SOT-23
DBV
5
W
Pin1
(mm) Quadrant
3.3
3.2
1.4
4.0
8.0
Q3
9.2
3.3
3.23
1.55
4.0
8.0
Q3
8.4
3.23
3.17
1.37
4.0
8.0
Q3
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
SN74AHC1G00DBVT
SOT-23
DBV
5
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
SN74AHC1G00DBVT
SOT-23
DBV
5
250
178.0
9.2
3.3
3.23
1.55
4.0
8.0
Q3
SN74AHC1G00DBVT
SOT-23
DBV
5
250
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
SN74AHC1G00DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
SN74AHC1G00DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
SN74AHC1G00DCKR
SC70
DCK
5
3000
180.0
8.4
2.47
2.3
1.25
4.0
8.0
Q3
SN74AHC1G00DCKR
SC70
DCK
5
3000
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74AHC1G00DCKRG4
SC70
DCK
5
3000
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74AHC1G00DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
SN74AHC1G00DCKT
SC70
DCK
5
250
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74AHC1G00DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
SN74AHC1G00DCKTG4
SC70
DCK
5
250
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74AHC1G00DRLR
SOT-5X3
DRL
5
4000
180.0
8.4
1.98
1.78
0.69
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AHC1G00DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
SN74AHC1G00DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
SN74AHC1G00DBVR
SOT-23
DBV
5
3000
202.0
201.0
28.0
SN74AHC1G00DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
SN74AHC1G00DBVRG4
SOT-23
DBV
5
3000
180.0
180.0
18.0
SN74AHC1G00DBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
SN74AHC1G00DBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
SN74AHC1G00DBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
SN74AHC1G00DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
SN74AHC1G00DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
SN74AHC1G00DCKR
SC70
DCK
5
3000
202.0
201.0
28.0
SN74AHC1G00DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
SN74AHC1G00DCKRG4
SC70
DCK
5
3000
180.0
180.0
18.0
SN74AHC1G00DCKT
SC70
DCK
5
250
180.0
180.0
18.0
SN74AHC1G00DCKT
SC70
DCK
5
250
180.0
180.0
18.0
SN74AHC1G00DCKT
SC70
DCK
5
250
180.0
180.0
18.0
SN74AHC1G00DCKTG4
SC70
DCK
5
250
180.0
180.0
18.0
SN74AHC1G00DRLR
SOT-5X3
DRL
5
4000
202.0
201.0
28.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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