Texas Instruments | TXS0108E-Q1 8-Bit Bi-directional, Level-Shifting, Voltage Translator for Open-Drain and Push-Pull Applications (Rev. A) | Datasheet | Texas Instruments TXS0108E-Q1 8-Bit Bi-directional, Level-Shifting, Voltage Translator for Open-Drain and Push-Pull Applications (Rev. A) Datasheet

Texas Instruments TXS0108E-Q1 8-Bit Bi-directional, Level-Shifting, Voltage Translator for Open-Drain and Push-Pull Applications (Rev. A) Datasheet
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TXS0108E-Q1
SCES861A – JUNE 2015 – REVISED FEBRUARY 2016
TXS0108E-Q1 8-Bit Bi-directional, Level-Shifting, Voltage Translator
for Open-Drain and Push-Pull Applications
1 Features
3 Description
•
This 8-bit non-inverting translator uses two separate
configurable power-supply rails. The A port tracks the
VCCA pin supply voltage. The VCCA pin accepts any
supply voltage between 1.4 V and 3.6 V. The B port
tracks the VCCB pin supply voltage. The VCCB pin
accepts any supply voltage between 1.65 V and 5.5
V. Two input supply pins allows for low Voltage
bidirectional translation between any of the 1.5 V, 1.8
V, 2.5 V, 3.3 V, and 5 V voltage nodes.
1
•
•
•
•
•
•
•
AEC-Q100 Qualified for Automotive Applications
– Device Temperature Grade 1: –40°C to 125°C
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C6
No Direction-Control Signal Needed
Maximum Data Rates
– 110 Mbps (Push Pull)
– 1.2 Mbps (Open Drain)
1.4 V to 3.6 V on A Port and 1.65 V to 5.5 V on B
Port (VCCA ≤ VCCB)
No Power-Supply Sequencing Required – Either
VCCA or VCCB Can Be Ramped First
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22 (A Port)
– 2000 V Human Body Model (A114-B)
– 1000 V Charged-Device Model (C101)
IEC 61000-4-2 ESD (B Port)
– ±8 kV Contact Discharge
– ±6 kV Air-Gap Discharge
When the output-enable (OE) input is low, all outputs
are placed in the high-impedance (Hi-Z) state.
To ensure the
down periods,
resistor. The
determined by
driver.
.
Device Information(1)
PART NUMBER
TXS0108E-Q1
PACKAGE
BODY SIZE (NOM)
TSSOP (20)
6.50 mm × 6.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
.
2 Applications
•
Hi-Z state during power-up or powertie OE to GND through a pull-down
minimum value of the resistor is
the current-sourcing capability of the
.
Automotive
Simplified Application
1.8 V
3.3 V
0.1 PF
0.1 PF
OE
VCCA
VCCB
1.8-V
System
Controller
Data
3.3-V
System
Controller
A1
A2
A3
A4
A5
A6
A7
A8
TXS0108E-Q1
GND
B1
B2
B3
B4
B5
B6
B7
B8
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TXS0108E-Q1
SCES861A – JUNE 2015 – REVISED FEBRUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
7
8
1
1
1
2
3
4
Absolute Maximum Ratings ..................................... 4
ESD Ratings ............................................................ 4
Recommended Operating Conditions ...................... 5
Thermal Information .................................................. 5
Electrical Characteristics: TA = –40°C to 125°C ...... 6
Timing Requirements: VCCA = 1.5 V ± 0.1 V ............ 6
Timing Requirements: VCCA = 1.8 V ± 0.15 V .......... 7
Timing Requirements: VCCA = 2.5 V ± 0.2 V ............ 7
Timing Requirements: VCCA = 3.3 V ± 0.3 V ............ 7
Switching Characteristics: VCCA = 1.5 V ± 0.1 V .... 8
Switching Characteristics: VCCA = 1.8 V ± 0.15 V .. 9
Switching Characteristics: VCCA = 2.5 V ± 0.2 V .. 10
Switching Characteristics: VCCA = 3.3 V ± 0.3 V .. 11
Typical Characteristics........................................ 12
Parameter Measurement Information ................ 13
8.1 Load Circuits ........................................................... 13
8.2 Voltage Waveforms................................................. 14
9
Detailed Description ............................................ 15
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
15
15
16
17
10 Application and Implementation........................ 18
10.1 Application Information.......................................... 18
10.2 Typical Application ............................................... 18
11 Power Supply Recommendations ..................... 20
12 Layout................................................................... 20
12.1 Layout Guidelines ................................................. 20
12.2 Layout Example .................................................... 20
13 Device and Documentation Support ................. 21
13.1
13.2
13.3
13.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
14 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
Changes from Original (June 2015) to Revision A
•
2
Page
Made changes to Pin Functions ............................................................................................................................................ 1
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SCES861A – JUNE 2015 – REVISED FEBRUARY 2016
5 Pin Configuration and Functions
PW PACKAGE
20-PIN TSSOP
(TOP VIEW)
A1
VCCA
1
20
2
19
A2
A3
A4
A5
A6
A7
A8
OE
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
B1
VCCB
B2
B3
B4
B5
B6
B7
B8
GND
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
A1
1
I/O
Input/output 1. Referenced to VCCA
A2
3
I/O
Input/output 2. Referenced to VCCA
A3
4
I/O
Input/output 3. Referenced to VCCA
A4
5
I/O
Input/output 4. Referenced to VCCA
A5
6
I/O
Input/output 5. Referenced to VCCA
A6
7
I/O
Input/output 6. Referenced to VCCA
A7
8
I/O
Input/output 7. Referenced to VCCA
A8
9
I/O
Input/output 8. Referenced to VCCA
B1
20
I/O
Input/output 1. Referenced to VCCB
B2
18
I/O
Input/output 2. Referenced to VCCB
B3
17
I/O
Input/output 3. Referenced to VCCB
B4
16
I/O
Input/output 4. Referenced to VCCB
B5
15
I/O
Input/output 5. Referenced to VCCB
B6
14
I/O
Input/output 6. Referenced to VCCB
B7
13
I/O
Input/output 7. Referenced to VCCB
B8
12
I/O
Input/output 8. Referenced to VCCB
GND
11
–
Ground
OE
10
I
3-state output-mode enable. Pull OE low to place all outputs in 3-state mode. Referenced to VCCA.
VCCA
2
I
A-port supply voltage. 1.5 V ≤ VCCA ≤ 3.6 V, VCCA ≤ VCCB.
VCCB
19
I
B-port supply voltage. 1.65 V ≤ VCCB ≤ 5.5 V.
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage, VCCA
Supply voltage, VCCB
Input voltage, VI (2)
Voltage applied to any output
in the high-impedance or power-off state, VO (2)
Voltage applied to any output in the high or low state, VO (2)
(3)
MAX
4.6
V
V
–0.5
5.5
A port
–0.5
4.6
B port
–0.5
6.5
A port
–0.5
4.6
B port
–0.5
6.5
A port
–0.5
VCCA + 0.5
B port
–0.5
VCCB + 0.5
Input clamp current, IIK
VI < 0
Output clamp current, IOK
VO < 0
Continuous output current, IO
Continuous current through VCCA, VCCB, or GND
Storage temperature, Tstg
(2)
(3)
V
V
V
V
–50
mA
–50
mA
–50
50
mA
–100
100
mA
150
°C
150
°C
Junction temperature, TJ
(1)
UNIT
–0.5
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative Voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCCA and VCCB are provided in the recommended operating conditions table.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
4
Electrostatic
discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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SCES861A – JUNE 2015 – REVISED FEBRUARY 2016
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
VCCA
Supply voltage
(3)
1.4
3.6
V
VCCB
Supply voltage (3)
1.65
5.5
V
VCCA (V) = 1.4 to 1.95
VCCB (V) = 1.65 to 5.5
VCCI – 0.2
VCCI
VCCA (V) = 1.95 to 3.6
VCCB (V) = 1.65 to 5.5
VCCI – 0.4
VCCI
B-Port I/Os
VCCA (V) = 1.4 to 3.6
VCCB (V) = 1.65 to 5.5
VCCI – 0.4
VCCI
V
OE
VCCA (V) = 1.4 to 3.6
VCCB (V) = 1.65 to 5.5
VCCA × 0.65
5.5
V
VCCA (V) = 1.4 to 1.95
VCCB (V) = 1.65 to 5.5
0
0.15
VCCA (V) = 1.95 to 3.6
VCCB (V) = 1.65 to 5.5
0
0.15
B-Port I/Os
VCCA (V) = 1.4 to 3.6
VCCB (V) = 1.65 to 5.5
0
0.15
V
OE
VCCA (V) = 1.4 to 3.6
VCCB (V) = 1.65 to 5.5
0
VCCA × 0.35
V
A-Port I/Os
Push-pull
VCCA (V) = 1.4 to 3.6
VCCB (V) = 1.65 to 5.5
10
ns/V
B-Port I/Os
Push-pull
VCCA (V) = 1.4 to 3.6
VCCB (V) = 1.65 to 5.5
10
ns/V
Control
input
VCCA (V) = 1.4 to 3.6
VCCB (V) = 1.65 to 5.5
10
ns/V
125
°C
A-Port I/Os
High-level input
voltage
VIH
A-Port I/Os
Low-level input
voltage
VIL
Δt/Δv
TA
(1)
(2)
(3)
Input transition
rise or fall rate
Operating free-air temperature
–40
V
V
VCCI is the VCC associated with the data input port.
VCCO is the VCC associated with the output port.
VCCA must be less than or equal to VCCB, and VCCA must not exceed 3.6 V.
6.4 Thermal Information
TXS0108E-Q1
THERMAL METRIC (1)
PW (TSSOP)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
101.5
RθJC(top)
Junction-to-case (top) thermal resistance
35.9
RθJB
Junction-to-board thermal resistance
52.4
ψJT
Junction-to-top characterization parameter
2.3
ψJB
Junction-to-board characterization parameter
51.9
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
(1)
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics: TA = –40°C to 125°C (1) (2) (3)
over recommended operating free-air temperature range (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VOHA
Port A output
high voltage
VOLA
Port A output
low voltage
VOHB
Port B output
high voltage
TA = 25°C
TA = –40°C to 125°C
VCCA (V)
VCCB (V)
1.4 to 3.6
1.65 to 5.5
IOL = 180 μA, VIB ≤ 0.15 V
1.4
1.65 to 5.5
0.4
IOL = 220 μA, VIB ≤ 0.15 V
1.65
1.65 to 5.5
0.4
IOL = 300 μA, VIB ≤ 0.15 V
2.3
1.65 to 5.5
0.4
IOL = 400 μA, VIB ≤ 0.15 V
0.55
IOH = –20 μA,
VIB ≥ VCCB – 0.4 V
MIN
TYP
MAX
MIN
VCCA × 0.67
V
3
1.65 to 5.5
IOH = –20 μA,
VIA ≥ VCCA – 0.2 V
1.4 to 3.6
1.65 to 5.5
IOL = 220 μA, VIA ≤ 0.15 V
1.4 to 3.6
1.65
IOL = 300 μA, VIA ≤ 0.15 V
1.4 to 3.6
2.3
0.4
IOL = 400 μA, VIA ≤ 0.15 V
1.4 to 3.6
3
0.55
IOL = 620 μA, VIA ≤ 0.15 V
0.55
V
0.4
Port B output
low voltage
1.4 to 3.6
4.5
II
Input leakage
current
OE:
VI = VCCI or GND
1.4
1.65 to 5.5
–1
1
IOZ
Highimpedance
state output
current
A or B port
1.4
1.65 to 5.5
–1
1
1.4 to 3.6
2.3 to 5.5
ICCA
VCCA supply
current
VI = VO = Open, IO = 0
3.6
0
2
0
5.5
–1
1.4 to 3.6
2.3 to 5.5
6
3.6
0
–1
0
5.5
1.5
VCCB supply
current
VI = VO = Open, IO = 0
V
VCCB × 0.67
VOLB
ICCB
UNIT
MAX
–2
V
2
μA
2
μA
2
μA
μA
ICCA +
ICCB
Combined
supply current
VI = VCCI or GND,
IO = 0
1.4 to 3.6
2.3 to 5.5
8
μA
ICCZA
Highimpedance
state VCCA
supply current
VI = VO = Open,
IO = 0, OE = GND
1.4 to 3.6
1.65 to 5.5
2
μA
ICCZB
Highimpedance
state VCCB
supply current
VI = VO = Open,
IO = 0, OE = GND
1.4 to 3.6
1.65 to 5.5
6
μA
Ci
Input
capacitance
OE
3.3
3.3
4.5
6.75
pF
Input-to-output
internal
capacitance
A port
3.3
3.3
6
7.6
Cio
B port
3.3
3.3
5.5
6.9
(1)
(2)
(3)
pF
VCCO is the VCC associated with the output port.
VCCI is the VCC associated with the input port.
VCCA must be less than or equal to VCCB, and VCCA must not exceed 3.6 V.
6.6 Timing Requirements: VCCA = 1.5 V ± 0.1 V
over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (unless otherwise noted)
VCC B = 1.8 V
± 0.15 V
MIN
Data rate
tw
6
Pulse
duration
VCC B = 2.5 V
± 0.2 V
VCC B= 3.3 V
± 0.3 V
MIN MAX
Push-pull
40
60
60
60
Open-drain
0.8
0.8
1
1
Push-pull
Open-drain
MAX
MIN
UNIT
MAX
Data inputs
MIN
VCC B= 5 V
± 0.5 V
25
16.7
16.7
16.7
1250
1250
1000
1000
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MAX
Mbps
ns
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6.7 Timing Requirements: VCCA = 1.8 V ± 0.15 V
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted)
VCC B = 1.8 V
± 0.15 V
MIN
Data rate
tw
Pulse
duration
MAX
VCC B = 2.5 V
± 0.2 V
MIN
VCC B= 3.3 V
± 0.3 V
MAX
VCC B= 5 V
± 0.5 V
MIN MAX
MIN
UNIT
MAX
Push-pull
45
65
70
70
Open-drain
0.8
0.8
0.8
1
Data inputs
Push-pull
22.2
15.3
15.3
15.3
Open-drain
1250
1250
1250
1000
Mbps
ns
6.8 Timing Requirements: VCCA = 2.5 V ± 0.2 V
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted)
VCCB = 2.5 V
± 0.2 V
MIN
Data rate
tw
Pulse duration
VCCB = 3.3 V
± 0.3 V
MAX
MIN
VCC = 5 V
± 0.5 V
MAX
MIN
UNIT
MAX
Push-pull
80
95
100
Open-drain
0.8
0.8
1
Data inputs
Push-pull
12.5
10.5
10
Open-drain
1250
1250
1000
Mbps
ns
6.9 Timing Requirements: VCCA = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted)
VCCB = 3.3 V
± 0.3 V
MIN
Data rate
tw
Pulse duration
VCC = 5 V
± 0.5 V
MAX
MIN
UNIT
MAX
Push-pull
100
110
Open-drain
0.8
1.2
Data inputs
Push-pull
Open-drain
10
9.1
1250
833
Mbps
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6.10 Switching Characteristics: VCCA = 1.5 V ± 0.1 V
over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCCB = 1.8 V
± 0.15 V
MIN
VCCB = 2.5 V
± 0.2 V
MAX
MIN
VCCB = 3.3 V
± 0.3 V
MAX
MIN
VCCB = 5 V
± 0.5 V
MAX
MIN
UNIT
MAX
Propagation
delay time
A-to-B
high-to-low
output
Push-pull
driving
Propagation
delay time
A-to-B
low-to-high
output
Push-pull
driving
Propagation
delay time
B-to-A
high-to-low
output
Push-pull
driving
Propagation
delay time
B-to-A
low-to-high
output
Push-pull
driving
9.5
6.2
5.1
4.2
Open-drain
driving
745
603
519
407
ten
Enable time OE-to-A or B
480
480
480
480
ns
tdis
Disable time OE-to-A or B
Push-pull
driving
400
400
400
400
ns
tPHL
tPLH
tPHL
tPLH
trA
trB
tfA
tfB
tSK(O)
8
Input rise
time
A-port rise
time
Input rise
time
B-port rise
time
Input fall
time
A-port fall
time
Open-drain
driving
Open-drain
driving
Open-drain
driving
Push-pull
driving
11
2.5
14.4
9.2
2
12.8
8.6
2
12.2
8.6
1.9
12
ns
12
0.9
720
10
0.9
12.7
3.4
13.2
554
9.8
1
11.1
2.6
9.6
473
9.7
1.5
11
2.3
8.5
384
12
2
7.5
ns
3
13.1
2.4
9.8
2
9
2
8.9
Open-drain
driving
220
982
180
716
140
592
100
481
Push-pull
driving
2.6
11.4
1.6
7.4
1
6
0.7
5
Open-drain
driving
220
1020
150
756
100
653
40
370
Push-pull
driving
2.3
9.9
1.7
7.7
1.6
6.8
1.7
6
Open-drain
driving
2.4
10
1.8
8.2
1.7
9
1.5
9.15
Push-pull
driving
2
8.7
1.3
5.5
1
3.8
1
3.1
Open-drain
driving
2
11.5
1.3
8.6
1
9.6
1
7.7
Input fall
time
B-port fall
time
Skew
(time),
output
Channel-toPush-pull
channel skew driving
ns
ns
ns
1
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1
1
1
ns
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6.11 Switching Characteristics: VCCA = 1.8 V ± 0.15 V
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted)
PARA-METER
TEST CONDITIONS
VCCB = 1.8 V
± 0.15 V
MIN
tPHL
tPLH
tPHL
Propagation
delay time
high-to-low
output
Propagation
delay time
low-to-high
output
Propagation
delay time
high-to-low
output
A-to-B
A-to-B
B-to-A
1.7
9.9
MAX
MIN
5.7
1.6
9.3
UNIT
MAX
5.6
1.5
8.9
ns
0.15
729
5.6
0.2
9.8
3.19
12.1
584
6.5
0.3
8
2
8.5
466
6.3
0.3
7.4
1.9
7.3
346
7
1.8
6.2
ns
5
Open-drain
driving
733
578
459
323
OE-to-A or B
Push-pull
driving
100
100
100
100
ns
Disable time
OE-to-A or B
Push-pull
driving
410
410
410
410
ns
Input rise
time
A-port rise time
Input rise
time
B-port rise time
Input fall time
A-port fall time
tdis
trA
tSK(O)
6.4
9
Push-pull
driving
Open-drain
driving
11.4
MIN
5.8
Enable time
tfB
2.1
MAX
7
ten
tfA
8.2
Push-pull
driving
Open-drain
driving
MIN
VCCB = 5 V
± 0.5 V
10.2
B-to-A
trB
Open-drain
driving
MAX
VCCB = 3.3 V
± 0.3 V
Push-pull
driving
Propagation
delay time
low-to-high
output
tPLH
Push-pull
driving
VCCB = 2.5 V
± 0.2 V
Input fall time
Skew (time),
output
B-port fall time
Channel-tochannel skew
Push-pull
driving
2.7
11.9
2
8.6
1.9
7.8
1.8
7.4
Open-drain
driving
250
996
200
691
150
508
110
365
Push-pull
driving
2.5
10.5
1.7
7.4
1.1
5.3
60
4.7
Open-drain
driving
250
1001
170
677
120
546
32
323
Push-pull
driving
2.1
8.8
1.6
7.1
1.4
6.8
1.4
6.06
Open-drain
driving
2.2
9
1.7
7.2
1.4
6.8
1.2
6.1
Push-pull
driving
2
8.3
1.3
5.4
0.9
3.9
0.7
3
Open-drain
driving
2
10.5
1
10.7
1
9.6
0.6
7.8
Push-pull
driving
ns
ns
ns
1
1
1
1
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6.12 Switching Characteristics: VCCA = 2.5 V ± 0.2 V
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted)
PARA-METER
TEST CONDITIONS
VCCB = 2.5 V
± 0.2 V
MIN
VCCB = 3.3 V
± 0.3 V
MAX
MIN
VCCB = 5 V
± 0.5 V
MAX
MIN
UNIT
MAX
Propagation delay
time
A-to-B
high-to-low output
Push-pull driving
5
4
3.7
tPHL
Open-drain
driving
6.2
6.3
5.8
Push-pull driving
5.2
4.3
3.9
tPLH
Propagation delay
time
A-to-B
low-to-high output
5
17.5
15.5
Propagation delay
time
B-to-A
high-to-low output
Push-pull driving
5.4
4.7
4.2
tPHL
Open-drain
driving
7.3
6
4.9
Push-pull driving
5.9
4.4
3.5
tPLH
Propagation delay
time
B-to-A
low-to-high output
5
5
5
ten
Enable time
100
100
100
ns
400
400
400
ns
OE-to-A or
B
tdis
Disable time
OE-to-A or
B
trA
Input rise time
A-port rise
time
trB
Input rise time
B-port rise
time
tfA
Input fall time
A-port fall
time
tfB
Input fall time
B-port fall
time
tSK(O)
Skew (time),
output
Channelto-channel
skew
10
Open-drain
driving
Open-drain
driving
ns
ns
Push-pull driving
Push-pull driving
1.89
7.3
1.6
6.4
1.5
5.8
110.00
692
157
529
116
377
1.70
6.5
1.3
5.1
0.9
4.32
107.00
693
140
483
77
304
Push-pull driving
1.50
5.7
1.2
4.7
1.3
3.8
Open-drain
driving
1.50
5.6
1.2
4.7
1.1
4.2
Push-pull driving
1.40
5.4
0.9
4.1
0.7
3
Open-drain
driving
0.40
14.2
0.5
19.4
0.4
3
Open-drain
driving
Push-pull driving
Open-drain
driving
Push-pull driving
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6.13 Switching Characteristics: VCCA = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted)
TEST CONDITION
(DRIVING)
PARAMETER
tPHL
Propagation
delay time
high-to-low
output
tPLH
Propagation
delay time
low-to-high
output
tPHL
Propagation
delay time
high-to-low
output
tPLH
Propagation
delay time
low-to-high
output
B-to-A
ten
Enable time
OE-to-A or B
Push-pull driving
tdis
Disable time
OE-to-A or B
Push-pull driving
A-to-B
A-to-B
B-to-A
VCCB = 3.3 V
± 0.3 V
MIN
Input rise time
A-port rise time
trB
Input rise time
B-port rise time
tfA
Input fall time
A-port fall time
tfB
Input fall time
B-port fall time
tSK(O)
Skew (time),
output
Channel-tochannel skew
MAX
MIN
UNIT
MAX
Push-pull driving
3.8
3.28
Open-drain driving
5.3
4.8
Push-pull driving
3.9
3.5
5
12.5
Push-pull driving
4.2
3.8
Open-drain driving
5.5
4.5
4.32
4.3
5
5
100
100
ns
400
ns
Open-drain driving
Push-pull driving
trA
VCCB = 5 V
± 0.5 V
Open-drain driving
400
Push-pull driving
1.5
5.7
1.4
5
Open-drain driving
129
446
99.6
337
Push-pull driving
1.35
5
1
4.24
Open-drain driving
129
427
77
290
Push-pull driving
1.4
4.5
1.3
3.5
Open-drain driving
1.4
4.4
1.2
3.7
Push-pull driving
1.3
4.2
1.1
3.1
Open-drain driving
1.3
4.2
1.1
3.1
Push-pull driving
1
1
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0.6
0.6
0.5
0.5
Low-Level Output Voltage (V)
Low-Level Output Voltage (V)
7 Typical Characteristics
0.4
0.3
0.2
TA ± ƒ&
TA = 25°C
TA = 125°C
0.1
0
0.4
0.3
0.2
TA ± ƒ&
TA = 25°C
TA = 125°C
0.1
0
0
100
200
VCCA = 2.3 V
300 400 500 600 700
Low-Level Current (µA)
VCCB = 2.7 V
800
900 1000
0
VIL(A) = 0.15 V
0.6
0.6
0.5
0.5
Low-Level Output Voltage (V)
Low-Level Output Voltage (V)
300 400 500 600 700
Low-Level Current (µA)
VCCB = 5.5 V
800
900 1000
D001
VIL(A) = 0.15 V
Figure 2. Low-Level Output Voltage (VOL(Bx))
vs Low-Level Current (IOL(Bx))
0.4
0.3
0.2
TA ± ƒ&
TA = 25°C
TA = 125°C
0
0.4
0.3
0.2
TA ± ƒ&
TA = 25°C
TA = 125°C
0.1
0
0
100
VCCA = 1.65 V
200
300
400
Low-Level Current (µA)
VCCB = 1.95 V
500
600
0
100
200
300
400
Low-Level Current (µA)
D001
VIL(A) = 0.15 V
Figure 3. Low-Level Output Voltage (VOL(Bx))
vs Low-Level Current (IOL(Bx))
12
200
VCCA = 3 V
Figure 1. Low-Level Output Voltage (VOL(Bx))
vs Low-Level Current (IOL(Bx))
0.1
100
D001
VCCA = 1.65 V
VCCB = 5.5 V
500
600
D001
VIL(A) = 0.15 V
Figure 4. Low-Level Output Voltage (VOL(Bx))
vs Low-Level Current (IOL(Bx))
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8 Parameter Measurement Information
8.1 Load Circuits
Figure 5 shows the push-pull driver circuit used for measuring data rate, pulse duration, propagation delay,
output rise-time and fall-time. Figure 6 shows the open-drain driver circuit used for measuring data rate, pulse
duration, propagation delay, output rise-time and fall-time.
VCCI
VCCO
DUT
IN
OUT
15 pF
(1)
VCCI is the VCC associated with the input port.
(2)
VCCO is the VCC associated with the output port.
1M
Figure 5. Data Rate, Pulse Duration, Propagation Delay, Output Rise-Time And Fall-Time Measurement
Using a Push-Pull Driver
VCCI
VCCO
DUT
IN
OUT
15 pF
(1)
VCCI is the VCC associated with the input port.
(2)
VCCO is the VCC associated with the output port.
1M
Figure 6. Data Rate (10 pF), Pulse Duration (10 pF), Propagation Delay, Output Rise-Time And Fall-Time
Measurement Using an Open-Drain Driver
2 × VCCO
50 k
From Output
Under Test
15 pF
(1)
tPLZ and tPHZ are the same as tdis.
(2)
tPZL and tPZH are the same as ten.
S1
Open
50 k
TEST
S1
tPZL, tPLZ
(tdis)
2 × VCCO
tPHZ, tPZH
(ten)
Open
Figure 7. Load Circuit for Enable-Time and Disable-Time Measurement
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8.2 Voltage Waveforms
tW .
VCCI
Input
VOHA/VOHB
VOHA/VOHB
0V
Figure 8. Pulse Duration (Push-Pull)
VCCI
Input
VCCI / 2
VCCI / 2
0V
tPLH
Output
tPHL
VCCO / 2
0.9
VCCO
0.1
VCCO
VOH
VCCO / 2
VOL
tr
tf
Figure 9. Propagation Delay Times
VCCA
VCCA / 2
OE input
VCCA / 2
0V
tPLZ
tPZL
VOH
Output
Waveform 1
S1 at 2 × VCCO
VCCO / 2
VCCO × 0.2
(see Note 2)
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note 2)
VOL
VOH × 0.9
VCCO
VCCO / 2
0V
•
CL includes probe and jig capacitance.
•
Waveform 1 in Figure 10 is for an output with internal such that the output is high, except when OE is high (see
Figure 7). Waveform 2 in Figure 10 is for an output with conditions such that the output is low, except when OE is
high.
•
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, dv/dt
≥ 1 V/ns.
•
The outputs are measured one at a time, with one transition per measurement.
•
tPLZ and tPHZ are the same as tdis.
•
tPZL and tPZH are the same as ten.
•
tPLH and tPHL are the same as tpd.
•
VCCI is the VCC associated with the input port.
•
VCCO is the VCC associated with the output port.
Figure 10. Enable and Disable Times
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9 Detailed Description
9.1 Overview
The TXS0108E-Q1 device is a directionless voltage-level translator specifically designed for translating logic
voltage levels. The A-port accepts I/O voltages ranging from 1.4 V to 3.6 V. The B-port accepts I/O voltages from
1.65 V to 5.5 V. The device uses pass gate architecture with edge rate accelerators (one shots) to improve the
overall data rate. The pull-up resistors, commonly used in open-drain applications, have been conveniently
integrated so that an external resistor is not needed. While this device is designed for open-drain applications,
the device can also translate push-pull CMOS logic outputs.
9.2 Functional Block Diagram
VCCB
VCCA
OE
One Shot
Accelerator
One Shot
Accelerator
Gate Bias
Rpua
Rpub
A1
B1
6 channels
One Shot
Accelerator
A2
A3
A4
A5
A6
A7
One Shot
Accelerator
Gate Bias
Rpub
Rpua
One Shot
Accelerator
B2
B3
B4
B5
B6
B7
One Shot
Accelerator
Gate Bias
Rpub
Rpua
A8
B8
Figure 11. Functional Block Diagram
Each A-port I/O has a pull-up resistor (RPUA) to VCCA and each B-port I/O has a pull-up resistor (RPUB) to VCCB.
RPUA and RPUB have a value of 40 kΩ when the output is driving low. RPUA and RPUB have a value of 4 kΩ when
the output is driving high. RPUA and RPUB are disabled when OE = Low.
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9.3 Feature Description
9.3.1 Architecture
Figure 12 describes semi-buffered architecture design this application requires for both push-pull and open-drain
mode. This application uses edge-rate accelerator circuitry (for both the high-to-low and low-to-high edges), a
high-on-resistance N-channel pass-gate transistor (on the order of 300 Ω to 500 Ω) and pull-up resistors (to
provide DC-bias and drive capabilities) to meet these requirements. This design needs no direction-control signal
(to control the direction of data flow from A to B or from B to A). The resulting implementation supports both lowspeed open-drain operation as well as high-speed push-pull operation.
VCCA
VCCB
RPUA
Translator
T1
A
Bias
One-Shot
Accelerator
OS3
P2
One-Shot
Accelerator
OS4
N2
R1
RPUB
B
R2
Npass
P1
N1
One-Shot
Accelerator
OS1
One-Shot
Accelerator
OS2
Translator
T2
Figure 12. Architecture of a TXS0108E-Q1 Cell
When transmitting data from A-ports to B-ports, during a rising edge the one-shot circuit (OS3) turns on the
PMOS transistor (P2) for a short-duration which reduces the low-to-high transition time. Similarly, during a falling
edge, when transmitting data from A to B, the one-shot circuit (OS4) turns on the N-channel MOSFET transistor
(N2) for a short-duration which speeds up the high-to-low transition. The B-port edge-rate accelerator consists of
one-shot circuits OS3 and OS4. Transistors P2 and N2 and serves to rapidly force the B port high or low when a
corresponding transition is detected on the A port.
When transmitting data from B- to A-ports, during a rising edge the one-shot circuit (OS1) turns on the PMOS
transistor (P1) for a short-duration which reduces the low-to-high transition time. Similarly, during a falling edge,
when transmitting data from B to A, the one-shot circuit (OS2) turns on NMOS transistor (N1) for a short-duration
and this speeds up the high-to-low transition. The A-port edge-rate accelerator consists of one-shots OS1 and
OS2, transistors P1 and N1 components and form the edge-rate accelerator and serves to rapidly force the A
port high or low when a corresponding transition is detected on the B port.
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Feature Description (continued)
9.3.2 Input Driver Requirements
The continuous DC-current sinking capability is determined by the external system-level open-drain (or push-pull)
drivers that are interfaced to the TXS0108E-Q1 I/O pins. Because the high bandwidth of these bidirectional I/O
circuits is used to facilitate this fast change from an input to an output and an output to an input, they have a
modest DC-current sourcing capability of hundreds of micro-amperes, as determined by the internal pull-up
resistors.
The fall time (tfA, tfB) of a signal depends on the edge-rate and output impedance of the external device driving
TXS0108E-Q1 data I/Os, as well as the capacitive loading on the data lines.
Similarly, the tPHL and maximum data rates also depend on the output impedance of the external driver. The
values for tfA, tfB, tPHL, and maximum data rates in the data sheet assume that the output impedance of the
external driver is less than 50 Ω.
9.3.3 Output Load Considerations
TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading
and to ensure that proper one-shot triggering takes place. PCB signal trace-lengths should be kept short enough
such that the round trip delay of any reflection is less than the one-shot duration. This improves signal integrity
by ensuring that any reflection sees a low impedance at the driver. The one-shot circuits have been designed to
stay on for approximately 30 ns. The maximum capacitance of the lumped load that can be driven also depends
directly on the one-shot duration. With very heavy capacitive loads, the one-shot can time-out before the signal is
driven fully to the positive rail. The one-shot duration has been set to best optimize trade-offs between dynamic
ICC, load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to
the capacitance of the TXS0108E-Q1 output. Therefore, TI recommends that this lumped-load capacitance is
considered in order to avoid one-shot retriggering, bus contention, output signal oscillations, or other adverse
system-level affects.
9.3.4 Enable and Disable
The TXS0108E-Q1 has an OE pin input that is used to disable the device by setting the OE pin low, which
places all I/Os in the Hi-Z state. The disable time (tdis) indicates the delay between the time when the OE pin
goes low and when the outputs actually get disabled (Hi-Z). The enable time (ten) indicates the amount of time
the design must allow for the one-shot circuitry to become operational after the OE pin goes high.
9.3.5 Pull-up or Pull-down Resistors on I/O Lines
The TXS0108E-Q1 has the smart pull-up resistors dynamically change value based on whether a low or a high is
being passed through the I/O line. Each A-port I/O has a pull-up resistor (RPUA) to VCCA and each B-port I/O has
a pull-up resistor (RPUB) to VCCB. RPUA and RPUB have a value of 40 kΩ when the output is driving low. RPUA and
RPUB have a value of 4 kΩ when the output is driving high. RPUA and RPUB are disabled when OE = Low. This
feature provides lower static power consumption (when the I/Os are passing a low), and supports lower VOL
values for the same size pass-gate transistor, and helps improve simultaneous switching performance.
9.4 Device Functional Modes
The TXS0108E-Q1 device has two functional modes, enabled and disabled. To disable the device set the OE pin
input low, which places all I/Os in a high impedance state. Setting the OE pin input high enables the device.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TXS0108E-Q1 can be used in level-translation applications for interfacing devices or systems operating at
different interface voltages with one another. The device is ideal for use in applications where an open-drain
driver is connected to the data I/Os. The device is appropriate for applications where a push-pull driver is
connected to the data I/Os, but the TXB0104 device, (SCES650) 4-Bit Bidirectional Voltage-Level Translator
might be a better option for such push-pull applications. The device is a semi-buffered auto-direction-sensing
voltage translator design is optimized for translation applications (for example, MMC Card Interfaces) that require
the system to start out in a low-speed open-drain mode and then switch to a higher speed push-pull mode.
10.2 Typical Application
1.8 V
3.3 V
0.1 PF
0.1 PF
VCCA
OE
VCCB
1.8-V
System
Controller
3.3-V
System
Controller
A1
A2
A3
A4
A5
A6
A7
A8
Data
TXS0108E-Q1
GND
B1
B2
B3
B4
B5
B6
B7
B8
Figure 13. Typical Application Circuit
10.2.1 Design Requirements
For this design example, use the parameters listed in Table 1. Ensure that VCCA ≤ VCCB.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
1.4 V to 3.6 V
Output voltage range
1.65 V to 5.5 V
10.2.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the TXS0108E-Q1 device to determine the input
voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low
18
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•
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the value must be less than the VIL of the input port.
Output voltage range
– Use the supply voltage of the device that the TXS0108E-Q1 device is driving to determine the output
voltage range.
– The TXS0108E-Q1 device has smart internal pull-up resistors. External pull-up resistors can be added to
reduce the total RC of a signal trace if necessary.
An external pull-down resistor decreases the output VOH and VOL. Use Equation 1 to calculate the VOH as a
result of an external pull-down resistor.
VOH = VCCx × RPD / (RPD + 4 kΩ)
(1)
10.2.3 Application Curves
VCCA = 1.8 V
VCCB = 3.3 V
Figure 14. Level-Translation of a 2.5-MHz Signal
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11 Power Supply Recommendations
During operation, ensure that VCCA ≤ VCCB at all times. The sequencing of each power supply will not damage the
device during the power up operation, so either power supply can be ramped up first. The output-enable (OE)
input circuit is designed so that it is supplied by VCCA and when the (OE) input is low, all outputs are placed in the
high-impedance state. To ensure the high-impedance state of the outputs during power up or power down, the
OE input pin must be tied to GND through a pull-down resistor and must not be enabled until VCCA and VCCB are
fully ramped and stable. The minimum value of the pull-down resistor to ground is determined by the currentsourcing capability of the driver.
12 Layout
12.1 Layout Guidelines
To ensure reliability of the device, following common printed-circuit board layout guidelines is recommended.
• Bypass capacitors should be used on power supplies. Place the capacitors as close as possible to the VCCA,
VCCB pin and GND pin.
• Short trace lengths should be used to avoid excessive loading.
• PCB signal trace-lengths must be kept short enough so that the round-trip delay of any reflection is less than
the one shot duration, approximately 30 ns, ensuring that any reflection encounters low impedance at the
source driver.
12.2 Layout Example
LEGEND
Polygonal Copper Pour
VIA to Power Plane
VIA to GND Plane (Inner Layer)
TXS0108E-Q1PWR
To Controller
1
A1
B1
20
Bypass capacitor 0.1
0.1 µF
µF
0.1
0.1 µF
µF Bypass capacitor
2
VCCA
VCCB
19
3
A2
B2
18
4
A3
B3
17
5
A4
B4
16
6
A5
B5
15
7
A6
B6
14
8
A7
B7
13
9
A8
B8
12
10
OE
GND
11
To system
To system
To Controller
To system
To Controller
To Controller
To Controller
To system
To system
To system
To Controller
To Controller
To system
To system
To Controller
Keep OE low until VCCA and VCCB are powered up
Figure 15. Layout Example
20
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Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TXS0108E-Q1
TXS0108E-Q1
www.ti.com
SCES861A – JUNE 2015 – REVISED FEBRUARY 2016
13 Device and Documentation Support
13.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TXS0108E-Q1
21
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jul-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TXS0108EQPWRQ1
Package Package Pins
Type Drawing
TSSOP
PW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
7.1
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jul-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TXS0108EQPWRQ1
TSSOP
PW
20
2000
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
26-Jan-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
TXS0108EQPWRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
TSSOP
PW
20
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
YF08EQ1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
26-Jan-2016
OTHER QUALIFIED VERSIONS OF TXS0108E-Q1 :
• Catalog: TXS0108E
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TXS0108EQPWRQ1
Package Package Pins
Type Drawing
TSSOP
PW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
7.0
1.4
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TXS0108EQPWRQ1
TSSOP
PW
20
2000
367.0
367.0
38.0
Pack Materials-Page 2
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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