Texas Instruments | SNx4AHC541 Octal Buffers/Drivers With 3-State Outputs (Rev. O) | Datasheet | Texas Instruments SNx4AHC541 Octal Buffers/Drivers With 3-State Outputs (Rev. O) Datasheet

Texas Instruments SNx4AHC541 Octal Buffers/Drivers With 3-State Outputs (Rev. O) Datasheet
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SN74AHC541, SN54AHC541
SCLS261O – OCTOBER 1995 – REVISED SEPTEMBER 2015
SNx4AHC541 Octal Buffers/Drivers With 3-State Outputs
1 Features
3 Description
•
•
The SNx4AHC541 octal buffers and drivers are ideal
for driving bus lines or buffer memory address
registers. These devices feature inputs and outputs
on opposite sides of the package to facilitate printed
circuit board layout.
1
•
Operating Range 2-V to 5.5-V VCC
Latch-Up Performance Exceeds 250 mA
Per JESD 17
On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include Testing
of All Parameters.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SNx4AHC541N
PDIP (20)
25.40 mm x 6.35 mm
SNx4AHC541DB
SSOP (20)
7.50 mm x 5.30 mm
2 Applications
SNx4AHC541PW
TSSOP (20)
6.50 mm x 4.40 mm
•
•
•
•
•
•
SNx4AHC541DGV
TVSOP (20)
5.00 mm x 4.40 mm
SNx4AHC541DW
SOIC (20)
12.80 mm x 7.50 mm
Servers
PCs and Notebooks
Network Switches
Wearable Health and Fitness Devices
Telecom Infrastructures
Electronic Points-of-Sale
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Block Diagram
1
OE1
OE2
A1
19
2
18
Y1
To Seven Other Channels
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN74AHC541, SN54AHC541
SCLS261O – OCTOBER 1995 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
4
4
4
5
5
6
6
7
7
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, VCC = 3.3 V ± 0.3 V ........
Switching Characteristics, VCC = 5 V ± 0.5 V ...........
Noise Characteristics ................................................
Operating Characteristics..........................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
8.1
8.2
8.3
8.4
9
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
9
9
9
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
10 Power Supply Recommendations ..................... 11
11 Layout................................................................... 11
11.1 Layout Guidelines ................................................. 11
11.2 Layout Example .................................................... 11
12 Device and Documentation Support ................. 12
12.1
12.2
12.3
12.4
12.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
12
12
12
12
12
13 Mechanical, Packaging, and Orderable
Information ........................................................... 12
4 Revision History
Changes from Revision N (July 2003) to Revision O
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Thermal Information table, Typical
Characteristics section, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Added Military Disclaimer to Features list. ............................................................................................................................. 1
•
Extended operating temperature range to 125°C................................................................................................................... 4
•
Added –40°C to 125°C range for SN74AHC541 in Electrical Characteristics table............................................................... 5
•
Added TA = –40°C to 125°C for SN74AHC541 in both Switching Characteristics tables. ..................................................... 6
2
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5 Pin Configuration and Functions
N, DB, PW, DGV, or DW Package
20-Pin PDIP, SSOP, TSSOP, TVSOP, SOIC
Top View
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
A3
A4
A5
A6
A7
OE2
20
A2
A1
OE1
VCC
1
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
Y1
Y2
Y3
Y4
Y5
A8
GND
Y8
Y7
Y6
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
FK Package
20-Pin LCCC
Top View
Pin Functions
PIN
NO.
I/O
NAME
DESCRIPTION
1
OE1
I
Output Enable 1
2
A1
I
A1 Input
3
A2
I
A2 Input
4
A3
I
A3 Input
5
A4
I
A4 Input
6
A5
I
A5 Input
7
A6
I
A6 Input
8
A7
I
A7 Input
9
A8
I
A8 Input
10
GND
—
Ground
11
Y8
O
Y8 Output
12
Y7
O
Y7 Output
13
Y6
O
Y6 Output
14
Y5
O
Y5 Output
15
Y4
O
Y4 Output
16
Y3
O
Y3 Output
17
Y2
O
Y2 Output
18
Y1
O
Y1 Output
19
OE2
I
Output Enable 2
20
VCC
—
Power Pin
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
7
V
(2)
–0.5
7
V
–0.5
VCC + 0.5
V
VI
Input voltage
VO
Output voltage (2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±75
mA
150
°C
Continuous current through VCC or GND
Tstg
(1)
(2)
Storage temperature
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
+1000
Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
+2000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN54AHC541
VCC
Supply voltage
VIH
High-level input voltage
SN74AHC541
MIN
MAX
2
5.5
MIN
MAX
2
5.5
VCC = 2 V
1.5
1.5
VCC = 3 V
2.1
2.1
VCC = 5.5 V
3.85
UNIT
V
V
3.85
VCC = 2 V
0.5
0.5
VCC = 3 V
0.9
0.9
VIL
Low-level Input voltage
VI
Input voltage
0
5.5
0
5.5
VO
Output voltage
0
VCC
0
VCC
V
–50
–50
µA
VCC = 3.3 V ± 0.3 V
–4
–4
VCC = 5 V ± 0.5 V
–8
–8
VCC = 2 V
50
50
VCC = 3.3 V ± 0.3 V
4
4
VCC = 5 V ± 0.5 V
8
8
100
100
20
20
VCC = 5.5 V
1.65
VCC = 2 V
IOH
High-level output current
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
4
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
–55
125
V
1.65
–40
125
V
mA
µA
mA
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
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6.4 Thermal Information
SN74AHC541
THERMAL METRIC
RθJA
(1)
DGV
(TVSOP)
DW
(SOIC)
N
(PDIP)
NS
(SO)
PW
(TSSOP)
20 PINS
20 PINS
20 PINS
20 PINS
20 PINS
20 PINS
UNIT
99.9
119.2
83.0
54.9
80.4
105.4
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
61.7
34.5
48.9
41.7
46.9
39.5
°C/W
RθJB
Junction-to-board thermal resistance
55.2
60.7
50.5
35.8
47.9
56.4
°C/W
ψJT
Junction-to-top characterization
parameter
22.6
1.2
21.1
27.9
19.9
3.1
°C/W
ψJB
Junction-to-board characterization
parameter
54.8
60.0
50.1
35.7
47.5
55.8
°C/W
(1)
Junction-to-ambient thermal resistance
DB
(SSOP)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
1.9
2
1.9
1.9
1.9
2.9
3
2.9
2.9
2.9
4.5 V
4.4
4.5
4.4
4.4
4.4
IOH = –4 mA
3V
2.58
2.48
2.48
2.48
IOH = –8 mA
4.5 V
3.94
IOH = 4 mA
IOH = 8 mA
MAX
MIN
3.8
MAX
3.8
MIN
UNIT
MAX
V
3.8
2V
0.1
0.1
0.1
0.1
3V
0.1
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
0.1
3V
0.36
0.5
0.44
0.5
V
4.5 V
0.36
0.5
0.44
0.5
VI = 5.5 V or GND
0 V to 5.5 V
±0.1
±1 (1)
±1
±1
µA
VO = VCC or GND
VI (OE) = VIL or VIH
5.5 V
±0.25
±2.5
±2.5
±2.5
µA
4
40
40
20
µA
ICC
VI = VCC or GND
Ci
VI = VCC or GND
5V
2
CO
VO = VCC or GND
5V
4
(1)
(2)
MIN
SN74AHC541
–40°C to 125°C
3V
VOL
MAX
SN74AHC541
2V
IOL = 50 µA
IOZ
SN54AHC541
TYP
VOH
(2)
TA = 25°C
MIN
IOH = –50 µA
II
VCC
IO = 0
5.5 V
10
10
pF
pF
On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
For input and output pins, IOZ includes the input leakage current.
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6.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A
Y
CL = 15 pF
OE
Y
CL = 15 pF
OE
Y
CL = 15 pF
A
Y
CL = 50 pF
OE
Y
CL = 50 pF
OE
Y
CL = 50 pF
tsk(o)
A or B
tPHL
Y
CL = 50 pF
SN54AHC541
SN74AHC541
SN74AHC541
TA = –40°C to 125°C
UNIT
TYP
MAX
MIN
MAX
MIN
MAX
MIN
MAX
5 (1)
7 (1)
1 (1)
8.5 (1)
1
8.5
1
8.5
5
(1)
7
(1)
1
(1)
8.5 (1)
1
8.5
1
8.5
6
(1)
10.5
(1)
1
(1)
(1)
1
11
1
11
6 (1)
10.5 (1)
1 (1)
11 (1)
1
11
1
11
7 (1)
11 (1)
1 (1)
12 (1)
1
12
1
12
7 (1)
11 (1)
1 (1)
12 (1)
1
12
1
12
7.5
10.5
1
12
1
12
1
12
7.5
10.5
1
12
1
12
1
12
8
14
1
16
1
16
1
16
8
14
1
16
1
16
1
16
9
15.4
1
17.5
1
17.5
1
17.5
9
15.4
1
17.5
1
17.5
1
17.5
11
1.5 (2)
CL = 50 pF
tPLH
(1)
(2)
TA = 25°C
1.5
ns
ns
ns
ns
ns
ns
ns
6.3
8.8
1
10
1
10
1
10
6.3
8.8
1
10
1
10
1
10
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
On products compliant to MIL-PRF-38535, this parameter does not apply.
6.7 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tsk(o)
(1)
(2)
6
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A
Y
CL = 15 pF
OE
Y
CL = 15 pF
OE
Y
CL = 15 pF
A
Y
CL = 50 pF
OE
Y
CL = 50 pF
OE
Y
CL = 50 pF
CL = 50 pF
TA = 25°C
SN54AHC541
SN74AHC541
TA = –40°C to 125°C
SN74AHC541
UNIT
TYP
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3.5 (1)
5 (1)
1 (1)
6 (1)
1
6
1
6
3.5 (1)
5 (1)
1 (1)
6 (1)
1
6
1
6
4.7 (1)
7.2 (1)
1 (1)
8.5 (1)
1
8.5
1
8.5
4.7 (1)
7.2 (1)
1 (1)
8.5 (1)
1
8.5
1
8.5
5 (1)
7.5 (1)
1 (1)
8 (1)
1
8
1
8
5 (1)
7.5 (1)
1 (1)
8 (1)
1
8
1
8
5
7
1
8
1
8
1
8
5
7
1
8
1
8
1
8
6.2
9.2
1
10.5
1
10.5
1
10.5
6.2
9.2
1
10.5
1
10.5
1
10.5
6
8.8
1
10
1
10
1
10
6
8.8
1
10
1
10
1
10
1 (2)
1
1
ns
ns
ns
ns
ns
ns
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
On products compliant to MIL-PRF-38535, this parameter does not apply.
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6.8 Noise Characteristics
VCC = 5 V, CL = 50 pF, TA = 25°C (1)
SN74AHC541
PARAMETER
MIN
UNIT
MAX
VOL(P)
Quiet output, maximum dynamic VOL
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
4.7
VIH(D)
High-level dynamic input voltage
3.5
VIL(D)
Low-level dynamic input voltage
(1)
V
V
1.5
V
Characteristics are for surface-mount packages only.
6.9 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
f = 1 MHz
TYP
UNIT
12
pF
6.10 Typical Characteristics
6
TPLH (ns)
5
4
3
2
2
3
4
5
Supply Voltage (V)
6
C001
Figure 1. TPD (Typical) vs VCC at CL = 15pF & TA = 25°C
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7 Parameter Measurement Information
From Output
Under Test
Test
Point
From Output
Under Test
RL = 1 kΩ
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
Input
50% VCC
50% VCC
0V
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
50% VCC
0V
tPLZ
tPZL
≈VCC
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
50% VCC
VCC
Output
Control
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
8
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8 Detailed Description
8.1 Overview
The SNx4AHC541 octal buffers/drivers are ideal for driving bus lines or buffer memory address registers. These
devices feature inputs and outputs on opposite sides of the package to facilitate printed circuit board layout.
The 3-state control gate is a two-input AND gate with active-low inputs. If either output-enable (OE1 or OE2)
input is high, all corresponding outputs are in the high-impedance state. The outputs provide noninverted data
when they are not in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor. The minimum value of the resistor is determined by the current-sinking capability of the driver.
8.2 Functional Block Diagram
1
OE1
OE2
A1
19
2
18
Y1
To Seven Other Channels
8.3 Feature Description
The SNx4AHC541 has a wide operating voltage range of 2 V to 5.5 V. It allows down voltage translations while
accepting input voltages of up to 5.5 V. The slow edges of the SNx4AHC541 enables the reduction of output
ringing.
8.4 Device Functional Modes
Table 1 lists the functional modes for the SNx4AHC541 devices.
Table 1. Function Table
(Each Buffer/Driver)
INPUTS
A
OUTPUT
Y
OE1
OE2
L
L
L
L
L
L
H
H
H
X
X
Z
X
H
X
Z
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74AHC541 is a low-drive CMOS device that can be used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. The inputs accept voltages up to 5.5 V, which allows down translation to the VCC level. Figure 4
shows how the slower edges can reduce ringing on the output compared to higher drive parts like AC.
9.2 Typical Application
Regulated 5.0 V
OE
VCC
A1
Y1
A8
Y8
µC or
5-V µC
System logic
LEDs
System Logic
GND
Figure 3. Typical Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads
so routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions table.
– For specified high and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommended Output Conditions:
– Load currents should not exceed 25 mA per output and 75 mA total for the part.
– Outputs should not be pulled above VCC.
10
Submit Documentation Feedback
Copyright © 1995–2015, Texas Instruments Incorporated
Product Folder Links: SN74AHC541 SN54AHC541
SN74AHC541, SN54AHC541
www.ti.com
SCLS261O – OCTOBER 1995 – REVISED SEPTEMBER 2015
Typical Application (continued)
9.2.3 Application Curve
4
Voltage (V)
3
2
1
A1
Y1
0
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Time (ns)
C001
Vcc = 3.3 V, CL = 15 pF, TA = 25°C
Figure 4. Simulated Propagation Delay From Input (A1) to Output (Y1)
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table. Each VCC terminal should have a good bypass capacitor to prevent
power disturbance. For devices with a single supply, 0.1 μF is recommended. If there are multiple VCC terminals
then 0.01 μF or 0.022 μF is recommended for each power terminal. It is acceptable to parallel multiple bypass
caps to reject different frequencies of noise. A 0.1 μF and 1 μF are commonly used in parallel. The bypass
capacitor should be installed as close to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states. Specified in the Figure 5 are
rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected
to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused
input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more
sense or is more convenient. It is acceptable to float outputs unless the part is a transceiver. If the transceiver
has an output enable pin, it will disable the outputs section of the part when asserted. This will not disable the
input section of the I/Os so they also cannot float when disabled.
11.2 Layout Example
Vcc
Input
Unused Input
Output
Unused Input
Output
Input
Figure 5. Layout Diagram
Copyright © 1995–2015, Texas Instruments Incorporated
Product Folder Links: SN74AHC541 SN54AHC541
Submit Documentation Feedback
11
SN74AHC541, SN54AHC541
SCLS261O – OCTOBER 1995 – REVISED SEPTEMBER 2015
www.ti.com
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN74AHC541
Click here
Click here
Click here
Click here
Click here
SN54AHC541
Click here
Click here
Click here
Click here
Click here
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
Submit Documentation Feedback
Copyright © 1995–2015, Texas Instruments Incorporated
Product Folder Links: SN74AHC541 SN54AHC541
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9685701Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629685701Q2A
SNJ54AHC
541FK
5962-9685701QRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9685701QR
A
SNJ54AHC541J
5962-9685701QSA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9685701QS
A
SNJ54AHC541W
SN74AHC541DBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA541
SN74AHC541DBRG4
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA541
SN74AHC541DGVR
ACTIVE
TVSOP
DGV
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA541
SN74AHC541DGVRG4
ACTIVE
TVSOP
DGV
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA541
SN74AHC541DW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC541
SN74AHC541DWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC541
SN74AHC541DWRE4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC541
SN74AHC541N
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 125
SN74AHC541N
SN74AHC541NSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC541
SN74AHC541PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA541
SN74AHC541PWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA541
SN74AHC541PWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
HA541
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
17-Mar-2017
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74AHC541PWRE4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA541
SN74AHC541PWRG4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA541
SNJ54AHC541FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629685701Q2A
SNJ54AHC
541FK
SNJ54AHC541J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9685701QR
A
SNJ54AHC541J
SNJ54AHC541W
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9685701QS
A
SNJ54AHC541W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54AHC541, SN74AHC541 :
• Catalog: SN74AHC541
• Automotive: SN74AHC541-Q1, SN74AHC541-Q1
• Military: SN54AHC541
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
7.5
2.5
12.0
16.0
Q1
SN74AHC541DBR
SSOP
DB
20
2000
330.0
16.4
SN74AHC541DGVR
TVSOP
DGV
20
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74AHC541DWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74AHC541NSR
SO
NS
20
2000
330.0
24.4
8.4
13.0
2.5
12.0
24.0
Q1
SN74AHC541PWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.0
1.4
8.0
16.0
Q1
SN74AHC541PWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
8.2
B0
(mm)
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AHC541DBR
SSOP
DB
20
2000
367.0
367.0
38.0
SN74AHC541DGVR
TVSOP
DGV
20
2000
367.0
367.0
35.0
SN74AHC541DWR
SOIC
DW
20
2000
367.0
367.0
45.0
SN74AHC541NSR
SO
NS
20
2000
367.0
367.0
45.0
SN74AHC541PWR
TSSOP
PW
20
2000
367.0
367.0
38.0
SN74AHC541PWR
TSSOP
PW
20
2000
364.0
364.0
27.0
Pack Materials-Page 2
PACKAGE OUTLINE
DB0020A
SSOP - 2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
C
8.2
TYP
7.4
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
18X 0.65
20
1
2X
7.5
6.9
NOTE 3
5.85
10
11
20X
B
5.6
5.0
NOTE 4
SEE DETAIL A
(0.15) TYP
0.38
0.22
0.1
C A B
2 MAX
0.25
GAGE PLANE
0 -8
0.95
0.55
0.05 MIN
DETAIL A
A 15
TYPICAL
4214851/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.85)
(R0.05) TYP
1
20
20X (0.45)
SYMM
18X (0.65)
11
10
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4214851/B 08/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
20X (1.85)
SYMM
(R0.05) TYP
1
20
20X (0.45)
SYMM
18X (0.65)
10
11
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214851/B 08/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
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damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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