Texas Instruments | SNx4LV123A Dual Retriggerable Monostable Multivibrators With Schmitt-Trigger Inputs (Rev. Q) | Datasheet | Texas Instruments SNx4LV123A Dual Retriggerable Monostable Multivibrators With Schmitt-Trigger Inputs (Rev. Q) Datasheet

Texas Instruments SNx4LV123A Dual Retriggerable Monostable Multivibrators With Schmitt-Trigger Inputs (Rev. Q) Datasheet
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SN54LV123A
SN74LV123A
SCLS393Q – APRIL 1998 – REVISED AUGUST 2015
SNx4LV123A Dual Retriggerable Monostable Multivibrators With Schmitt-Trigger Inputs
1 Features
2 Applications
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2-V to 5.5-V VCC Operation
Maximum tpd of 11 ns at 5 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2.3 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on
All Ports
Schmitt-Trigger Circuitry on A, B, and CLR Inputs
for Slow Input Transition Rates
Edge Triggered From Active-High or
Active-Low Gated Logic Inputs
Ioff Supports Partial-Power-Down Mode Operation
Retriggerable for Very Long Output Pulses,
up to 100% Duty Cycle
Overriding Clear Terminates Output Pulse
Glitch-Free Power-Up Reset on Outputs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class 11
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
AV Receivers
Blu-ray Players and Home Theaters
DVD Recorders and Players
Desktop PCs or Notebook PCs
Digital Radio and Internet Radio Players
Digital Video Cameras (DVC)
Embedded PCs
GPS: Personal Navigation Devices
Mobile Internet Devices
Network Attached Storage (NAS)
Personal Digital Assistant (PDA)
Server PSU
Solid-State Drive (SSD): Client and Enterprise
Video Analytics Servers
Wireless Headsets, Keyboard, and Mice
3 Description
The 'LV123A devices are dual retriggerable
monostable multivibrators designed for 2-V to 5.5-V
VCC operation.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LV123AD
SOIC (16)
6.00 mm x 9.90 mm
SN74LV123ADB
SSOP (16)
7.80 mm x 6.20 mm
SN74LV123ANS
SO (16)
7.80 mm x 10.20 mm
SN74LV123APW
TSSOP (16)
6.40 mm x 5.00 mm
SN74LV123ARGY
VQFN (16)
3.50 mm x 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram, Each Multivibrator (Positive Logic)
Rext/Cext
A
Cext
B
Q
CLR
R
Q
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
SN54LV123A
SN74LV123A
SCLS393Q – APRIL 1998 – REVISED AUGUST 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
8
1
1
1
2
3
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Timing Requirements, VCC = 2.5 V ± 0.2 V............... 6
Timing Requirements, VCC = 3.3 V ± 0.3 V............... 7
Timing Requirements, VCC = 5 V ± 0.5 V.................. 7
Switching Characteristics, VCC = 2.5 V ± 0.2 V ........ 7
Switching Characteristics, VCC = 3.3 V ± 0.3 V ...... 8
Switching Characteristics, VCC = 5 V ± 0.5 V ......... 8
Operating Characteristics........................................ 9
Typical Characteristics ............................................ 9
Parameter Measurement Information ................ 10
9
Detailed Description ............................................ 11
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
11
12
12
13
10 Application and Implementation........................ 14
10.1 Application Information.......................................... 14
10.2 Typical Application ............................................... 14
11 Power Supply Recommendations ..................... 18
12 Layout................................................................... 18
12.1 Layout Guidelines ................................................. 18
12.2 Layout Example .................................................... 18
13 Device and Documentation Support ................. 19
13.1
13.2
13.3
13.4
13.5
13.6
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
19
14 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision P (November 2013) to Revision Q
•
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision O (April 1998) to Revision P
Page
•
Updated document to new TI datasheet format - no specification changes .......................................................................... 1
•
Removed Ordering Information table .................................................................................................................................... 3
•
Updated operating temperature range. .................................................................................................................................. 5
2
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SCLS393Q – APRIL 1998 – REVISED AUGUST 2015
5 Description (continued)
These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method,
the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes
low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.
The output pulse duration is programmable by selecting external resistance and capacitance values. The
external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor
connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance
between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.
6 Pin Configuration and Functions
D, DB, DGV, NS, or PW Package
16-Pin SOIC, SSOP, SO, TSSOP
Top View
RGY Package
16-Pin VQFN
Top View
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
1A
1
I
Channel 1 falling edge trigger input when 1B = L; Hold low for other input methods
1B
2
I
Channel 1 rising edge trigger input when 1A = H; Hold high for other input methods
1CLR
3
I
Channel 1 rising edge trigger when 1A = H and 1B = L; Hold high for other input methods;
Can cut pulse length short by driving low during output
1Q
4
O
Channel 1 inverted output
2Q
5
O
Channel 2 output
2Cext
6
—
Channel 2 external capacitor negative connection
2Rext/Cext
7
—
Channel 2 external capacitor and resistor junction connection
GND
8
—
Ground
2A
9
I
Channel 2 falling edge trigger input when 2B = L; Hold low for other input methods
2B
10
I
Channel 2 rising edge trigger input when 2A = H; Hold high for other input methods
2CLR
11
I
Channel 2 rising edge trigger when 2A = H and 2B = L; Hold high for other input methods;
Can cut pulse length short by driving low during output
2Q
12
O
Channel 2 inverted output
1Q
13
O
Channel 1 output
1Cext
14
—
Channel 1 external capacitor negative connection
1Rext/Cext
15
—
Channel 1 external capacitor and resistor junction connection
VCC
16
—
Power supply
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
7
V
(2)
VI
Input voltage
–0.5
7
V
VO
Voltage applied to any output in the high-impedance or power-off state (2)
–0.5
7
V
VO
Output voltage in the high or low state (2) (3)
–0.5
VCC + 0.5
V
(2)
VO
Output voltage in power-off state
7
V
IIK
Input clamp current
VI < 0
–0.5
–20
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
Continuous current through VCC or GND
±50
mA
Tj
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value is limited to 5.5 V maximum.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
(1)
See
.
SN54LV123A (2)
MIN
VCC
Supply voltage
High-level input voltage
MAX
2
VCC = 2 V
VIH
NOM
SN74LV123A
5.5
Low-level input voltage
NOM
2
1.5
1.5
VCC = 2.3 V to 2.7 V
VCC ×
0.7
VCC × 0.7
VCC = 3 V to 3.6 V
VCC ×
0.7
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC ×
0.7
VCC × 0.7
VCC = 2 V
VIL
MIN
MAX
UNIT
5.5
V
V
0.5
0.5
VCC = 2.3 V to 2.7 V
VCC × 0.3
VCC ×
0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC ×
0.3
VCC = 4.5 V to 5.5 V
VCC × 0.3
VCC ×
0.3
V
VI
Input voltage
0
5.5
0
5.5
V
VO
Output voltage
0
VCC
0
VCC
V
µA
VCC = 2 V
IOH
High-level output current
–50
–50
VCC = 2.3 V to 2.7 V
–2
–2
VCC = 3 V to 3.6 V
–6
–6
–12
–12
50
50
VCC = 2.3 V to 2.7 V
2
2
VCC = 3 V to 3.6 V
6
6
VCC = 4.5 V to 5.5 V
VCC = 2 V
IOL
Low-level output current
VCC = 4.5 V to 5.5 V
Rext
External timing resistance
Cext
External timing capacitance
12
TA
5
5
VCC ≥ 3 V
1
1
No restriction
(1)
(2)
kΩ
pF
1
–55
mA
No restriction
1
Operating free-air temperature
µA
12
VCC = 2 V
Δt/ΔVCC Power-up ramp rate
mA
125
ms/V
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
Product Preview
7.4 Thermal Information
SNx4LV123A
THERMAL METRIC (1)
RθJA
(1)
Junction-to-ambient thermal resistance
D (SOIC)
DB
(SSOP)
DGV
(TVSOP)
NS (SO)
PW
(TSSOP)
RGY
(VQFN)
16 PINS
16 PINS
16 PINS
16 PINS
16 PINS
16 PINS
73
82
120
64
108
39
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
–55°C to 125°C
SN54LV123A (1)
VCC
MIN TYP
VOH
VOL
II
ICC
ICC
MAX
MIN
TYP
MAX
MIN
TYP
UNIT
MAX
IOH = –50 µA
2 V to
5.5 V
IOH = –2 mA
2.3 V
2
2
2
IOH = –6 mA
3V
2.48
2.48
2.48
IOH = –12 mA
4.5 V
3.8
3.8
3.8
IOL = 50 µA
2 V to
5.5 V
IOL = 2 mA
2.3 V
0.4
0.4
0.4
IOL = 6 mA
3V
0.44
0.44
0.44
VCC – 0.1
VCC – 0.1
VCC – 0.1
0.1
V
0.1
0.1
IOL = 12 mA
4.5 V
0.55
0.55
0.55
Rext/Cext (2)
VI = 5.5 V or GND
5.5 V
±2.5
±2.5
±25
A, B, and
CLR
0V
±1
±1
±1
VI = 5.5 V or GND
0 to
5.5 V
±1
±1
±1
Quiescent
VI = VCC or GND,
Active state
(per circuit)
Ioff
IO = 0
VI = VCC or GND,
Rext/Cext = 0.5 VCC
VI or VO = 0 to 5.5 V
Ci
(1)
(2)
Recommended
–40°C to 125°C
SN74LV123A
–40°C to 85°C
SN74LV123A
VI = VCC or GND
5.5 V
20
20
20
3V
280
280
280
4.5 V
650
650
650
5.5 V
975
975
975
0V
5
5
3.3 V
1.9
1.9
1.9
5V
1.9
1.9
1.9
V
µA
µA
µA
µA
pF
Product Preview
This test is performed with the terminal in the off-state condition.
7.6 Timing Requirements, VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 5)
PARAMETER
TEST CONDITIONS
MIN
MAX
MIN
TYP
MAX
MIN
TYP
MAX
–40°C to 125°C
SN74LV123A
MIN
6
6.5
6.5
6.5
A or B
trigger
6
6.5
6.5
6.5
Pulse
duration
trr
Pulse retrigger time
6
TYP
–40°C to 85°C
SN74LV123A
CLR
tw
(1)
(2)
–55°C to 125°C
SN54LV123A (1)
TA = 25°C
Rext = 1
kΩ
TYP
UNIT
MAX
ns
Cext =
100 pF
See (2)
94
See (2)
See (2)
See (2)
ns
Cext =
0.01 µF
See (2)
2
See (2)
See (2)
See (2)
µs
Product Preview
See retriggering data in the Application Information section.
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7.7 Timing Requirements, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 5)
PARAMETER
MIN
tw
trr
(1)
(2)
Pulse
duration
–55°C to 125°C
SN54LV123A (1)
TA = 25°C
TEST CONDITIONS
TYP
MAX
MIN
TYP
–40°C to 85°C
SN74LV123A
MAX
MIN
TYP
–40°C to 125°C
SN74LV123A
MAX
MIN TYP
UNIT
MAX
CLR
5
5
5
5
A or B
trigger
5
5
5
5
See (2)
See (2)
ns
See (2)
µs
Pulse retrigger time
Rext = 1
kΩ
Cext =
100 pF
See (2)
76
See (2)
Cext =
0.01 µF
See (2)
1.8
See (2)
See (2)
ns
Product Preview
See retriggering data in the Application Information section.
7.8 Timing Requirements, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 5)
PARAMETER
tw
trr
(1)
(2)
Pulse
duration
–55°C to 125°C
SN54LV123A (1)
TA = 25°C
TEST
CONDITIONS
MIN
TY
P
MA
X
MIN
TYP
–40°C to 85°C
SN74LV123A
MAX
MIN
TYP
–40°C to 125°C
SN74LV123A
MAX
MIN
CLR
5
5
5
5
A or B
trigger
5
5
5
5
Pulse retrigger time
Rext = 1
kΩ
TYP
UNIT
MAX
ns
Cext =
100 pF
See (2)
59
See (2)
See (2)
See (2)
ns
Cext =
0.01
µF
See (2)
1.5
See (2)
See (2)
See (2)
µs
Product Preview
See retriggering data in the Application Information section.
7.9 Switching Characteristics, VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 5)
PARAMETER
tpd
tpd
FROM
(INPUT)
TO
TEST
(OUTPUT) CONDITIONS
MIN
(1)
(2)
(3)
(4)
MAX
MIN
TYP
MAX
MIN
TYP
–40°C to 125°C
SN74LV123A
MAX
MIN TYP
Q or Q
14.5
31.4 (2)
1 (2)
37 (2)
1
37
1
37
Q or Q
13
25 (2)
1 (2)
29.5 (2)
1
29.5
1
29.5
CLR
trigger
Q or Q
15.1
33.4 (2)
1 (2)
39 (2)
1
39
1
39
A or B
Q or Q
16.6
36
1
42
1
42
1
42
CLR
Q or Q
14.7
32.8
1
34.5
1
34.5
1
34.5
CLR
trigger
Q or Q
17.4
38
1
44
1
44
1
44
197
260
CL = 15 pF
CL = 50 pF
320
320
UNIT
MAX
CLR
Q or Q
Δtw (4)
TYP
–40°C to 85°C
SN74LV123A
A or B
CL = 50 pF
Cext = 28 pF
Rext = 2 kΩ
tw (3)
–55°C to 125°C
SN54LV123A (1)
TA = 25°C
ns
ns
320
ns
CL = 50 pF
Cext = 0.01 µF
Rext = 10 kΩ
90
100
110
90
110
90
110
90
110
µs
CL = 50 pF
Cext = 0.1 µF
Rext = 10 kΩ
0.9
1
1.1
0.9
1.1
0.9
1.1
0.9
1.1
ms
CL = 50 pF
±1%
Product Preview
On products compliant to MIL-PRF-38535, this parameter is not production tested.
tw = Duration of pulse at Q and Q outputs
Δtw = Output pulse-duration variation (Q and Q) between circuits in same package
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7.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 5)
PARAMETER
FROM
(INPUT)
A or B
tpd
tpd
TO
TEST
(OUTPUT) CONDITIONS
20.6 (2)
1 (2)
24 (2)
1
24
1
24
9.3
(2)
(2)
18.5 (2)
1
18.5
1
18.5
MAX
MIN
TYP
MAX
CLR
Q or Q
CLR
trigger
Q or Q
10.6
22.4 (2)
1 (2)
26 (2)
1
26
1
26
A or B
Q or Q
11.8
24.1
1
27.5
1
27.5
1
27.5
CLR
Q or Q
10.5
19.3
1
22
1
22
1
22
CLR
trigger
Q or Q
12.3
25.9
1
29.5
1
29.5
1
29.5
182
240
CL = 15 pF
CL = 50 pF
tw (3)
Q or Q
Δtw (4)
1
MIN TYP
UNIT
10.2
15.8
MAX
–40°C to 125°C
SN74LV123A
MAX
Q or Q
MIN TYP
–40°C to 85°C
SN74LV123A
MIN TYP
CL = 50 pF
Cext = 28 pF
Rext = 2 kΩ
(1)
(2)
(3)
(4)
–55°C to 125°C
SN54LV123A (1)
TA = 25°C
300
300
ns
ns
300
ns
CL = 50 pF
Cext = 0.01 µF
Rext = 10 kΩ
90
100
110
90
110
90
110
90
110
µs
CL = 50 pF
Cext = 0.1 µF
Rext = 10 kΩ
0.9
1
1.1
0.9
1.1
0.9
1.1
0.9
1.1
ms
CL = 50 pF
±1%
Product Preview
On products compliant to MIL-PRF-38535, this parameter is not production tested.
tw = Duration of pulse at Q and Q outputs
Δtw = Output pulse-duration variation (Q and Q) between circuits in same package
7.11 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 5)
PARAMETER
tpd
tpd
FROM
(INPUT)
TO
TEST
(OUTPUT) CONDITIONS
MIN TYP
(1)
(2)
(3)
(4)
8
MIN
TYP
MAX
MIN
TYP
–40°C to 125°C
SN74LV123A
MAX
MIN TYP
Q or Q
7.1
12 (2)
1 (2)
14 (2)
1
14
1
14
Q or Q
6.5
9.4 (2)
1 (2)
11 (2)
1
11
1
11
(2)
(2)
(2)
1
15
1
15
CL = 15 pF
CLR
trigger
Q or Q
7.4
A or B
Q or Q
8.3
14
1
16
1
16
1
16
CLR
Q or Q
7.4
11.4
1
13
1
13
1
13
CLR
trigger
Q or Q
8.7
14.9
1
17
1
17
1
17
167
200
CL = 50 pF
12.9
1
15
240
240
UNIT
MAX
CLR
Q or Q
Δtw (4)
MAX
–40°C to 85°C
SN74LV123A
A or B
CL = 50 pF
Cext = 28 pF
Rext = 2 kΩ
tw (3)
–55°C to 125°C
SN54LV123A (1)
TA = 25°C
ns
ns
240
ns
CL = 50 pF
Cext = 0.01 µF
Rext = 10 kΩ
90
100
110
90
110
90
110
90
110
µs
CL = 50 pF
Cext = 0.1 µF
Rext = 10 kΩ
0.9
1
1.1
0.9
1.1
0.9
1.1
0.9
1.1
ms
CL = 50 pF
±1%
Product Preview
On products compliant to MIL-PRF-38535, this parameter is not production tested.
tw = Duration of pulse at Q and Q outputs
Δtw = Output pulse-duration variation (Q and Q) between circuits in same package
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7.12 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
f = 10 MHz
VCC
TYP
3.3 V
44
5V
49
UNIT
pF
7.13 Typical Characteristics
Operation of the devices at these or any other conditions beyond those indicated under Recommended Operating Conditions
is not implied.
10.00
1.20
Output Pulse Duration Constant − K
t rr − Minimum Retrigger Time − ms
RT = 1 kΩ
TA = 25°C
CT = 0.01 µF
1.00
CT = 1000 pF
0.10
CT = 100 pF
1.15
1.10
CT = 1000 pF
1.05
CT = 1 µF, CT = 0.1 µF
0.95
2
3
4
5
6
0.90
1.5
VCC − Supply Voltage − V
Figure 1. Minimum Trigger vs VCC Characteristics
CT − External Capacitor Value − mF
0.001
For Capacitor Values of
0.001 µF or Greater,
K = 1.0
(K is Independent of R)
0.0001
TA = 25°C
VCC = 5 V
0.00001
1.00 1.50 2.00
2.5
3
3.5
4
4.5 5
5.5
6
VCC − Supply Voltage − V
Figure 2. Output Pulse-Duration Constant vs Supply Voltage
Relative Frequency of Occurance
1
CT = 0.01 µF
1.00
0.01
0
RT = 10 kΩ
TA = 25°C
tw = K × CT × RT
2
VCC = 5 V
TA = 25°C
CT = 50 pF
RT = 10 kΩ
Mean = 856 ns
Median = 856 ns
Std. Dev. = 3.5 ns
2.50 3.00 3.50 4.00 4.50
Multiplier Factor − K
Figure 3. External Capacitance vs Multiplier Factor
−3 Std. Dev.
+3 Std. Dev.
Median
99% of Data Units
tw − Output Pulse Duration
Figure 4. Distribution of Units vs Output Pulse Duration
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8 Parameter Measurement Information
Test
Point
From Output
Under Test
tw
VCC
CL
(see Note A)
Inputs or
Outputs
50% VCC
50% VCC
0V
VOLTAGE WAVEFORMS
PULSE DURATION
LOAD CIRCUIT
VCC
Input A
(see Note B)
50% VCC
0V
VCC
Input B
(see Note B)
50% VCC
50% VCC
0V
50% VCC
tPLH
0V
tPLH
VOH
In-Phase
Output
50% VCC
In-Phase
Output
VOL
VOH
50% VCC
VOL
tPHL
50% VCC
tPHL
tPHL
Out-of-Phase
Output
VCC
Input CLR
(see Note B)
Out-of-Phase
Output
tPLH
50% VCC
VOLTAGE WAVEFORMS
DELAY TIMES
VOH
50% VCC
VOL
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR≤ 1 MHz, ZO = 50 Ω, tr – 3 ns, t f – 3 ns.
C. The outputs are measured one at a time, with one input transition per measurement.
Figure 5. Load Circuit and Voltage Waveforms
10
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9 Detailed Description
9.1 Overview
The SNx4LV123A devices contain two independent monostable multivibrators. They produce a specific width
high output pulse when triggered (Q is normally high, pulse is low). The device uses an external RC circuit to
determine the output pulse length, which is explained in detail in the Application Information section.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition
rates with jitter-free triggering at the outputs.
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or highlevel-active (B) input. Pulse duration can be reduced by taking CLR low. The Figure 7 illustrates pulse control by
retriggering the inputs and early clearing.
During power-up, Q outputs are in the low state, and Q outputs are in the high state. The outputs are glitch free,
without applying a reset pulse.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Pin assignments for these devices are identical to those of the 'AHC123A and 'AHCT123A devices for
interchangeability, when allowed.
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9.2 Functional Block Diagrams
Rext/Cext
A
Cext
B
Q
CLR
Q
R
Figure 6. Logic Diagram, Each Multivibrator (Positive Logic)
trr
A
B
CLR
Rext/Cext
Q
Q
tw
tw
tw + trr
Figure 7. Input and Output Timing Diagram
9.3 Feature Description
The 'LV123A devices operate over a wide supply range from 2 V to 5.5 V. The propagation delay has a
maximum of 11 ns at 5-V supply. The typical output ground bounce is less than 0.8 V at 3.3-V supply and 25°C.
The typical output VOH undershoot is greater than 2.3 V at 3.3-V supply and 25°C.
These parts support mixed-mode voltage operation on all ports.
Schmitt-trigger circuitry on the A, B, and CLR inputs allow for slow input transition rates and noisy input signals.
This device can be configured for rising or falling edge triggering.
This device supports partial-power-down mode operation.
This device is retriggerable for very long output pulses up to 100% duty cycle.
The clear signal overrides an output pulse and terminates it early.
Glitch-free power-up reset on outputs.
12
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9.4 Device Functional Modes
Table 1 lists the functional modes of the 'LV123A devices.
Table 1. Function Table
(Each Multivibrator)
INPUTS
OUTPUTS
CLR
A
B
Q
Q
L
X
X
L
H
X
H
X
L
H
L
H
X
X
L
H
L
↑
H
↓
H
↑
L
H
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SNx4LV123A device is a dual monostable multivibrator. It can be configured for many pulse width outputs
and rising- or falling-edge triggering. The application shown here could be used to signal separate interruptable
inputs on a microcontroller when an input had a rising or falling edge.
10.2 Typical Application
Rising Edge Detector
1
A
VCC
Q
OUTPUT 1
Q
B
CLR
Cext
Rext/Cext
INPUT
C
VCC
R
Falling Edge Detector
VCC
2
A
Q
OUTPUT 2
Q
B
CLR
Cext
Rext/Cext
C
VCC
R
Figure 8. Simplified Application Schematic
10.2.1 Design Requirements
CAUTION
To prevent malfunctions due to noise, connect a high-frequency capacitor between
VCC and GND, and keep the wiring between the external components and Cext and
Rext/Cext terminals as short as possible.
14
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Typical Application (continued)
10.2.1.1 Power-Down Considerations
Large values of Cext can cause problems when powering down the 'LV123A devices because of the amount of
energy stored in the capacitor. When a system containing this device is powered down, the capacitor can
discharge from VCC through the protection diodes at pin 2 or pin 14. Current through the input protection diodes
must be limited to 30 mA; therefore, the turn-off time of the VCC power supply must not be faster than t = VCC ×
Cext/30 mA. For example, if VCC = 5 V and Cext = 15 pF, the VCC supply must turn off no faster than t = (5 V) ×
(15 pF)/30 mA = 2.5 ns. Usually, this is not a problem because power supplies are heavily filtered and cannot
discharge at this rate. When a more rapid decrease of VCC to zero occurs, the 'LV123A devices can sustain
damage. To avoid this possibility, use external clamping diodes.
10.2.1.2 Output Pulse Duration
The output pulse duration, tw, is determined primarily by the values of the external capacitance (CT) and timing
resistance (RT). The timing components are connected as shown in Figure 9.
VCC
RT
CT
To Rext/Cext
Terminal
To Cext
Terminal
Figure 9. Timing-Component Connections
If CT is ≥1000 pF and K = 1.0, the pulse duration is given by:
tw = K × RT × CT
where
•
•
•
•
tw = pulse duration in ns
RT = external timing resistance in kΩ
CT = external capacitance in pF
K = multiplier factor
(1)
if CT is <1000 pF, K can be determined from Figure 3
Equation 1 and Figure 13 can be used to determine values for pulse duration, external resistance, and external
capacitance.
10.2.1.3 Retriggering Data
The minimum input retriggering time (tMIR) is the minimum time required after the initial signal before retriggering
the input. After tMIR, the device retriggers the output. Experimentally, it also can be shown that to retrigger the
output pulse, the two adjacent input signals must be tMIR apart, where tMIR = 0.30 × tw. The retrigger pulse
duration is calculated as shown in Figure 10.
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Typical Application (continued)
tMIR
Input
tRT = tw + tPLH = (K × RT × CT) + tPLH
tRT
tw
tPLH
Output
Where:
tMIR = Minimum Input Retriggering Time
tPLH = Propagation Delay
tRT = Retrigger Time
tw
= Output Pulse Duration Before Retriggering
Figure 10. Retrigger Pulse Duration
The minimum value from the end of the input pulse to the beginning of the retriggered output must be
approximately 15 ns to ensure a retriggered output (see Figure 11).
Input
tMRT
Output
tMRT = Minimum Time Between the End of the Second Input Pulse and the Beginning of the Retriggered Output
tMRT = 15 ns
Figure 11. Input and Output Requirements
10.2.2 Detailed Design Procedure
• Timing requirements:
– The pulse width must be long enough to be read by the desired output system, but short enough so that
the output pulse completes prior to the next trigger event. It is recommended to make the output pulse just
10% longer than the minimum required for the output system.
• Recommended input conditions:
– Slow or noisy inputs are allowed on A, B, and CLR due to Schmitt-trigger input circuitry.
– Specified high and low levels. See (VIH and VIL) in Recommended Operating Conditions.
• Recommended output conditions:
– Load currents must not exceed the values listed in Absolute Maximum Ratings.
16
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Typical Application (continued)
10.2.3 Application Curves
Operation of the devices at these or any other conditions beyond those indicated under Recommended Operating Conditions
is not implied.
1.00E+07
VCC = 3 V
TA = 25°C
1.00E+06
t w − Output Pulse Duration − ns
t w − Output Pulse Duration − ns
1.00E+07
RT = 1 MΩ
1.00E+05
RT = 100 kΩ
1.00E+04
RT = 10 kΩ
1.00E+03
VCC = 4.5 V
TA = 25°C
1.00E+06
RT = 1 MΩ
1.00E+05
RT = 100 kΩ
1.00E+04
RT = 10 kΩ
1.00E+03
RT = 1 kΩ
RT = 1 kΩ
1.00E+02
101
102
103
104
1.00E+02
101
105
103
104
105
CT − External Timing Capacitance − pF
Figure 13. Output Pulse Duration vs. External Timing
Capacitance
CT − External Timing Capacitance − pF
Figure 12. Output Pulse Duration vs. External Timing
Capacitance
14%
1.00E+09
VCC = 5 V
TA = 25°C
12%
Variation in Output Pulse Duration
1.00E+08
RT = 200kΩ
1.00E+07
t w − Output Pulse Duration − ns
102
RT = 150kΩ
1.00E+06
RT = 80kΩ
1.00E+05
RT = 10kΩ
1.00E+04
1.00E+03
RT = 5kΩ
10%
tw = 866 ns at:
VCC = 5 V
RT = 10 kΩ
CT = 50 pF
TA = 25°C
VCC = 2.5 V
VCC = 3 V
VCC = 3.5 V
8%
VCC = 4 V
6%
VCC = 5 V
4%
VCC = 6 V
VCC = 7 V
2%
0%
−2%
−4%
1.00E+02
−6%
−60
RT = 1kΩ
1.00E+01
−40
−20
0
20
40
60
80
100
120
140
160
180
Temperature − °C
1.00E+00
1
10
102
103
104
105
106
107
CT − External Timing Capacitance − pF
Figure 14. Output Pulse Duration
vs External Timing Capacitance
Figure 15. Variations in Output Pulse Duration
vs Temperature
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11 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Absolute Maximum Ratings. Each VCC terminal must have a good bypass capacitor to prevent power
disturbance. For devices with a single supply, TI recommends a 0.1-µF capacitor. If there are multiple VCC
terminals, then TI recommends a 0.01-µF or 0.022-µF capacitor for each power terminal. Multiple bypass
capacitors can be paralleled to reject different frequencies of noise. Frequencies of 0.1 μF and 1 μF are
commonly used in parallel. The bypass capacitor must be installed as close as possible to the power terminal for
best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices, inputs must never float. In many cases, functions or parts of functions of
digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only
three of the four buffer gates are used. Such input pins must not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that must be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC whichever makes more sense or is more convenient. Floating outputs is generally acceptable, unless the
part is a transceiver.
12.2 Layout Example
Figure 16. Layout Recommendation
BETTER
BEST
2W
WORST
1W min.
W
Figure 17. Trace Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation, please see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54LV123A
Click here
Click here
Click here
Click here
Click here
SN74LV123A
Click here
Click here
Click here
Click here
Click here
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Jul-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LV123AD
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV123A
SN74LV123ADBR
ACTIVE
SSOP
DB
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV123A
SN74LV123ADG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV123A
SN74LV123ADGVR
ACTIVE
TVSOP
DGV
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV123A
SN74LV123ADR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LV123A
SN74LV123ADRE4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV123A
SN74LV123ADRG4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV123A
SN74LV123ANSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
74LV123A
SN74LV123APW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV123A
SN74LV123APWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV123A
SN74LV123APWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LV123A
SN74LV123APWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV123A
SN74LV123APWT
ACTIVE
TSSOP
PW
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV123A
SN74LV123ARGYR
ACTIVE
VQFN
RGY
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LV123A
SN74LV123ARGYRG4
ACTIVE
VQFN
RGY
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LV123A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Jul-2015
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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OTHER QUALIFIED VERSIONS OF SN74LV123A :
• Automotive: SN74LV123A-Q1
• Enhanced Product: SN74LV123A-EP
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
15-Jul-2015
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
31-May-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LV123ADGVR
TVSOP
DGV
16
2000
330.0
12.4
6.8
4.0
1.6
8.0
12.0
Q1
SN74LV123ADR
SOIC
D
16
2500
330.0
16.8
6.5
10.3
2.1
8.0
16.0
Q1
SN74LV123ADR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
SN74LV123ADRG4
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
SN74LV123APWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV123APWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV123APWRG4
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV123APWT
TSSOP
PW
16
250
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV123ARGYR
VQFN
RGY
16
3000
330.0
12.4
3.8
4.3
1.5
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-May-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV123ADGVR
TVSOP
DGV
16
2000
367.0
367.0
35.0
SN74LV123ADR
SOIC
D
16
2500
364.0
364.0
27.0
SN74LV123ADR
SOIC
D
16
2500
333.2
345.9
28.6
SN74LV123ADRG4
SOIC
D
16
2500
333.2
345.9
28.6
SN74LV123APWR
TSSOP
PW
16
2000
364.0
364.0
27.0
SN74LV123APWR
TSSOP
PW
16
2000
367.0
367.0
35.0
SN74LV123APWRG4
TSSOP
PW
16
2000
367.0
367.0
35.0
SN74LV123APWT
TSSOP
PW
16
250
367.0
367.0
35.0
SN74LV123ARGYR
VQFN
RGY
16
3000
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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