Texas Instruments | SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear (Rev. G) | Datasheet | Texas Instruments SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear (Rev. G) Datasheet

Texas Instruments SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear (Rev. G) Datasheet
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SN74LVC1G175
SCES560G – MARCH 2004 – REVISED JUNE 2015
SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear
1 Features
3 Description
•
This single D-type flip-flop is designed for 1.65-V to
5.5-V VCC operation.
1
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Available in the Texas Instruments
NanoFree™ Package
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Supports Down Translation to VCC
Max tpd of 4.3 ns at 3.3 V
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
The SN74LVC1G175 device has an asynchronous
clear (CLR) input. When CLR is high, data from the
input pin (D) is transferred to the output pin (Q) on
the clock's (CLK) rising edge. When CLR is low, Q is
forced into the low state, regardless of the clock edge
or data on D.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
SN74LVC1G175DBV
PACKAGE
SOT-23 (6)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
2 Applications
SN74LVC1G175DCK SC70 (6)
2.00 mm × 1.25 mm
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SN74LVC1G175DRY SON (6)
1.45 mm × 1.00 mm
SN74LVC1G175YZP
1.41 mm × 0.91 mm
TV/Set Top Box/Audio
EPOS (Electronic Point-of-Sale)
Motor Drives
PC/Notebook
Servers
Factory Automation and Control
Tablets
Medical Healthcare and Fitness
Smart Grid
Telecom Infrastructure
Enterprise Switching
Projectors
Storage
DSBGA (6)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
CLR
CLK
D
6
1
3
D
C1
4
Q
R
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G175
SCES560G – MARCH 2004 – REVISED JUNE 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
4
4
4
5
5
6
6
6
6
7
7
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements, –40°C to 85°C.......................
Timing Requirements, –40°C to 125°C.....................
Switching Characteristics, –40°C to 85°C.................
Switching Characteristics, –40°C to 85°C.................
Switching Characteristics, –40°C to 125°C.............
Operating Characteristics........................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 8
8
Detailed Description ............................................ 10
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
10
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 12
11.1 Layout Guidelines ................................................. 12
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
14
13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (December 2013) to Revision G
Page
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Added Applications ................................................................................................................................................................. 1
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Added Device Information table ............................................................................................................................................. 1
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Added ESD Ratingss table. .................................................................................................................................................... 4
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Added Thermal Information table ........................................................................................................................................... 5
•
Added Typical Characteristics. ............................................................................................................................................... 7
Changes from Revision E (June 2008) to Revision F
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Updated Features. .................................................................................................................................................................. 1
2
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SCES560G – MARCH 2004 – REVISED JUNE 2015
5 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
DCK Package
6-Pin SC70
Top View
CLK
1
6
CLR
GND
2
5
VCC
D
3
CLK
1
6
CLR
GND
2
5
VCC
D
3
4
Q
Q
4
DRY Package
6-Pin SON
Top View
YZP Package
6-Pin DSBGA
Bottom View
CLK
1
6
CLR
GND
2
5
VCC
D
3
4
Q
D
3 4
GND
2 5
CLK
1 6
Q
VCC
CLR
See mechanical drawings for dimensions.
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
CLK
1
I
Clock Input
CLR
6
I
Clear Data Input
D
3
I
Data Input
GND
2
—
Ground
Q
4
O
Output
VCC
5
—
Power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCC
Supply voltage
–0.5
6.5
V
VI
Input voltage
–0.5
6.5
V
VO
Voltage applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltageapplied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
150
°C
Continuous current through VCC or GND
Tstg
(1)
(2)
(3)
Storage temperature
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
Operating
Data retention only
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
MIN
MAX
1.65
5.5
1.5
UNIT
V
0.65 × VCC
1.7
V
2
0.7 × VCC
VCC = 1.65 V to 1.95 V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VIL
Low-level input voltage
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V
VCC = 2.3 V
IOH
High-level output current
VCC = 3 V
VCC = 4.5 V
(1)
4
V
0.3 × VCC
–4
–8
–16
mA
–24
–32
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
VCC = 1.65 V
4
VCC = 2.3 V
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
UNIT
8
16
VCC = 3 V
mA
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
ns/V
10
–40
125
°C
6.4 Thermal Information
SN74LVC1G175
THERMAL METRIC (1)
RθJA
(1)
Junction-to-ambient thermal resistance
DBV (SOT-23)
DCK (SC70)
DRY (SON)
YZP (DSBGA)
6 PINS
6 PINS
6 PINS
6 PINS
165
259
234
123
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = –100 µA
VOH
1.65 V to 5.5 V
(1)
MIN
VCC – 0.1
VCC – 0.1
1.2
1.2
IOH = –8 mA
2.3 V
1.9
1.9
2.4
2.4
2.3
2.3
IOH = –16 mA
3V
MAX
IOL = 100 µA
1.65 V to 5.5 V
0.1
0.1
IOL = 4 mA
1.65 V
0.45
0.45
IOL = 8 mA
2.3 V
0.3
0.3
0.4
0.4
0.55
0.55
0.55
0.55
II
VI = 5.5 V or GND
Ioff
VI or VO = 5.5 V
ICC
VI = 5.5 V or GND, IO = 0
3.8
3V
4.5 V
One input at VCC – 0.6 V,
Other inputs at VCC or GND
VI = VCC or GND
UNIT
V
4.5 V
IOL = 16 mA
3.8
TYP (1)
IOH = –32 mA
IOL = 32 mA
Ci
–40°C to 125°C
MAX
1.65 V
IOL = 24 mA
ΔICC
TYP (1)
IOH = –4 mA
IOH = –24 mA
VOL
–40°C to 85°C
MIN
V
0 to 5.5 V
±1
±1
µA
0
±10
±10
µA
1.65 V to 5.5 V
10
10
µA
3 V to 5.5 V
500
500
µA
3.3 V
3
3
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
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6.6 Timing Requirements, –40°C to 85°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
–40°C to 85°C
VCC = 1.8 V
± 0.15 V
MIN
fclock
Clock frequency
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
100
tw
Pulse duration
tsu
Setup time, before CLK↑
th
Hold time, data after CLK↑
VCC = 3.3 V
± 0.3 V
MIN
VCC = 5 V
± 0.5 V
MAX
125
MIN
UNIT
MAX
150
175
CLR
Low
5.6
3
2.8
2.5
CLK
High or low
3.5
3
2.8
2.5
Data
3
2.5
2
1.5
CLR inactive
0
0
0.5
0.5
0
0
0.5
0.5
MHz
ns
ns
ns
6.7 Timing Requirements, –40°C to 125°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
–40°C to 125°C
VCC = 1.8 V
± 0.15 V
MIN
fclock
Clock frequency
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
100
tw
Pulse duration
tsu
Setup time, before CLK↑
th
Hold time, data after CLK↑
VCC = 3.3 V
± 0.3 V
MIN
VCC = 5 V
± 0.5 V
MAX
125
MIN
150
Low
5.6
3
2.8
2.5
CLK
High or low
3.5
3
2.8
2.5
CLR inactive
MAX
175
CLR
Data
UNIT
3
2.5
2
1.5
0.5
0.5
0.7
0.7
0.5
0.5
0.7
0.7
MHz
ns
ns
ns
6.8 Switching Characteristics, –40°C to 85°C
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 2)
–40°C to 85°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
MIN
fmax
VCC = 2.5 V
± 0.2 V
MAX
MIN
100
CLK
tpd
CLR
Q
VCC = 3.3 V
± 0.3 V
MAX
125
MIN
MAX
150
VCC = 5 V
± 0.5 V
MIN
UNIT
MAX
175
MHz
2.5
12.9
2
6.5
1.4
4.6
1
3
2.5
12.4
2
6
1.2
4.3
1
3.2
ns
6.9 Switching Characteristics, –40°C to 85°C
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 3)
–40°C to 85°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
MIN
fmax
tpd
6
VCC = 2.5 V
± 0.2 V
MAX
100
CLK
CLR
Q
MIN
VCC = 3.3 V
± 0.3 V
MAX
125
MIN
MAX
150
VCC = 5 V
± 0.5 V
MIN
UNIT
MAX
175
MHz
2.7
13.4
2.2
7.1
1.6
5.7
1.5
4
2.7
12.9
2.2
7
1.5
5.8
1.3
4.1
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6.10 Switching Characteristics, –40°C to 125°C
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 3)
–40°C to 125°C
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
MIN
fmax
VCC = 2.5 V
± 0.2 V
MAX
100
CLK
tpd
Q
CLR
MIN
VCC = 3.3 V
± 0.3 V
MAX
125
MIN
MAX
150
VCC = 5 V
± 0.5 V
MIN
UNIT
MAX
175
MHz
2.7
15.4
2.2
8.1
1.6
6.7
1.5
5
2.7
14.9
2.2
8
1.5
6.8
1.3
5.1
ns
6.11 Operating Characteristics
TA = 25°C
Cpd
PARAMETER
TEST CONDITIONS
Power dissipation capacitance
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
18
19
19
21
UNIT
pF
6.12 Typical Characteristics
21.5
Power Dissipation Capacitance (pF)
21
20.5
20
19.5
19
18.5
18
Typical
&KDUDFWHU«
17.5
0
1
2
3
4
5
6
Supply Voltage [VCC] (V)
C001
Figure 1. Voltage vs Capacitance
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
15 pF
15 pF
15 pF
15 pF
1 MW
1 MW
1 MW
1 MW
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
8
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Parameter Measurement Information (continued)
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
This single D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G175 device has an asynchronous clear (CLR) input. When CLR is high, data from the input pin
(D) is transferred to the output pin (Q) on the clock's (CLK) rising edge. When CLR is low, Q is forced into the
low state, regardless of the clock edge or data on D.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
8.2 Functional Block Diagram
CLR
CLK
D
6
1
3
D
4
C1
Q
R
8.3 Feature Description
The SN74LVC1G175 device has a wide operating VCC range of 1.65 V to 5.5 V, which allows it to be used in a
broad range of systems. The 5.5-V I/Os allow down translation and also allow voltages at the inputs when
VCC = 0.
8.4 Device Functional Modes
Table 1 lists the functional modes for SN74LVC1G175.
Table 1. Function Table
INPUTS
10
D
OUTPUT
Q
CLR
CLK
H
↑
L
L
H
↑
H
H
H
H or L
X
Q0
L
X
X
L
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Product Folder Links: SN74LVC1G175
SN74LVC1G175
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SCES560G – MARCH 2004 – REVISED JUNE 2015
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Multiple SN74LVC1G175 devices can be used in tandem to create a shift register of arbitrary length. In this
example, we use four SN74LVC1G175 devices to form a 4-bit serial shift register. By connecting all CLK inputs
to a common clock pulse and tying each output of one device to the next, we can store and load 4-bit values on
demand. We demonstrate loading the 4 bit value 1101 into memory by setting Serial Input Data to each desired
memory bit, and by sending a clock pulse for each bit, we sequentially move all stored bits from left to right
(A → B → C → D)
9.2 Typical Application
VCC = 5 V
Serial
Input Data
Clock
Pulse
D
Q
VCC
D
VCC
Q
D
VCC
Q
SN74LVC1G175
SN74LVC1G175
SN74LVC1G175
A
B
C
CLK
GND
CLK
GND
CLK
D
VCC
Q
Serial
Output Data
SN74LVC1G175
D
GND
CLK
GND
Figure 4. 4-Bit Serial Shift Register
Table 2. Stored Data Values
Serial Input Data
Stored A
Stored B
Stored C
Stored D
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
9.2.1 Design Requirements
The SN74LVC1G175 device uses CMOS technology and has balanced output drive. Care must be taken to
avoid bus contention because it can drive currents that would exceed maximum limits.
The SN74LVC1G175 allows storing digital signals with a digital control signal. All input signals should remain as
close as possible to either 0 V or VCC for optimal operation.
9.2.2 Detailed Design Procedure
1. Recommended input conditions:
– For rise time and fall time specifications, see Δt/Δv in the table.
– For specified high and low levels, see VIH and VIL in the table.
– Inputs and outputs are overvoltage tolerant and can therefore go as high as 5.5 V at any valid VCC.
2. Recommended output conditions:
– Load currents should not exceed ±50 mA.
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11
SN74LVC1G175
SCES560G – MARCH 2004 – REVISED JUNE 2015
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3. Frequency selection criterion:
– The effects of frequency upon the output current should be studied in Figure 5.
– Added trace resistance and capacitance can reduce maximum frequency capability; follow the layout
practices listed in the Layout section.
9.2.3 Application Curve
20.00
tpd from CLR to Q.
CL= 30 pF or 50 pF
–40°C to 125°C
Max tpd (ns)
15.00
10.00
5.00
0.00
0.00
1.00
2.00
3.00
4.00
5.00
Voltage (V)
6.00
7.00
C001
Figure 5. Max tpd vs Voltage of LVC Family
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the
table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If multiple pins are labeled VCC, then a 0.01-μF or 0.022-μF
capacitor is recommended for each VCC because the VCC pins are tied together internally. For devices with dual
supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass capacitor is recommended
for each supply pin. To reject different frequencies of noise, use multiple bypass capacitors in parallel. Capacitors
with values of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close
to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple-bit logic devices, inputs must never float.
In many cases, functions (or parts of functions) of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or when only 3 of the 4 buffer gates are used. Such input pins must
not be left unconnected, because the undefined voltages at the outside connections result in undefined
operational states. Figure 6 specifies the rules that must be observed under all circumstances. All unused inputs
of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that
must be applied to any particular unused input depends on the function of the device. Generally they are tied to
GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs,
unless the part is a transceiver. If the transceiver has an output enable pin, it disables the output section of the
part when asserted, which does not disable the input section of the I/Os. Therefore, the I/Os cannot float when
disabled.
12
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Product Folder Links: SN74LVC1G175
SN74LVC1G175
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SCES560G – MARCH 2004 – REVISED JUNE 2015
11.2 Layout Example
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 6. Layout Diagram
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Product Folder Links: SN74LVC1G175
13
SN74LVC1G175
SCES560G – MARCH 2004 – REVISED JUNE 2015
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Implications of Slow or Floating CMOS Inputs, SCBA004
• Selecting the Right Texas Instruments Signal Switch, SZZA030
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
14
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Product Folder Links: SN74LVC1G175
PACKAGE OPTION ADDENDUM
www.ti.com
4-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
74LVC1G175DBVRE4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(C755, C75R)
74LVC1G175DBVRG4
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(C755, C75R)
74LVC1G175DCKRG4
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D65
74LVC1G175DCKTG4
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D65
SN74LVC1G175DBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(C755, C75R)
SN74LVC1G175DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(C755, C75R)
SN74LVC1G175DCKR
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(D65, D6J, D6R)
SN74LVC1G175DCKT
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(D65, D6J, D6R)
SN74LVC1G175DRYR
ACTIVE
SON
DRY
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D6
SN74LVC1G175YZPR
ACTIVE
DSBGA
YZP
6
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
D6N
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
4-Apr-2019
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1G175 :
• Enhanced Product: SN74LVC1G175-EP
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jan-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
74LVC1G175DCKRG4
Package Package Pins
Type Drawing
SC70
DCK
6
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
178.0
9.2
2.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2.4
1.22
4.0
8.0
Q3
74LVC1G175DCKTG4
SC70
DCK
6
250
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74LVC1G175DBVR
SOT-23
DBV
6
3000
178.0
9.2
3.3
3.23
1.55
4.0
8.0
Q3
SN74LVC1G175DBVT
SOT-23
DBV
6
250
178.0
9.2
3.3
3.23
1.55
4.0
8.0
Q3
SN74LVC1G175DCKR
SC70
DCK
6
3000
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74LVC1G175DCKR
SC70
DCK
6
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
SN74LVC1G175DCKT
SC70
DCK
6
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
SN74LVC1G175DCKT
SC70
DCK
6
250
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74LVC1G175DRYR
SON
DRY
6
5000
179.0
8.4
1.2
1.65
0.7
4.0
8.0
Q1
SN74LVC1G175YZPR
DSBGA
YZP
6
3000
178.0
9.2
1.02
1.52
0.63
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jan-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
74LVC1G175DCKRG4
SC70
DCK
6
3000
180.0
180.0
18.0
74LVC1G175DCKTG4
SC70
DCK
6
250
180.0
180.0
18.0
SN74LVC1G175DBVR
SOT-23
DBV
6
3000
180.0
180.0
18.0
SN74LVC1G175DBVT
SOT-23
DBV
6
250
180.0
180.0
18.0
SN74LVC1G175DCKR
SC70
DCK
6
3000
180.0
180.0
18.0
SN74LVC1G175DCKR
SC70
DCK
6
3000
180.0
180.0
18.0
SN74LVC1G175DCKT
SC70
DCK
6
250
180.0
180.0
18.0
SN74LVC1G175DCKT
SC70
DCK
6
250
180.0
180.0
18.0
SN74LVC1G175DRYR
SON
DRY
6
5000
203.0
203.0
35.0
SN74LVC1G175YZPR
DSBGA
YZP
6
3000
220.0
220.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
6
2X 0.95
1.9
1.45 MAX
3.05
2.75
5
2
4
0.50
6X
0.25
0.2
C A B
3
(1.1)
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X (0.95)
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214840/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X(0.95)
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
YZP0006
DSBGA - 0.5 mm max height
SCALE 9.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.19
0.15
BALL TYP
0.05 C
0.5 TYP
C
SYMM
1
TYP
B
0.5
TYP
D: Max = 1.418 mm, Min =1.358 mm
E: Max = 0.918 mm, Min =0.858 mm
A
6X
0.015
0.25
0.21
C A
B
1
2
SYMM
4219524/A 06/2014
NanoFree Is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
TM
3. NanoFree package configuration.
www.ti.com
EXAMPLE BOARD LAYOUT
YZP0006
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
6X ( 0.225)
1
2
A
(0.5) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
( 0.225)
METAL
0.05 MAX
METAL
UNDER
MASK
0.05 MIN
( 0.225)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4219524/A 06/2014
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017).
www.ti.com
EXAMPLE STENCIL DESIGN
YZP0006
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
6X ( 0.25)
(R0.05) TYP
2
1
A
(0.5)
TYP
SYMM
B
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4219524/A 06/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
GENERIC PACKAGE VIEW
DRY 6
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4207181/G
PACKAGE OUTLINE
DRY0006A
USON - 0.6 mm max height
SCALE 8.500
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
B
A
PIN 1 INDEX AREA
1.5
1.4
C
0.6 MAX
SEATING PLANE
0.05
0.00
0.08 C
3X 0.6
SYMM
(0.127) TYP
(0.05) TYP
3
4
4X
0.5
SYMM
2X
1
1
6
6X
0.4
0.3
PIN 1 ID
(OPTIONAL)
5X
0.25
0.15
0.1
0.05
0.35
0.25
C A B
C
4222894/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DRY0006A
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
6
1
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
LAND PATTERN EXAMPLE
1:1 RATIO WITH PKG SOLDER PADS
EXPOSED METAL SHOWN
SCALE:40X
0.05 MAX
ALL AROUND
EXPOSED
METAL
0.05 MIN
ALL AROUND
EXPOSED
METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222894/A 01/2018
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DRY0006A
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
1
6
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X
4222894/A 01/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
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